KR970054265A - Nonvolatile Memory Device and Manufacturing Method - Google Patents

Nonvolatile Memory Device and Manufacturing Method Download PDF

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Publication number
KR970054265A
KR970054265A KR1019950057119A KR19950057119A KR970054265A KR 970054265 A KR970054265 A KR 970054265A KR 1019950057119 A KR1019950057119 A KR 1019950057119A KR 19950057119 A KR19950057119 A KR 19950057119A KR 970054265 A KR970054265 A KR 970054265A
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KR
South Korea
Prior art keywords
memory device
floating gate
forming
gate
insulating layer
Prior art date
Application number
KR1019950057119A
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Korean (ko)
Inventor
전영진
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950057119A priority Critical patent/KR970054265A/en
Publication of KR970054265A publication Critical patent/KR970054265A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

프로그램 및 소거동작의 속도를 증가시킬 수 있는 비휘발성 메모리장치 및 그 제조방법에 대해 기재되어 있다.A nonvolatile memory device capable of increasing the speed of program and erase operations and a manufacturing method thereof are described.

이는, 플로팅 게이트, 유전체막 및 콘트롤 게이트를 구비하는 메모리장치에 있어서, 상기 플로팅 게이트 양단의 하부에, 그 양단이 상기 플로팅 게이트와 오버랩되는 절연층을 더 구비하는 것을 특징으로 한다.In the memory device having a floating gate, a dielectric layer, and a control gate, the memory device may further include an insulating layer at both ends of the floating gate, the both ends of which overlap the floating gate.

따라서, 터널영역에 대한 유전체막의 면적을 넓히므로써 결과적으로 커플링 비를 증가시켜, 프로그램 및 소거 동작시 속도를 증가시킬 수 있고, 메모리 셀간의 소자분리 특성을 향상시킬 수 있다.Therefore, by increasing the area of the dielectric film with respect to the tunnel region, the coupling ratio can be increased as a result, the speed during program and erase operations can be increased, and device isolation characteristics between memory cells can be improved.

Description

비휘발성 메모리장치 및 그 제조방법Nonvolatile Memory Device and Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 비휘발성 메모리장치를 제조하기 위한 레이아웃도이다.3 is a layout diagram for manufacturing a nonvolatile memory device according to the present invention.

Claims (2)

플로팅 게이트, 유전체막 및 콘트롤 게이트를 구비하는 메모리장치에 있어서, 상기 플로팅 게이트 양단의 하부에, 그 양단이 상기 플로팅 게이트와 오버랩되는 절연층을 더 구비하는 것을 특징으로 하는 비휘발성 메모리장치.A memory device having a floating gate, a dielectric film, and a control gate, the nonvolatile memory device further comprising an insulating layer at both ends of the floating gate, the ends of which overlap the floating gate. 제1도전형의 반도체기판에 필드산화막을 형성하여 활성영역과 비활성영역을 한정하는 단계; 결과를 전면에 절연층을 형성한 후, 상기 필드산화막의 일부를 오버랩하도록 상기 절연층을 패터닝하는 단계; 결과물 상에 게이트산화막을 형성하는 단계; 터널영역 상의 상기 게이트산화막을 제거한 후, 상기 반도체기판에 제2도전형의 불순물이온을 주입하여 터널영역을 형성하는 단계; 상기 터널영역 상의 반도체기판에 터널산화막을 형성하는 단계; 및 상기 플로팅 게이트, 유전체막 콘트롤 게이트를 차례로 형성하는 단계를 포함하는 것을 특징으로 하는 비휘발성 메모리장치의 제조방법.Forming a field oxide film on the first conductive semiconductor substrate to define an active region and an inactive region; After forming an insulating layer on the entire surface, patterning the insulating layer to overlap a part of the field oxide film; Forming a gate oxide film on the resultant; Removing the gate oxide layer on the tunnel region, and implanting impurity ions of a second conductivity type into the semiconductor substrate to form a tunnel region; Forming a tunnel oxide film on the semiconductor substrate on the tunnel region; And sequentially forming the floating gate and the dielectric film control gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950057119A 1995-12-26 1995-12-26 Nonvolatile Memory Device and Manufacturing Method KR970054265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950057119A KR970054265A (en) 1995-12-26 1995-12-26 Nonvolatile Memory Device and Manufacturing Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950057119A KR970054265A (en) 1995-12-26 1995-12-26 Nonvolatile Memory Device and Manufacturing Method

Publications (1)

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KR970054265A true KR970054265A (en) 1997-07-31

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KR1019950057119A KR970054265A (en) 1995-12-26 1995-12-26 Nonvolatile Memory Device and Manufacturing Method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425438B1 (en) * 1997-05-16 2004-09-18 삼성전자주식회사 Method of manufacturing non-volatile memory cell without stringers between adjacent control gate electrodes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425438B1 (en) * 1997-05-16 2004-09-18 삼성전자주식회사 Method of manufacturing non-volatile memory cell without stringers between adjacent control gate electrodes

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