KR950007135A - Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof - Google Patents
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof Download PDFInfo
- Publication number
- KR950007135A KR950007135A KR1019930017549A KR930017549A KR950007135A KR 950007135 A KR950007135 A KR 950007135A KR 1019930017549 A KR1019930017549 A KR 1019930017549A KR 930017549 A KR930017549 A KR 930017549A KR 950007135 A KR950007135 A KR 950007135A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- high concentration
- drain
- gate insulating
- gate electrode
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract 8
- 239000012535 impurity Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 230000014759 maintenance of location Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
Abstract
본 발명은 비휘발성 반도체 메모리장치 및 그 제조방법에 관한 것으로, 제1도전형의 반도체기판에 제1길이를 사이에 두고 서로 이격되어 제2도전형의 고농도 소오스 및 드레인이 형성되고 상기 고농도 소오스 및 드레인 사이에 상기 고농도 소오스 및 드레인 각각으로 부터 상기 제1길이보다 짧은 제2길이를 사이에 두고 격리되어 제2도전형의 고농도 터널접합영역이 형성되고, 상기 고농도 터널접합영역상에 얇은 터널산화막이 형성되고, 상기 고농도 소오스 및 드레인과 상기 고농도 터널접합영역사이의 반도체기판상에 제1게이트절연막이 형성되고, 상기 터널산화막 및 제1게이트절연막상에 제1길이를 갖는 제1게이트전극과 제2게이트절연막 및 제2게이트전극이 형성된 것을 특징으로 하는 비휘발성 반도체 메모리장치를 제공한다.The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein a high concentration source and a drain of a second conductivity type are formed on a semiconductor substrate of a first conductivity type with a first length therebetween to form a high concentration source and a drain. A high concentration tunnel junction region of a second conductivity type is formed between the drains with a second length shorter than the first length therebetween from each of the high concentration source and the drain, and a thin tunnel oxide film is formed on the high concentration tunnel junction region. And a first gate insulating film formed on a semiconductor substrate between the high concentration source and drain and the high concentration tunnel junction region, and a first gate electrode and a second gate electrode having a first length on the tunnel oxide film and the first gate insulating film. Provided is a nonvolatile semiconductor memory device comprising a gate insulating film and a second gate electrode.
본 발명에 의하면, 전하보존(Charge Retention) 특성이 향상되고 데이타독출시의 간섭(Reading interference)을 방지할 수 있으며, 게이트산화막의 두께조절로 프로그램 및 소거동작의 속도를 조절할 수 있고, 또한 미세한 드레인전압으로 독출(Reading)이 가능하게 된다.According to the present invention, the charge retention characteristic can be improved and data interference can be prevented, and the thickness of the gate oxide film can be controlled to control the speed of program and erase operations, and also fine drainage. Reading is possible with voltage.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 의한 EEPTOM셀의 단면구조를 나타낸 도면,2 is a view showing a cross-sectional structure of the EEPTOM cell according to the present invention,
제3도는 본 발명에 의한 EEPROM셀의 프로그램동작을 설명하기 위한 도면,3 is a view for explaining the program operation of the EEPROM cell according to the present invention;
제4도는 본 발명에 의한 EEPROM셀의 수거동작을 설명하기 위한 도면,4 is a view for explaining the collection operation of the EEPROM cell according to the present invention;
제5도는 내지 제8도는 본 발명에 의한 EEPROM셀의 제조방법을 나타낸 공정순서도.5 to 8 are process flowcharts showing a method for manufacturing an EEPROM cell according to the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930017549A KR960014471B1 (en) | 1993-08-31 | 1993-08-31 | Nonvolatile semiconductor memory device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930017549A KR960014471B1 (en) | 1993-08-31 | 1993-08-31 | Nonvolatile semiconductor memory device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950007135A true KR950007135A (en) | 1995-03-21 |
KR960014471B1 KR960014471B1 (en) | 1996-10-15 |
Family
ID=19362757
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930017549A KR960014471B1 (en) | 1993-08-31 | 1993-08-31 | Nonvolatile semiconductor memory device and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960014471B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010078525A (en) * | 1999-12-30 | 2001-08-21 | 박종섭 | Method for manufacturing gate eletrode of EEPROM flash memory |
-
1993
- 1993-08-31 KR KR1019930017549A patent/KR960014471B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010078525A (en) * | 1999-12-30 | 2001-08-21 | 박종섭 | Method for manufacturing gate eletrode of EEPROM flash memory |
Also Published As
Publication number | Publication date |
---|---|
KR960014471B1 (en) | 1996-10-15 |
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