TW202408006A - 碳化矽半導體功率電晶體及其製造方法 - Google Patents
碳化矽半導體功率電晶體及其製造方法 Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 69
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000009413 insulation Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 162
- 230000005684 electric field Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
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Abstract
一種碳化矽半導體功率電晶體及其製造方法。所述碳化矽半導體功率電晶體包括碳化矽基底、第一漂移層、位在基底上具有多個V形槽的第二漂移層、位於V形槽下方的第一漂移層中的埋入式摻雜區、位在V形槽中的閘極、閘極絕緣層、Delta摻雜層、井區、多個源極區、多個井拾取區(well pick-up regions)、導電溝槽以及摻雜部。每個埋入式摻雜區距每個V形槽的底部一預定距離。Delta摻雜層設置於第二漂移層中,且V形槽橫跨Delta摻雜層。導電溝槽設置於第二漂移層中,且各導電溝槽穿過井拾取區與井區接觸。多個摻雜部別位於井區中的導電溝槽的側壁上。
Description
本發明是有關於一種碳化矽半導體功率電晶體技術,且特別是有關於一種碳化矽半導體功率電晶體及其製造方法。
高壓場效電晶體,也稱為功率電晶體或碳化矽半導體功率電晶體,在半導體領域是眾所周知的。垂直功率電晶體包括延伸汲極或漂移區,可在元件處於「關閉」狀態時,支撐所施加的高壓,且這種類型的功率電晶體通常用於電源轉換應用,例如離線電源的AC/DC轉換器、電機控制等。這些功率電晶體元件可以在高電壓下切換,並在「關閉」狀態下實現高阻遏電壓(blocking voltage),同時最大限度地減少汲極和源極之間的電阻,在「開啟」狀態通常稱為比導通電阻(specific on resistance,R
on)。
碳化矽(SiC)MOSFET由於其優於相同元件領域的矽基元件(silicon-based devices)的物理特性而受到高度關注。例如,已知 SiC MOSFET比矽 MOSFET具有更高的阻遏電壓、更低的Ron和更高的熱傳導性。
H-SiC MOSFET是一種具前景的建構模塊,用於低損耗與高壓開關功率模塊。4H-SiC功率MOSFET的主要挑戰之一是同時實現低比導通電阻以及高起始電壓(threshold voltage)。這是因為常用於閘極氧化之後、用以降低通道電阻的氮化製程,常造成較低的起始電壓、而非以高通道遷移率作結。為了克服上述問題,已經研究了一種 4H-SiC (03-38) 通道取向,用於在V形槽上形成 MOSFET的技術。然而,由於V形槽底部的高電場,導致這些MOSFET的低崩潰電壓與低短路電流特性。
本發明提供一種碳化矽半導體功率電晶體,用於在不影響崩潰電壓的情況下降低特定導通電阻(R
on)。
本發明另提供一種製造碳化矽半導體功率電晶體的方法,以降低R
on並且無需複雜的製程步驟。
本發明的一種碳化矽半導體功率電晶體包括由碳化矽製成的基底、第一漂移層、第二漂移層、多個埋入式摻雜區、多個閘極、閘極絕緣層、Delta摻雜層、井區、多個源極區、多個井拾取區、多個導電溝槽以及多個摻雜部。第一漂移層設置於所述基底的平面上,第二漂移層形成於所述第一漂移層上,其中多個V形槽形成於所述第二漂移層中,且V形槽相互平行。埋入式摻雜區設置於所述多個V形槽下方的第一漂移層中,每個埋入式摻雜區與每個V形槽的底部相隔一預定距離。多個閘極設置於所述第二漂移層中的所述多個V形槽中,閘極絕緣層設置於所述第二漂移層和每個閘極之間。Delta摻雜層設置於所述第二漂移層中,且所述多個V形槽橫跨所述Delta摻雜層。井區設置於所述第二漂移層中的所述Delta摻雜層上,多個源極區設置於V形槽之間的井區內,其中源極區與埋入式摻雜區電性連接。井拾取區設置於所述第二漂移層中,且每個井拾取區穿過源極區並與井區接觸。多個導電溝槽設置於所述第二漂移層中,且每個導電溝槽穿過井拾取區並與井區接觸。多個摻雜部別位於所述井區中的導電溝槽的側壁上。
在本發明的一實施例中,上述的基底的上述平面為{0001}面、{11-20}面或{1100}面。
在本發明的一實施例中,上述基底的所述上述平面具有5°以下的離軸定向。
在本發明的一實施例中,每個V形槽的側壁與底部之間的傾斜角為30°至65°。
在本發明的一實施例中,上述基底、上述第一漂移層、上述第二漂移層、上述Delta摻雜層和上述多個源極區具有第一導電類型,且上述井區、上述多個井拾取區、上述摻雜部和上述多個埋入式摻雜區具有第二導電類型。
在本發明的一實施例中,上述Delta摻雜層的摻質選自氮、磷與砷中的至少一種。
在本發明的一實施例中,上述碳化矽半導體功率電晶體中還包括摻雜帶,設置在所述第一漂移層和所述第二漂移層中,以連接所述多個源極區和所述多個埋入式摻雜區。
在本發明的一實施例中,上述摻雜帶的延伸方向垂直於所述V形槽的延伸方向。
在本發明的一實施例中,上述多個閘極對稱設置在上述摻雜帶的兩側。
在本發明的一實施例中,上述井區的摻雜濃度範圍為5E15/cm
3~1E18/cm
3。
在本發明的一實施例中,上述多個埋入式摻雜區的摻雜濃度範圍為5E15/cm
3~1E18/cm
3。
在本發明的一實施例中,每個埋入式摻雜區的寬度是每個V形槽的底部的寬度的1.5至2.0倍。
在本發明的一實施例中,上述第一漂移層中的所述埋入式摻雜區的上表面的深度為0.2μm~1.5μm,且所述預定距離為0.3μm~1μm。
在本發明的一實施例中,上述碳化矽半導體功率電晶體中還包括多個源極電極、多個閘極電極以及汲極電極。上述源極電極設置於第二漂移層上,以與井拾取區與源極區直接接觸。閘極電極設置於閘極上,汲極電極設置於基底的背面。
本發明的一種碳化矽半導體功率電晶體的製造方法,包括在碳化矽基底的上表面上形成第一漂移層;在所述第一漂移層中形成多個埋入式摻雜區,且所述多個埋入式摻雜區相互平行;在所述第一漂移層上形成第二漂移層,覆蓋所述多個埋入式摻雜區;在所述第二漂移層的表面中形成Delta摻雜層;在所述Delta摻雜層上形成摻雜磊晶層作為井區;形成摻雜帶,從所述摻雜磊晶層的表面穿過所述Delta摻雜層到所述多個埋入式摻雜區;在所述摻雜磊晶層的所述表面中形成源極區,其中所述源極區與所述多個埋入式摻雜區通過所述摻雜帶電性連接;在所述多個埋入式摻雜區之間的所述摻雜磊晶層的所述表面中形成多個井拾取區,穿過所述源極區並與所述井區接觸;在所述多個埋入式摻雜區上方的所述摻雜磊晶層以及所述第二漂移層中形成多個V形槽,其中所述多個V形槽穿過所述源極區、所述井區與所述Delta摻雜層,且每個所述埋入式摻雜區與每個所述V形槽的底部相隔一預定距離;在所述第二漂移層中形成多個導電溝槽,以穿過所述多個井拾取區並與所述井區接觸;在所述井區中的所述多個導電溝槽的側壁上形成多個摻雜部;在所述多個V形槽中形成閘極絕緣層;以及在所述閘極絕緣層上形成多個閘極。
在本發明的另一實施例中,在形成上述多個閘極之後,上述方法還包括形成多個源極電極以及形成多個閘極電極,所述源極電極設置於所述摻雜磊晶層上,以直接接觸所述多個井拾取區和所述源極區,且所述閘極電極設置於所述多個閘極上。
在本發明的另一實施例中,在形成上述源極電極以及上述閘極電極之後還包括:在所述碳化矽基底的底表面上形成汲極電極。
在本發明的另一實施例中,上述SiC基底的上述上表面為{0001}面、{11-20}面或{1100}面。
在本發明的另一實施例中,上述SiC基底的上述上表面具有5°以下的離軸定向。
在本發明的另一實施例中,形成上述多個V形槽的步驟包括在每個所述V形槽的側壁與底部之間形成30°至65°的傾斜角。
基於上述,根據本發明的碳化矽半導體功率電晶體,閘極形成在漂移層的V形槽中,而埋入式摻雜區設置在V形槽下方並與每個 V形槽的底部分離。因此,埋入式摻雜區與源極區等電位的情況下,可以屏蔽V形槽底部的閘極絕緣層下方的高電場,並提供額外的電流通路來降低碳化矽半導體功率電晶體的有效JFET電阻(R
JFET)。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
本發明將通過以下實施例配合圖示說明。然而,本發明可以以許多不同的形式來體現,並不應被解釋為限於本文所闡述的實施例。在附圖中,為清楚和具體的目的,各層和區域的尺寸和相對尺寸可能並未按照準確的比例呈現。
圖1A是依照本發明第一實施例的一種碳化矽半導體功率電晶體的剖面示意圖。
請參照圖1A,第一實施例的碳化矽半導體功率電晶體至少包括由碳化矽(SiC)製成的基底100、設置於基底100的平面100a上的第一漂移層102a、形成於所述第一漂移層102a上的第二漂移層102b、設置於第一漂移層102a中的多個埋入式摻雜區104、多個閘極106、閘極絕緣層108、設置於所述第二漂移層102b中的Delta摻雜層110、設置於所述第二漂移層102b中的Delta摻雜層110上的井區112、設置於井區112內的多個源極區114、設置於所述第二漂移層120b中的多個井拾取區116、多個導電溝槽CT以及多個摻雜部DP。在一實施例中,所述基底100的所述平面100a為{0001}面、{11-20}面或{1100}面。再者,所述基底100的所述平面100a具有5°以下的離軸定向,較佳是3°以下的離軸定向。在一實施例中,第一漂移層102a和第二漂移層102b可以通過磊晶生長形成在基底100的所述平面100a上,並且第一漂移層102a和第二漂移層102b可以用作一整個漂移層102。
請繼續參照圖1A,多個V形槽118形成於所述第二漂移層102b中,且V形槽118相互平行,且V形槽118橫跨所述Delta摻雜層110。在一實施例中,每個V形槽118的側壁118a與底部118b之間的傾斜角θ例如30°至65°。此外,為了提高通道遷移率(channel mobility)和高弱反轉臨限(weak inversion threshold),側壁118a可以是(03-38)平面,其代表從(0001)面方向傾斜54.7°的面以及從(1120)面方向傾斜35.3°的面。多個埋入式摻雜區104設置於所述多個V形槽118下方,因此埋入式摻雜區104也是相互平行。每個埋入式摻雜區104與每個V形槽118的底部118b相隔一預定距離d2。源極區114設置於V形槽118之間,其中源極區114與埋入式摻雜區104可經由內連線(未顯示)電性連接,因此埋入式摻雜區104與源極區114等電位(例如0V),可解決V形槽118的底部118b的閘極絕緣層108下方的高電場問題。
在一實施例中,如果埋入式摻雜區104的摻雜濃度高達1E18/cm
3,預定距離d2為0.3μm~1μm,則埋入式PN接面有兩種作用。一種是在V形槽118的底部118b處屏蔽閘極絕緣層108下方的高電場,而無需擔心潛在的p井和埋入式p井打穿問題。另一種是提供額外的電流通路,如圖1B所示。
圖1B繪示出圖1A的碳化矽半導體功率電晶體的開啟狀態,其中省略了一些元件符號以清楚表達碳化矽半導體功率電晶體的電特性。在圖1B中,電流路徑P1和P2可以降低碳化矽半導體功率電晶體的有效JFET電阻(R
JFET),因為R
JFET= R
JFET1// R
JFET2。因此,可以提高碳化矽半導體功率電晶體的可靠性和RDS
on。電流路徑P1是從「源極」直接到汲極124,而電流路徑P2是從「源極」經由埋入式摻雜區104的上表面上的第二漂移層102b到汲極124。
在圖1A中,每個井拾取區116穿過源極區114並與井區112接觸。閘極106設置於所述第二漂移層102b中的V形槽118中,閘極絕緣層108設置於所述第二漂移層102b和每個閘極106之間。舉例來說,閘極106為多晶矽並且共形沉積於各V形槽118的側壁118a和底部118b上。例如,閘極絕緣層108的厚度範圍為250 Å至1000 Å。 閘極106可延伸至V形槽118外的第二漂移層102b的頂部,但本發明不以此為限。在其他實施例中,閘極106可以不延伸到第二漂移層102b的頂部。在第一實施例中,每個埋入式摻雜區104的寬度w1是每個V形槽118的底部118b的寬度w2的1.5至2.0倍。用語「寬度」是指在基底100的剖面圖中埋入式摻雜區104或底部118b的兩側邊之間的距離。在一實施例中,每個埋入式摻雜區104的寬度w1例如是1 µm至1.5 µm,每個V形槽118的底部118b的寬度w2例如是0.1 µm至0.6 µm。在本發明的一實施例中,第一漂移層102a中的埋入式摻雜區104的上表面104a的深度d1為0.2μm~1.5μm,預定距離d2為0.3μm~1μm。導電溝槽CT設置於第二漂移層102b中,且每個導電溝槽CT穿過井拾取區116並與井區112接觸,其中各導電溝槽CT由導電材料製成,以降低碳化矽半導體功率電晶體的潛在回彈效應(potential snapback effect)。碳化矽半導體功率電晶體的回彈是有害的,可能會造成永久性損壞。摻雜部DP分別位於井區112中的導電溝槽CT的側壁上,以提高導電溝槽CT與井區112之間的導電性。如圖1A所示,摻雜部DP可以進一步位於導電溝槽CT的底部下方。
所述基底100、所述第一漂移層102a、所述第二漂移層102b、所述Delta摻雜層110和所述源極區114具有第一導電類型,所述井區112、所述井拾取區116、所述摻雜部DP和所述埋入式摻雜區104具有第二導電類型。舉例來說,基底100、第一漂移層102a、第二漂移層102b、Delta摻雜層110和源極區114是N型,井區112、井拾取區116、摻雜部DP和埋入式摻雜區104是P型。所述多個埋入式摻雜區104的摻雜濃度範圍例如5E15/cm
3~1E18/cm
3。所述井區112的摻雜濃度範圍例如5E15/cm
3~1E18/cm
3,且所述井區112的厚度(或深度)例如0.5μm~1.5μm。所述源極區114的摻雜濃度範圍例如1E17/cm
3~1E19/cm
3。所述井拾取區116的摻雜濃度範圍例如1E18/cm
3~2E20/cm
3。所述Delta摻雜層110的摻雜濃度範圍例如1E19/cm
3~5E19/cm
3。
此外,Delta摻雜層110可以有效地限制p井(如井區112)的接面輪廓變化,其由量產中的模糊的內在和外在的缺陷所引起。Delta摻雜層110中的摻質例如是選自氮(N)、磷(P)與砷(As)中的至少一種。Delta摻雜層110的厚度例如1000 Å至3000 Å,Delta摻雜層110的摻雜濃度例如1E17/cm
3至5E18/cm
3。
在第一實施例中,碳化矽半導體功率電晶體還包括多個源極電極120、多個閘極電極122與汲極電極124。源極電極120設置於所述第二漂移層120b上,以與井拾取區116與源極區114直接接觸。閘極電極122設置於所述閘極106上,汲極電極124設置於所述基底100的背面。
在本實施例中,源極區114與埋入式摻雜區104電性連接。 例如,埋入式摻雜區104通過摻雜帶200連接到碳化矽半導體功率電晶體的V
SS節點。如圖1A的平面圖圖2所示,形成有摻雜帶200以連接多個源極區114和多個埋入式摻雜區104,其中一些元件在圖2中被省略,以闡明埋入式摻雜區104、源極區114、閘極電極122等的位置關係。摻雜帶200也可設置在漂移層102(第一漂移層102a和第二漂移層102b)中,如圖3所示,其為沿圖2的III-III線段的剖面示意圖。摻雜帶200可以在源極區114形成之前摻雜在井區112中。摻雜帶200的摻雜濃度例如2E19/cm
3至1E20/cm
3。
在圖2中,所述摻雜帶200的延伸方向垂直於多個閘極122的延伸方向,閘極122可設計為對稱設置在所述摻雜帶200的兩側S1和S2。換言之,摻雜帶200的延伸方向垂直於閘極122下方的V形槽(118)的延伸方向。因此,摻雜帶200不會影響圖1B中第一漂移層102a中的電流流動。也就是說,V形槽底部不存在電場擁擠問題。摻雜帶200在圖2中是連續區,但本發明不限於此;在另一個實施例中,摻雜帶200可以分成幾個從圖2的上到下分佈的子區,且每個子區連接多個源極區114和多個埋入式摻雜區104之一。
圖4A至圖4I是依照本發明第二實施例的一種碳化矽半導體功率電晶體的製造方法的步驟的剖面示意圖。
請參照圖4A,使用碳化矽(SiC)基底400,並且所述SiC基底400可以是n型基底。第一漂移層402形成在SiC基底400的上表面400a上,所述第一漂移層402可以是N-漂移層,其中所述第一漂移層402的摻雜濃度範圍例如5E14/cm
3~1E17/cm
3,且所述第一漂移層402的厚度例如4 μm~20 μm。然而本發明不以此為限。所述SiC基底400的上表面400a可為{0001}面、{11-20}面或{1100}面。所述SiC基底400的上表面400a可具有5°以下的離軸定向。在所述第一漂移層402中形成多個埋入式摻雜區404,且所述多個埋入式摻雜區404相互平行。形成埋入式摻雜區404的方法可以是使用覆蓋部分第一漂移層402的圖案化光阻(未示出)的摻雜步驟。
然後,請參照圖4B,在所述第一漂移層402上形成第二漂移層406,覆蓋所述多個埋入式摻雜區404,且第二漂移層406的摻雜濃度可以與第一漂移層402的摻雜濃度相同或更高。在一實施例中,由於埋入式摻雜區404的存在,第二漂移層406的摻雜濃度可以是第一漂移層402的摻雜濃度的1.2至3倍。所述第二漂移層406的厚度例如1 μm~3 μm。然後,在所述第二漂移層406的表面406a中全面形成Delta摻雜層408。Delta摻雜層408的厚度例如1000 Å至3000 Å,且Delta摻雜層408的摻雜濃度例如1E17/cm
3至5E18/cm
3。Delta摻雜層408的摻質例如是選自氮(N)、磷(P)與砷(As)中的至少一種。
此後,請參照圖4C,在所述Delta摻雜層408上形成摻雜磊晶層410作為井區(well region),其中所述井區(即,摻雜磊晶層410)的摻雜濃度範圍例如5E15/cm
3~1E18/cm
3,且所述井區的厚度(或深度)例如0.5μm~1.5μm。然而本發明不以此為限。然後,在形成摻雜帶(A strap of doped region)500,從所述摻雜磊晶層410的表面410a到所述多個埋入式摻雜區410,如圖5所示。在第二實施例中,摻雜磊晶層410是P型,摻雜帶500也是P型。形成摻雜帶500的方法可以是使用覆蓋部分摻雜磊晶層410的圖案化光阻(未示出)的摻雜步驟。摻雜帶500的摻雜濃度例如2E19/cm
3至1E20/cm
3。在圖5中,摻雜帶500延伸至埋入式摻雜區404,但本發明不以此為限。在另一個實施例中,摻雜帶500可以僅形成在第二漂移層406中並且與第一漂移層402的頂部直接接觸。
然後,請參照圖4D,在所述摻雜磊晶層410的所述表面410a中形成源極區412,其中所述源極區412與所述埋入式摻雜區404通過圖5所示的摻雜帶500電性連接。所述源極區412的摻雜濃度範圍例如1E17/cm
3~1E19/cm
3。
之後,請參照圖4E,在所述埋入式摻雜區404之間的所述摻雜磊晶層410的所述表面410a中形成多個井拾取區414,使得井拾取區414穿過源極區412並與井區(即,摻雜磊晶層410)接觸。所述井拾取區414的摻雜濃度範圍例如1E18/cm
3~2E20/cm
3。形成井拾取區414的方法可以是使用覆蓋部分表面410a的圖案化光阻(未示出)的摻雜步驟。
然後,請參照圖4F,在所述多個埋入式摻雜區404上方的摻雜磊晶層410以及第二漂移層406中形成多個V形槽416,其中所述V形槽416穿過所述源極區412、所述井區(即,摻雜磊晶層410)與所述Delta摻雜層408。每個埋入式摻雜區404與每個V形槽416的底部416b相隔一預定距離d2。而形成所述V形槽416的步驟例如在每個V形槽416的側壁416a與底部416b之間形成30°至65°的傾斜角θ。從 MOSFET RDS
on的角度來看,(03-38)面的通道取向對反轉臨限電壓和通道遷移率有正面影響,因此側壁416a可以是(03-38)面。側壁118a可以是(03-38)面。所述(03-38)面代表從(0001)面方向傾斜54.7°的面以及從(1120)面方向傾斜35.3°的面。
隨後,請參照圖4G,在所述第二漂移層406中形成多個導電溝槽CT,以穿過所述井拾取區414並與所述井區(即,摻雜磊晶層410)接觸。然後,在所述摻雜磊晶層410中的多個導電溝槽CT的側壁上形成多個摻雜部DP。具體而言,可以通過蝕刻第二漂移層406以形成多個凹槽並暴露摻雜磊晶層410的一部分,再執行摻雜步驟以在所述凹槽的側壁上形成所述摻雜部DP,然後在所述凹槽中填充導電材料,以形成所述多個導電溝槽CT。在一實施例中,摻雜部DP的摻雜步驟可以使用1.2MeV Al植入,且所述摻雜部DP的摻雜濃度範圍例如1E19/cm
3~5E19/cm
3。在形成多個導電溝槽CT和多個摻雜部DP的步驟中,可以用保護層(未示出)覆蓋除了導電溝槽CT的位置之外的V形槽416和表面410a。同時,所述多個導電溝槽CT和所述多個摻雜部DP也可形成在摻雜帶500上方,如(沿著與圖5相同的剖面線的)圖6所示。
之後,請參照圖4H,在每個V形槽416中形成閘極絕緣層418以及在所述閘極絕緣層418上形成多個閘極420。閘極絕緣層418可以是厚度為250埃至1000埃的閘極氧化層。形成閘極絕緣層418和閘極420的方法可包括依次形成整層閘極氧化層和多晶矽層,然後使用覆蓋V形槽416的圖案化光阻(未示出)作為蝕刻掩模,蝕刻上述多晶矽層和閘極氧化層。在圖4H中,閘極420延伸至V形槽416之外的源極區412的頂部,但本發明不以此為限。在其它實施例中,閘極420可以不延伸到源極區412的頂部。
接著,請參照圖4I,同時形成多個源極電極422以及多個閘極電極424。所述源極電極422設置於所述摻雜磊晶層410的表面410a上,以直接接觸所述多個井拾取區414和所述源極區412,且所述閘極電極424設置於所述多個閘極420上。形成源極電極422和閘極電極424的方法可包括在摻雜磊晶層410的表面410a上先形成絕緣層426,蝕刻所述絕緣層426以形成分別暴露井拾取區414、源極412與閘極420的多個開口,並在所述多個開口中沉積導電材料(例如金屬或合金)。在形成所述源極電極422以及所述閘極電極424之後,在所述SiC基底400的底表面400b上形成汲極電極428。
綜上所述,根據本發明的碳化矽半導體功率電晶體,在閘極下方的漂移層中設有埋入式摻雜區。由於埋入式摻雜區與形成閘極的V形槽底部相距預定距離,因此可以解決V形槽底部下方的高電場問題。此外,埋入式摻雜區能提供額外的電流通路,以降低有效 JFET 電阻,從而在不影響崩潰電壓的情況下降低比導通電阻(R
on),從而獲得良好的可靠性。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、400:基底
100a:平面
102:漂移層
102a、402:第一漂移層
102b、406:第二漂移層
104、404:埋入式摻雜區
104a:上表面
106、420:閘極
108、418:閘極絕緣層
110、408:Delta摻雜層
112、410:井區
114、412:源極區
116、414:井拾取區
118、416:V形槽
118a、416a:側壁
118b、416b:底部
120、422:源極電極
122、424:閘極電極
124、428:汲極電極
200、500:摻雜帶
400a:上表面
400b:底表面
406a、410a:表面
426:絕緣層
CT:導電溝槽
d1:深度
d2:預定距離
DP:摻雜部
P1、P2:電流路徑
S1、S2:兩側
w1、w2:寬度
θ:傾斜角
圖1A是依照本發明第一實施例的一種碳化矽半導體功率電晶體的剖面示意圖。
圖1B繪示出圖1A的碳化矽半導體功率電晶體的開啟狀態。
圖2是圖1A的碳化矽半導體功率電晶體的平面圖。
圖3是沿圖2的III-III線段的剖面示意圖。
圖4A至圖4I是依照本發明第二實施例的一種碳化矽半導體功率電晶體的製造方法的步驟的剖面示意圖。
圖5是表示圖4C沿不同的剖面線的一種步驟的剖面示意圖。
圖6是表示圖4G沿不同的剖面線的一種步驟的剖面示意圖。
100:基底
100a:平面
102:漂移層
102a:第一漂移層
102b:第二漂移層
104:埋入式摻雜區
104a:上表面
106:閘極
108:閘極絕緣層
110:Delta摻雜層
112:井區
114:源極區
116:井拾取區
118:V形槽
118a:側壁
118b:底部
120:源極電極
122:閘極電極
124:汲極電極
CT:導電溝槽
d1:深度
d2:預定距離
DP:摻雜部
w1、w2:寬度
θ:傾斜角
Claims (20)
- 一種碳化矽半導體功率電晶體,包括: 基底,由碳化矽製成; 第一漂移層,設置於所述基底的平面上; 第二漂移層,形成於所述第一漂移層上,其中多個V形槽形成於所述第二漂移層中,且所述多個V形槽相互平行; 多個埋入式摻雜區,設置於所述多個V形槽下方的所述第一漂移層中,每個所述埋入式摻雜區與每個所述V形槽的底部相隔一預定距離; 多個閘極,設置於所述第二漂移層中的所述多個V形槽中; 閘極絕緣層,設置於所述第二漂移層和每個所述閘極之間; Delta摻雜層,設置於所述第二漂移層中,且所述多個V形槽橫跨所述Delta摻雜層; 井區,設置於所述第二漂移層中的所述Delta摻雜層上; 多個源極區,設置於所述多個V形槽之間的所述井區內,其中所述多個源極區與所述多個埋入式摻雜區電性連接; 多個井拾取區,設置於所述第二漂移層中,且每個所述井拾取區穿過所述多個源極區並與所述井區接觸; 多個導電溝槽,設置於所述第二漂移層中,且每個所述導電溝槽穿過所述多個井拾取區並與所述井區接觸;以及 多個摻雜部,分別位於所述井區中的所述多個導電溝槽的側壁上。
- 如請求項1所述的碳化矽半導體功率電晶體,其中所述基底的所述平面為{0001}面、{11-20}面或{1100}面。
- 如請求項1所述的碳化矽半導體功率電晶體,其中所述基底的所述平面具有具有5°以下的離軸定向。
- 如請求項1所述的碳化矽半導體功率電晶體,其中每個所述V形槽的側壁與所述底部之間的傾斜角為30°至65°。
- 如請求項1所述的碳化矽半導體功率電晶體,其中所述基底、所述第一漂移層、所述第二漂移層、所述Delta摻雜層和所述多個源極區具有第一導電類型,且所述井區、所述多個井拾取區、所述摻雜部和所述多個埋入式摻雜區具有第二導電類型。
- 如請求項1所述的碳化矽半導體功率電晶體,其中所述Delta摻雜層的摻質選自氮、磷與砷中的至少一種。
- 如請求項1所述的碳化矽半導體功率電晶體,更包括摻雜帶,設置在所述第一漂移層和所述第二漂移層中,以連接所述多個源極區和所述多個埋入式摻雜區。
- 如請求項7所述的碳化矽半導體功率電晶體,其中所述摻雜帶的延伸方向垂直於所述V形槽的延伸方向。
- 如請求項8所述的碳化矽半導體功率電晶體,其中所述多個閘極對稱設置在所述摻雜帶的兩側。
- 如請求項1所述的碳化矽半導體功率電晶體,其中所述井區的摻雜濃度範圍為5E15/cm 3~1E18/cm 3。
- 如請求項1所述的碳化矽半導體功率電晶體,其中所述多個埋入式摻雜區的摻雜濃度範圍為5E15/cm 3~1E18/cm 3。
- 如請求項1所述的碳化矽半導體功率電晶體,其中每個所述埋入式摻雜區的寬度是每個所述V形槽的所述底部的寬度的1.5至2.0倍。
- 如請求項1所述的碳化矽半導體功率電晶體,其中所述第一漂移層中的所述埋入式摻雜區的上表面的深度為0.2μm~1.5μm,且所述預定距離為0.3μm~1μm。
- 如請求項1所述的碳化矽半導體功率電晶體,更包括: 多個源極電極,設置於所述第二漂移層上,以與所述多個井拾取區與所述多個源極區直接接觸; 多個閘極電極,設置於所述多個閘極上;以及 汲極電極,設置於所述基底的背面。
- 一種碳化矽半導體功率電晶體的製造方法,包括: 在碳化矽基底的上表面上形成第一漂移層; 在所述第一漂移層中形成多個埋入式摻雜區,且所述多個埋入式摻雜區相互平行; 在所述第一漂移層上形成第二漂移層,覆蓋所述多個埋入式摻雜區; 在所述第二漂移層的表面中形成Delta摻雜層; 在所述Delta摻雜層上形成摻雜磊晶層作為井區; 形成摻雜帶,從所述摻雜磊晶層的表面穿過所述Delta摻雜層到所述多個埋入式摻雜區; 在所述摻雜磊晶層的所述表面中形成源極區,其中所述源極區與所述多個埋入式摻雜區通過所述摻雜帶電性連接; 在所述多個埋入式摻雜區之間的所述摻雜磊晶層的所述表面中形成多個井拾取區,穿過所述源極區並與所述井區接觸; 在所述多個埋入式摻雜區上方的所述摻雜磊晶層以及所述第二漂移層中形成多個V形槽,其中所述多個V形槽穿過所述源極區、所述井區與所述Delta摻雜層,且每個所述埋入式摻雜區與每個所述V形槽的底部相隔一預定距離; 在所述第二漂移層中形成多個導電溝槽,以穿過所述多個井拾取區並與所述井區接觸; 在所述井區中的所述多個導電溝槽的側壁上形成多個摻雜部; 在所述多個V形槽中形成閘極絕緣層;以及 在所述閘極絕緣層上形成多個閘極。
- 如請求項15所述的碳化矽半導體功率電晶體的製造方法,其中在形成所述多個閘極之後,更包括:形成多個源極電極以及形成多個閘極電極,所述源極電極設置於所述摻雜磊晶層上,以直接接觸所述多個井拾取區和所述源極區,且所述閘極電極設置於所述多個閘極上。
- 如請求項16所述的碳化矽半導體功率電晶體的製造方法,其中在形成所述源極電極以及所述閘極電極之後,更包括:在所述碳化矽基底的底表面上形成汲極電極。
- 如請求項15所述的碳化矽半導體功率電晶體的製造方法,其中所述碳化矽基底的所述上表面為{0001}面、{11-20}面或{1100}面。
- 如請求項15所述的碳化矽半導體功率電晶體的製造方法,其中所述碳化矽基底的所述上表面具有5°以下的離軸定向。
- 如請求項15所述的碳化矽半導體功率電晶體的製造方法,其中形成所述多個V形槽的步驟包括在每個所述V形槽的側壁與所述底部之間形成30°至65°的傾斜角。
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