CN117577681A - 碳化硅半导体功率晶体管及其制造方法 - Google Patents

碳化硅半导体功率晶体管及其制造方法 Download PDF

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CN117577681A
CN117577681A CN202211260696.2A CN202211260696A CN117577681A CN 117577681 A CN117577681 A CN 117577681A CN 202211260696 A CN202211260696 A CN 202211260696A CN 117577681 A CN117577681 A CN 117577681A
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doped
silicon carbide
regions
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drift layer
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陈伟梵
蔡国基
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Leap Semiconductor Corp
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Abstract

本发明提供一种碳化硅半导体功率晶体管及其制造方法。所述碳化硅半导体功率晶体管包括碳化硅衬底、第一漂移层、位在衬底上具有多个V形槽的第二漂移层、位于V形槽下方的第一漂移层中的掩埋掺杂区、位在V形槽中的栅极、栅极绝缘层、Delta掺杂层、阱区、多个源极区、多个阱拾取区(well pick‑up regions)、导电沟槽以及掺杂部。每个掩埋掺杂区距每个V形槽的底部一预定距离。Delta掺杂层设置于第二漂移层中，且V形槽横跨Delta掺杂层。导电沟槽设置于第二漂移层中，且各导电沟槽穿过阱拾取区与阱区接触。多个掺杂部分别位于阱区中的导电沟槽的侧壁上。

Description

碳化硅半导体功率晶体管及其制造方法
技术领域
本发明涉及一种碳化硅半导体功率晶体管，尤其涉及一种碳化硅半导体功率晶体管及其制造方法。
背景技术
高压场效晶体管，也称为功率晶体管或碳化硅半导体功率晶体管，在半导体领域是众所周知的。垂直功率晶体管包括延伸漏极或漂移区，可在器件处于“关闭”状态时，支撑所施加的高压，且这种类型的功率晶体管通常用于电源转换应用，例如离线电源的AC/DC转换器、电机控制等。这些功率晶体管器件可以在高电压下切换，并在“关闭”状态下实现高阻断电压(blocking voltage)，同时最大限度地减少漏极和源极之间的电阻，在“开启”状态通常称为比导通电阻(specific on resistance，Ron)。
碳化硅(SiC)MOSFET由于其优于相同器件领域的硅基器件(silicon-baseddevices)的物理特性而受到高度关注。例如，已知SiC MOSFET比硅MOSFET具有更高的阻断电压、更低的Ron和更高的热传导率。
4H-SiC MOSFET是一种具前景的构建块，用于低损耗与高压开关功率模块。4H-SiC功率MOSFET的主要挑战之一是同时实现低比导通电阻以及高阈值电压(thresholdvoltage)。这是因为常用于栅极氧化之后、用以降低沟道电阻的氮化工艺，常造成较低的阈值电压、而非以高沟道迁移率作结。为了克服上述问题，已经研究了一种4H-SiC(03-38)沟道取向，用于在V形槽上形成MOSFET的技术。然而，由于V形槽底部的高电场，导致这些MOSFET的低击穿电压与低短路电流特性。
发明内容
本发明是针对一种碳化硅半导体功率晶体管，用于在不影响击穿电压的情况下降低特定导通电阻(Ron)。
本发明另针对一种碳化硅半导体功率晶体管的制造方法，以降低Ron并且无需复杂的工艺步骤。
根据本发明的实施例，一种碳化硅半导体功率晶体管包括由碳化硅制成的衬底、第一漂移层、第二漂移层、多个掩埋掺杂区、多个栅极、栅极绝缘层、Delta掺杂层、阱区、多个源极区、多个阱拾取区、多个导电沟槽以及多个掺杂部。第一漂移层设置于所述衬底的平面上，第二漂移层形成于所述第一漂移层上，其中多个V形槽形成于所述第二漂移层中，且V形槽相互平行。掩埋掺杂区设置于所述多个V形槽下方的第一漂移层中，每个掩埋掺杂区与每个V形槽的底部相隔一预定距离。多个栅极设置于所述第二漂移层中的所述多个V形槽中，栅极绝缘层设置于所述第二漂移层和每个栅极之间。Delta掺杂层设置于所述第二漂移层中，且所述多个V形槽横跨所述Delta掺杂层。阱区设置于所述第二漂移层中的所述Delta掺杂层上，多个源极区设置于V形槽之间的阱区内，其中源极区与掩埋掺杂区电连接。阱拾取区设置于所述第二漂移层中，且每个阱拾取区穿过源极区并与阱区接触。多个导电沟槽设置于所述第二漂移层中，且每个导电沟槽穿过阱拾取区并与阱区接触。多个掺杂部分别位于所述阱区中的导电沟槽的侧壁上。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述衬底的所述平面为{0001}面、{11-20}面或{1100}面。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述衬底的所述平面具有5°以下的离轴取向。
在根据本发明的实施例的碳化硅半导体功率晶体管中，每个V形槽的侧壁与底部之间的倾斜角为30°至65°。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述衬底、所述第一漂移层、所述第二漂移层、所述Delta掺杂层和所述多个源极区具有第一导电类型，且所述阱区、所述多个阱拾取区、所述掺杂部DP和所述多个掩埋掺杂区具有第二导电类型。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述Delta掺杂层的掺杂剂选自氮、磷与砷中的至少一种。
在根据本发明的实施例的碳化硅半导体功率晶体管中，还包括掺杂带，设置在所述第一漂移层和所述第二漂移层中，以连接所述多个源极区和所述多个掩埋掺杂区。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述掺杂带的延伸方向垂直于所述V形槽的延伸方向。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述多个栅极对称设置在所述掺杂带的两侧。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述阱区的掺杂浓度范围为5E15/cm3～1E18/cm3。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述多个掩埋掺杂区的掺杂浓度范围为5E15/cm3～1E18/cm3。
在根据本发明的实施例的碳化硅半导体功率晶体管中，每个掩埋掺杂区的宽度是每个V形槽的底部的宽度的1.5至2.0倍。
在根据本发明的实施例的碳化硅半导体功率晶体管中，所述第一漂移层中的所述掩埋掺杂区的上表面的深度为0.2μm～1.5μm，且所述预定距离为0.3μm～1μm。
在根据本发明的实施例的碳化硅半导体功率晶体管中，还包括多个源极电极、多个栅极电极与漏极电极。源极电极设置于所述第二漂移层上，以与阱拾取区与源极区直接接触。栅极电极设置于所述栅极上，漏极电极设置于所述衬底的背面。
根据本发明的另一实施例，一种碳化硅半导体功率晶体管的制造方法，包括：在碳化硅衬底的上表面上形成第一漂移层；在所述第一漂移层中形成多个掩埋掺杂区，且所述多个掩埋掺杂区相互平行；在所述第一漂移层上形成第二漂移层，覆盖所述多个掩埋掺杂区；在所述第二漂移层的表面中形成Delta掺杂层；在所述Delta掺杂层上形成掺杂外延层作为阱区；形成掺杂带，从所述掺杂外延层的表面穿过所述Delta掺杂层到所述多个掩埋掺杂区；在所述掺杂外延层的所述表面中形成源极区，其中所述源极区与所述多个掩埋掺杂区通过所述掺杂带电连接；在所述多个掩埋掺杂区之间的所述掺杂外延层的所述表面中形成多个阱拾取区，穿过所述源极区并与所述阱区接触；在所述多个掩埋掺杂区上方的所述掺杂外延层以及所述第二漂移层中形成多个V形槽，其中所述多个V形槽穿过所述源极区、所述阱区与所述Delta掺杂层，且每个所述掩埋掺杂区与每个所述V形槽的底部相隔一预定距离；在所述第二漂移层中形成多个导电沟槽，以穿过所述多个阱拾取区并与所述阱区接触；在所述阱区中的所述多个导电沟槽的侧壁上形成多个掺杂部；在所述多个V形槽中形成栅极绝缘层；以及在所述栅极绝缘层上形成多个栅极。
在根据本发明的另一实施例的制造方法中，在形成所述多个栅极之后还包括：形成多个源极电极以及形成多个栅极电极，所述源极电极设置于所述掺杂外延层上，以直接接触所述多个阱拾取区和所述源极区，且所述栅极电极设置于所述多个栅极上。
在根据本发明的另一实施例的制造方法中，在形成所述源极电极以及所述栅极电极之后还包括：在所述碳化硅衬底的底表面上形成漏极电极。
在根据本发明的另一实施例的制造方法中，所述碳化硅衬底的所述上表面为{0001}面、{11-20}面或{1100}面。
在根据本发明的另一实施例的制造方法中，所述碳化硅衬底的所述上表面具有5°以下的离轴取向。
在根据本发明的另一实施例的制造方法中，形成所述多个V形槽的步骤包括在每个所述V形槽的侧壁与所述底部之间形成30°至65°的倾斜角。
基于上述，根据本发明的碳化硅半导体功率晶体管，栅极形成在漂移层的V形槽中，而掩埋掺杂区设置在V形槽下方并与每个V形槽的底部分离。因此，掩埋掺杂区与源极区等电位的情况下，可以屏蔽V形槽底部的栅极绝缘层下方的高电场，并提供额外的电流通路来降低碳化硅半导体功率晶体管的有效JFET电阻(RJFET)。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例详细说明如下。
附图说明
图1A是依照本发明第一实施例的一种碳化硅半导体功率晶体管的截面示意图；
图1B绘示出图1A的碳化硅半导体功率晶体管的开启状态；
图2是图1A的碳化硅半导体功率晶体管的平面图；
图3是沿图2的III-III线段的截面示意图；
图4A至图4I是依照本发明第二实施例的一种碳化硅半导体功率晶体管的制造方法的步骤的截面示意图；
图5是表示图4C沿不同的截面线的一种步骤的截面示意图；
图6是表示图4G沿不同的截面线的一种步骤的截面示意图。
附图标记说明
100、400：衬底
100a：平面
102：漂移层
102a、402：第一漂移层
102b、406：第二漂移层
104、404：掩埋掺杂区
104a：上表面
106、420：栅极
108、418：栅极绝缘层
110、408：Delta掺杂层
112、410：阱区
114、412：源极区
116、414：阱拾取区
118、416：V形槽
118a、416a：侧壁
118b、416b：底部
120、422：源极电极
122、424：栅极电极
124、428：漏极电极
200、500：掺杂带
400a：上表面
400b：底表面
406a、410a：表面
426：绝缘层
CT：导电沟槽
d1：深度
d2：预定距离
DP：掺杂部
P1、P2：电流路径
S1、S2：两侧
w1、w2：宽度
θ：倾斜角
具体实施方式
本发明将通过以下实施例配合图示说明。然而，本发明可以以许多不同的形式来体现，并不应被解释为限于本文所阐述的实施例。在附图中，为清楚和具体的目的，各层和区域的尺寸和相对尺寸可能并未按照准确的比例呈现。
图1A是依照本发明第一实施例的一种碳化硅半导体功率晶体管的截面示意图。
请参照图1A，第一实施例的碳化硅半导体功率晶体管至少包括由碳化硅(SiC)制成的衬底100、设置于衬底100的平面100a上的第一漂移层102a、形成于所述第一漂移层102a上的第二漂移层102b、设置于第一漂移层102a中的多个掩埋掺杂区104、多个栅极106、栅极绝缘层108、设置于所述第二漂移层102b中的Delta掺杂层110、设置于所述第二漂移层102b中的Delta掺杂层110上的阱区112、设置于阱区112内的多个源极区114、设置于所述第二漂移层120b中的多个阱拾取区116、多个导电沟槽CT以及多个掺杂部DP。在一实施例中，所述衬底100的所述平面100a为{0001}面、{11-20}面或{1100}面。再者，所述衬底100的所述平面100a具有5°以下的离轴取向，较佳是3°以下的离轴取向。在一实施例中，第一漂移层102a和第二漂移层102b可以通过外延生长形成在衬底100的所述平面100a上，并且第一漂移层102a和第二漂移层102b可以用作一整个漂移层102。
请继续参照图1A，多个V形槽118形成于所述第二漂移层102b中，且V形槽118相互平行，且V形槽118横跨所述Delta掺杂层110。在一实施例中，每个V形槽118的侧壁118a与底部118b之间的倾斜角θ例如30°至65°。此外，为了提高沟道迁移率(channel mobility)和高弱反转阈值(weak inversion threshold)，侧壁118a可以是(03-38)平面，其代表从(0001)面方向倾斜54.7°的面以及从(1120)面方向倾斜35.3°的面。多个掩埋掺杂区104设置于所述多个V形槽118下方，因此掩埋掺杂区104也是相互平行。每个掩埋掺杂区104与每个V形槽118的底部118b相隔一预定距离d2。源极区114设置于V形槽118之间，其中源极区114与掩埋掺杂区104可经由互连(未显示)电连接，因此掩埋掺杂区104与源极区114等电位(例如0V)，可解决V形槽118的底部118b的栅极绝缘层108下方的高电场问题。
在一实施例中，如果掩埋掺杂区104的掺杂浓度高达1E18/cm3，预定距离d2为0.3μm～1μm，则埋入式PN结有两种作用。一种是在V形槽118的底部118b处屏蔽栅极绝缘层108下方的高电场，而无需担心潜在的p阱和埋入式p阱打穿问题。另一种是提供额外的电流通路，如图1B所示。
图1B绘示出图1A的碳化硅半导体功率晶体管的开启状态，其中省略了一些附图标记以清楚表达碳化硅半导体功率晶体管的电特性。在图1B中，电流路径P1和P2可以降低碳化硅半导体功率晶体管的有效JFET电阻(RJFET)，因为RJFET＝RJFET1//RJFET2。因此，可以提高碳化硅半导体功率晶体管的可靠性和RDSon。电流路径P1是从“源极”直接到漏极124，而电流路径P2是从“源极”经由掩埋掺杂区104的上表面上的第二漂移层102b到漏极124。
在图1A中，每个阱拾取区116穿过源极区114并与阱区112接触。栅极106设置于所述第二漂移层102b中的V形槽118中，栅极绝缘层108设置于所述第二漂移层102b和每个栅极106之间。举例来说，栅极106为多晶硅并且共形沉积于各V形槽118的侧壁118a和底部118b上。例如，栅极绝缘层108的厚度范围为至/>栅极106可延伸至V形槽118外的第二漂移层102b的顶部，但本发明不以此为限。在其他实施例中，栅极106可以不延伸到第二漂移层102b的顶部。在第一实施例中，每个掩埋掺杂区104的宽度w1是每个V形槽118的底部118b的宽度w2的1.5至2.0倍。术语“宽度”是指在衬底100的截面图中掩埋掺杂区104或底部118b的两侧边之间的距离。在一实施例中，每个掩埋掺杂区104的宽度w1例如是1μm至1.5μm，每个V形槽118的底部118b的宽度w2例如是0.1μm至0.6μm。在本发明的一实施例中，第一漂移层102a中的掩埋掺杂区104的上表面104a的深度d1为0.2μm～1.5μm，预定距离d2为0.3μm～1μm。导电沟槽CT设置于第二漂移层102b中，且每个导电沟槽CT穿过阱拾取区116并与阱区112接触，其中各导电沟槽CT由导电材料制成，以降低碳化硅半导体功率晶体管的潜在回弹效应(potential snapback effect)。碳化硅半导体功率晶体管的回弹是有害的，可能会造成永久性损坏。掺杂部DP分别位于阱区112中的导电沟槽CT的侧壁上，以提高导电沟槽CT与阱区112之间的导电性。如图1A所示，掺杂部DP可以进一步位于导电沟槽CT的底部下方。
所述衬底100、所述第一漂移层102a、所述第二漂移层102b、所述Delta掺杂层110和所述源极区114具有第一导电类型，所述阱区112、所述阱拾取区116、所述掺杂部DP和所述掩埋掺杂区104具有第二导电类型。举例来说，衬底100、第一漂移层102a、第二漂移层102b、Delta掺杂层110和源极区114是N型，阱区112、阱拾取区116、掺杂部DP和掩埋掺杂区104是P型。所述多个掩埋掺杂区104的掺杂浓度范围例如5E15/cm3～1E18/cm3。所述阱区112的掺杂浓度范围例如5E15/cm3～1E18/cm3，且所述阱区112的厚度(或深度)例如0.5μm～1.5μm。所述源极区114的掺杂浓度范围例如1E17/cm3～1E19/cm3。所述阱拾取区116的掺杂浓度范围例如1E18/cm3～2E20/cm3。所述Delta掺杂层110的掺杂浓度范围例如1E19/cm3～5E19/cm3。
此外，Delta掺杂层110可以有效地限制p阱(如阱区112)的结轮廓变化，其由量产中的模糊的内在和外在的缺陷所引起。Delta掺杂层110中的掺杂剂例如是选自氮(N)、磷(P)与砷(As)中的至少一种。Delta掺杂层110的厚度例如至/>Delta掺杂层110的掺杂浓度例如1E17/cm3至5E18/cm3。
在第一实施例中，碳化硅半导体功率晶体管还包括多个源极电极120、多个栅极电极122与漏极电极124。源极电极120设置于所述第二漂移层120b上，以与阱拾取区116与源极区114直接接触。栅极电极122设置于所述栅极106上，漏极电极124设置于所述衬底100的背面。
在本实施例中，源极区114与掩埋掺杂区104电连接。例如，掩埋掺杂区104通过掺杂带200连接到碳化硅半导体功率晶体管的VSS节点。如图1A的平面图图2所示，形成有掺杂带200以连接多个源极区114和多个掩埋掺杂区104，其中一些元件在图2中被省略，以阐明掩埋掺杂区104、源极区114、栅极电极122等的位置关系。掺杂带200也可设置在漂移层102(第一漂移层102a和第二漂移层102b)中，如图3所示，其为沿图2的III-III线段的截面示意图。掺杂带200可以在源极区114形成之前掺杂在阱区112中。掺杂带200的掺杂浓度例如2E19/cm3至1E20/cm3。
在图2中，所述掺杂带200的延伸方向垂直于多个栅极122的延伸方向，栅极122可设计为对称设置在所述掺杂带200的两侧S1和S2。换言之，掺杂带200的延伸方向垂直于栅极122下方的V形槽(118)的延伸方向。因此，掺杂带200不会影响图1B中第一漂移层102a中的电流流动。也就是说，V形槽底部不存在电场拥挤问题。掺杂带200在图2中是连续区，但本发明不限于此；在另一个实施例中，掺杂带200可以分成几个从图2的上到下分布的子区，且每个子区连接多个源极区114和多个掩埋掺杂区104之一。
图4A至图4I是依照本发明第二实施例的一种碳化硅半导体功率晶体管的制造方法的步骤的截面示意图。
请参照图4A，使用碳化硅(SiC)衬底400，并且所述SiC衬底400可以是n型衬底。第一漂移层402形成在SiC衬底400的上表面400a上，所述第一漂移层402可以是N-漂移层，其中所述第一漂移层402的掺杂浓度范围例如5E14/cm3～1E17/cm3，且所述第一漂移层402的厚度例如4μm～20μm。然而本发明不以此为限。所述SiC衬底400的上表面400a可为{0001}面、{11-20}面或{1100}面。所述SiC衬底400的上表面400a可具有5°以下的离轴取向。在所述第一漂移层402中形成多个掩埋掺杂区404，且所述多个掩埋掺杂区404相互平行。形成掩埋掺杂区404的方法可以是使用覆盖部分第一漂移层402的图案化光刻胶(未示出)的掺杂步骤。
然后，请参照图4B，在所述第一漂移层402上形成第二漂移层406，覆盖所述多个掩埋掺杂区404，且第二漂移层406的掺杂浓度可以与第一漂移层402的掺杂浓度相同或更高。在一实施例中，由于掩埋掺杂区404的存在，第二漂移层406的掺杂浓度可以是第一漂移层402的掺杂浓度的1.2至3倍。所述第二漂移层406的厚度例如1μm～3μm。然后，在所述第二漂移层406的表面406a中全面形成Delta掺杂层408。Delta掺杂层408的厚度例如 至且Delta掺杂层408的掺杂浓度例如1E17/cm3至5E18/cm3。Delta掺杂层408的掺杂剂例如是选自氮(N)、磷(P)与砷(As)中的至少一种。
接着，请参照图4C，在所述Delta掺杂层408上形成掺杂外延层410作为阱区(wellregion)，其中所述阱区(即，掺杂外延层410)的掺杂浓度范围例如5E15/cm3～1E18/cm3，且所述阱区的厚度(或深度)例如0.5μm～1.5μm。然而本发明不以此为限。然后，在形成掺杂带(A strap of doped region)500，从所述掺杂外延层410的表面410a到所述多个掩埋掺杂区410，如图5所示。在第二实施例中，掺杂外延层410是P型，掺杂带500也是P型。形成掺杂带500的方法可以是使用覆盖部分掺杂外延层410的图案化光刻胶(未示出)的掺杂步骤。掺杂带500的掺杂浓度例如2E19/cm3至1E20/cm3。在图5中，掺杂带500延伸至掩埋掺杂区404，但本发明不以此为限。在另一个实施例中，掺杂带500可以仅形成在第二漂移层406中并且与第一漂移层402的顶部直接接触。
随后，请参照图4D，在所述掺杂外延层410的所述表面410a中形成源极区412，其中所述源极区412与所述掩埋掺杂区404通过图5所示的掺杂带500电连接。所述源极区412的掺杂浓度范围例如1E17/cm3～1E19/cm3。
然后，请参照图4E，在所述掩埋掺杂区404之间的所述掺杂外延层410的所述表面410a中形成多个阱拾取区414，使得阱拾取区414穿过源极区412并与阱区(即，掺杂外延层410)接触。所述阱拾取区414的掺杂浓度范围例如1E18/cm3～2E20/cm3。形成阱拾取区414的方法可以是使用覆盖部分表面410a的图案化光刻胶(未示出)的掺杂步骤。
接着，请参照图4F，在所述多个掩埋掺杂区404上方的掺杂外延层410以及第二漂移层406中形成多个V形槽416，其中所述V形槽416穿过所述源极区412、所述阱区(即，掺杂外延层410)与所述Delta掺杂层408。每个掩埋掺杂区404与每个V形槽416的底部416b相隔一预定距离d2。而形成所述V形槽416的步骤例如在每个V形槽416的侧壁416a与底部416b之间形成30°至65°的倾斜角θ。从MOSFET RDSon的角度来看，(03-38)面的沟道取向对弱反型阈值电压和沟道迁移率有正面影响，因此侧壁416a可以是(03-38)面。侧壁118a可以是(03-38)面。所述(03-38)面代表从(0001)面方向倾斜54.7°的面以及从(1120)面方向倾斜35.3°的面。
随后，请参照图4G，在所述第二漂移层406中形成多个导电沟槽CT，以穿过所述阱拾取区414并与所述阱区(即，掺杂外延层410)接触。然后，在所述掺杂外延层410中的多个导电沟槽CT的侧壁上形成多个掺杂部DP。具体而言，可以通过蚀刻第二漂移层406以形成多个凹槽并暴露掺杂外延层410的一部分，再执行掺杂步骤以在所述凹槽的侧壁上形成所述掺杂部DP，然后在所述凹槽中填充导电材料，以形成所述多个导电沟槽CT。在一实施例中，掺杂部DP的掺杂步骤可以使用1.2MeV Al注入，且所述掺杂部DP的掺杂浓度范围例如1E19/cm3～5E19/cm3。在形成多个导电沟槽CT和多个掺杂部DP的步骤中，可以用保护层(未示出)覆盖除了导电沟槽CT的位置之外的V形槽416和表面410a。同时，所述多个导电沟槽CT和所述多个掺杂部DP也可形成在掺杂带500上方，如(沿着与图5相同的截面线的)图6所示。
之后，请参照图4H，在每个V形槽416中形成栅极绝缘层418以及在所述栅极绝缘层418上形成多个栅极420。栅极绝缘层418可以是厚度为250埃至1000埃的栅极氧化层。形成栅极绝缘层418和栅极420的方法可包括依次形成整层栅极氧化层和多晶硅层，然后使用覆盖V形槽416的图案化光刻胶(未示出)作为蚀刻掩模，蚀刻上述多晶硅层和栅极氧化层。在图4H中，栅极420延伸至V形槽416之外的源极区412的顶部，但本发明不以此为限。在其它实施例中，栅极420可以不延伸到源极区412的顶部。
接着，请参照图4I，同时形成多个源极电极422以及多个栅极电极424。所述源极电极422设置于所述掺杂外延层410的表面410a上，以直接接触所述多个阱拾取区414和所述源极区412，且所述栅极电极424设置于所述多个栅极420上。形成源极电极422和栅极电极424的方法可包括在掺杂外延层410的表面410a上先形成绝缘层426，蚀刻所述绝缘层426以形成分别暴露阱拾取区414、源极412与栅极420的多个开口，并在所述多个开口中沉积导电材料(例如金属或合金)。在形成所述源极电极422以及所述栅极电极424之后，在所述SiC衬底400的底表面400b上形成漏极电极428。
综上所述，根据本发明的碳化硅半导体功率晶体管，在栅极下方的漂移层中设有掩埋掺杂区。由于掩埋掺杂区与形成栅极的V形槽底部相距预定距离，因此可以解决V形槽底部下方的高电场问题。此外，掩埋掺杂区能提供额外的电流通路，以降低有效JFET电阻，从而在不影响击穿电压的情况下降低比导通电阻(specific on resistance，Ron)，从而获得良好的可靠性。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (20)

1.一种碳化硅半导体功率晶体管，其特征在于，包括：
衬底，由碳化硅制成；
第一漂移层，设置于所述衬底的平面上；
第二漂移层，形成于所述第一漂移层上，其中多个V形槽形成于所述第二漂移层中，且所述多个V形槽相互平行；
多个掩埋掺杂区，设置于所述多个V形槽下方的所述第一漂移层中，每个所述掩埋掺杂区与每个所述V形槽的底部相隔一预定距离；
多个栅极，设置于所述第二漂移层中的所述多个V形槽中；
栅极绝缘层，设置于所述第二漂移层和每个所述栅极之间；
Delta掺杂层，设置于所述第二漂移层中，且所述多个V形槽横跨所述Delta掺杂层；
阱区，设置于所述第二漂移层中的所述Delta掺杂层上；
多个源极区，设置于所述多个V形槽之间的所述阱区内，其中所述多个源极区与所述多个掩埋掺杂区电连接；
多个阱拾取区，设置于所述第二漂移层中，且每个所述阱拾取区穿过所述多个源极区并与所述阱区接触；
多个导电沟槽，设置于所述第二漂移层中，且每个所述导电沟槽穿过所述多个阱拾取区并与所述阱区接触；以及
多个掺杂部，分别位于所述阱区中的所述多个导电沟槽的侧壁上。
2.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，所述衬底的所述平面为{0001}面、{11-20}面或{1100}面。
3.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，所述衬底的所述平面具有5°以下的离轴取向。
4.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，每个所述V形槽的侧壁与所述底部之间的倾斜角为30°至65°。
5.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，所述衬底、所述第一漂移层、所述第二漂移层、所述Delta掺杂层和所述多个源极区具有第一导电类型，且所述阱区、所述多个阱拾取区、所述多个掺杂部和所述多个掩埋掺杂区具有第二导电类型。
6.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，所述Delta掺杂层的掺杂剂选自氮、磷与砷中的至少一种。
7.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，还包括掺杂带，设置在所述第一漂移层和所述第二漂移层中，以连接所述多个源极区和所述多个掩埋掺杂区。
8.根据权利要求7所述的碳化硅半导体功率晶体管，其特征在于，所述掺杂带的延伸方向垂直于所述V形槽的延伸方向。
9.根据权利要求8所述的碳化硅半导体功率晶体管，其特征在于，所述多个栅极对称设置在所述掺杂带的两侧。
10.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，所述阱区的掺杂浓度范围为5E15/cm3～1E18/cm3。
11.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，所述多个掩埋掺杂区的掺杂浓度范围为5E15/cm3～1E18/cm3。
12.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，每个所述掩埋掺杂区的宽度是每个所述V形槽的所述底部的宽度的1.5至2.0倍。
13.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，所述第一漂移层中的所述掩埋掺杂区的上表面的深度为0.2μm～1.5μm，且所述预定距离为0.3μm～1μm。
14.根据权利要求1所述的碳化硅半导体功率晶体管，其特征在于，还包括：
多个源极电极，设置于所述第二漂移层上，以与所述多个阱拾取区与所述多个源极区直接接触；
多个栅极电极，设置于所述多个栅极上；以及
漏极电极，设置于所述衬底的背面。
15.一种碳化硅半导体功率晶体管的制造方法，其特征在于，包括：
在碳化硅衬底的上表面上形成第一漂移层；
在所述第一漂移层中形成多个掩埋掺杂区，且所述多个掩埋掺杂区相互平行；
在所述第一漂移层上形成第二漂移层，覆盖所述多个掩埋掺杂区；
在所述第二漂移层的表面中形成Delta掺杂层；
在所述Delta掺杂层上形成掺杂外延层作为阱区；
形成掺杂带，从所述掺杂外延层的表面穿过所述Delta掺杂层到所述多个掩埋掺杂区；
在所述掺杂外延层的所述表面中形成源极区，其中所述源极区与所述多个掩埋掺杂区通过所述掺杂带电连接；
在所述多个掩埋掺杂区之间的所述掺杂外延层的所述表面中形成多个阱拾取区，穿过所述源极区并与所述阱区接触；
在所述多个掩埋掺杂区上方的所述掺杂外延层以及所述第二漂移层中形成多个V形槽，其中所述多个V形槽穿过所述源极区、所述阱区与所述Delta掺杂层，且每个所述掩埋掺杂区与每个所述V形槽的底部相隔一预定距离；
在所述第二漂移层中形成多个导电沟槽，以穿过所述多个阱拾取区并与所述阱区接触；
在所述阱区中的所述多个导电沟槽的侧壁上形成多个掺杂部；
在所述多个V形槽中形成栅极绝缘层；以及
在所述栅极绝缘层上形成多个栅极。
16.根据权利要求15所述的碳化硅半导体功率晶体管的制造方法，其特征在于，在形成所述多个栅极之后，还包括：形成多个源极电极以及形成多个栅极电极，所述源极电极设置于所述掺杂外延层上，以直接接触所述多个阱拾取区和所述源极区，且所述栅极电极设置于所述多个栅极上。
17.根据权利要求16所述的碳化硅半导体功率晶体管的制造方法，其特征在于，在形成所述源极电极以及所述栅极电极之后，还包括：在所述碳化硅衬底的底表面上形成漏极电极。
18.根据权利要求15所述的碳化硅半导体功率晶体管的制造方法，其特征在于，所述碳化硅衬底的所述上表面为{0001}面、{11-20}面或{1100}面。
19.根据权利要求15所述的碳化硅半导体功率晶体管的制造方法，其特征在于，所述碳化硅衬底的所述上表面具有5°以下的离轴取向。
20.根据权利要求15所述的碳化硅半导体功率晶体管的制造方法，其特征在于，形成所述多个V形槽的步骤包括在每个所述V形槽的侧壁与所述底部之间形成30°至65°的倾斜角。
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