TW202406145A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202406145A
TW202406145A TW111127823A TW111127823A TW202406145A TW 202406145 A TW202406145 A TW 202406145A TW 111127823 A TW111127823 A TW 111127823A TW 111127823 A TW111127823 A TW 111127823A TW 202406145 A TW202406145 A TW 202406145A
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gate
layer
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electron mobility
high electron
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TWI820820B (zh
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温文瑩
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新唐科技股份有限公司
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Priority to CN202211066344.3A priority patent/CN117497536A/zh
Priority to US17/938,953 priority patent/US20240030216A1/en
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Abstract

一種半導體裝置包括金屬-絕緣體-半導體高電子遷移率電晶體（MISHEMT）以及蕭特基閘極高電子遷移率電晶體（HEMT）。蕭特基閘極高電子遷移率電晶體（HEMT）與金屬-絕緣體-半導體高電子遷移率電晶體串聯，且所述蕭特基閘極高電子遷移率電晶體的蕭特基閘極與所述金屬-絕緣體-半導體高電子遷移率電晶體的源極電性連接，以形成從所述金屬-絕緣體-半導體高電子遷移率電晶體的源極往汲極的正向二極體（forward diode）。串聯的結構有利於提高所述半導體裝置的崩潰電壓，而上述正向二極體能降低功率損失。

Description

半導體裝置
本發明是有關於一種具有高電子遷移率電晶體（HEMT）的半導體裝置，且特別是有關於一種結合不同的高電子遷移率電晶體的半導體裝置。
常開型（D-mode）金屬-絕緣體-半導體高電子遷移率電晶體（metal-insulator-semiconductor high-electron-mobility transistor，MISHEMT）是目前發展的一種可應用於耐高壓的功率裝置的電晶體元件，且一般需要與低壓矽（LV Si）MOSFET結合使用，以構成疊接電路（Cascode circuit）。
然而，當上述系統進行開到關的切換（on到off的switch）時，疊接電路中的兩元件（MISHEMＴ和LV Si MOSFET）之間會產生電壓過沖（voltage overshooting）現象，造成兩元件的汲極至閘極（下端元件）和閘極至源低（上端元件）的燒毀。
本發明提供一種半導體裝置，能防止電壓過沖現象發生，從而避免疊接電路中的下端元件和下端元件燒毀。
本發明另提供一種半導體裝置，可降低崩潰電壓以及功率損失。
本發明的半導體裝置，包括常開型金屬-絕緣體-半導體高電子遷移率電晶體（MISHEMT）、蕭特基閘極高電子遷移率電晶體（HEMT）以及低壓矽場效電晶體。常開型MISHEMT具有第一源極、第一閘極與第一汲極。蕭特基閘極高電子遷移率電晶體與常開型MISHEMT串聯，且所述蕭特基閘極高電子遷移率電晶體的蕭特基閘極與所述常開型MISHEMT的第一源極電性連接，以形成從所述第一源極往第一汲極的正向二極體（forward diode）。低壓矽場效電晶體耦接至所述常開型MISHEMT，以形成疊接電路（Cascode circuit）。
在本發明的一實施例中，上述低壓矽場效電晶體具有第二源極、第二閘極與第二汲極，且所述第二源極電性連接至所述常開型MISHEMT的第一閘極，且所述第二汲極電性連接至所述常開型MISHEMT的第一源極。
在本發明的一實施例中，上述常開型MISHEMT的結構包括：形成於一基板上的通道層、形成於通道層上的障壁層、形成於障壁層上的頂蓋層、形成於頂蓋層上的閘極介電層、形成於閘極介電層上的上述第一閘極以及上述第一源極與第一汲極。上述第一源極與第一汲極分別設置在第一閘極兩側且穿過閘極介電層、頂蓋層與障壁層，而與通道層接觸。
在本發明的一實施例中，上述蕭特基閘極高電子遷移率電晶體的蕭特基閘極設置於第一閘極與第一汲極之間的頂蓋層上，且上述蕭特基閘極高電子遷移率電晶體還可包括一源極場板，連接蕭特基閘極與常開型MISHEMT的第一源極。
在本發明的一實施例中，上述半導體裝置還可包括內層介電層，覆蓋上述第一閘極並具有露出上述蕭特基閘極的開口，且上述源極場板形成於內層介電層上並通過上述開口與蕭特基閘極直接接觸。
在本發明的一實施例中，上述通道層為未摻雜氮化鎵層，上述障壁層為氮化鋁鎵層，上述頂蓋層為氮化鎵層。
本發明的另一半導體裝置，包括常關型金屬-絕緣體-半導體高電子遷移率電晶體（MISHEMT）以及蕭特基閘極高電子遷移率電晶體（HEMT）。常關型MISHEMT具有第一源極、第一閘極與第一汲極。蕭特基閘極高電子遷移率電晶體（HEMT）與常關型MISHEMT串聯，且所述蕭特基閘極高電子遷移率電晶體的蕭特基閘極與所述常關型MISHEMT的第一源極電性連接，以形成從所述常關型MISHEMT的第一源極往第一汲極的正向二極體（forward diode）。
在本發明的另一實施例中，上述常關型MISHEMT的結構包括：形成於一基板上的通道層、形成於通道層上的障壁層、形成於障壁層上的上述第一閘極、設置於障壁層與第一閘極之間的P型氮化鎵層、以及上述第一源極與第一汲極。上述第一源極與第一汲極分別設置在第一閘極兩側且穿過上述障壁層，而與通道層接觸。
在本發明的另一實施例中，上述蕭特基閘極高電子遷移率電晶體的蕭特基閘極設置於上述第一閘極與上述第一汲極之間的障壁層上，且上述蕭特基閘極高電子遷移率電晶體還可包括一源極場板，連接上述蕭特基閘極與上述常關型MISHEMT的第一源極。
在本發明的另一實施例中，上述半導體裝置還可包括內層介電層，覆蓋上述第一閘極並具有露出上述蕭特基閘極的開口，且上述源極場板形成於上述內層介電層上並通過上述開口與蕭特基閘極直接接觸。
在本發明的另一實施例中，上述通道層為未摻雜氮化鎵層，且上述障壁層為氮化鋁鎵層。
基於上述，在本發明的半導體裝置中，於金屬-絕緣體-半導體高電子遷移率電晶體（MISHEMT）中串聯一個蕭特基閘極高電子遷移率電晶體，因此可通過串聯的電晶體緩和電壓過沖（voltage overshooting）現象，並藉此提升半導體裝置整體的崩潰電壓。而且，本發明應用於常開型MISHEMT以及常關型MISHEMT都能達到提升崩潰電壓的功效。另外，由於蕭特基閘極高電子遷移率電晶體的蕭特基閘極電性連接至MISHEMT的源極，所以會形成正向二極體，而減少本發明的半導體裝置的功率損失。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下實施例中所附的圖式是為了能更完整地描述本發明的實施例，然而本發明仍可使用許多不同的形式來實施，不限於所記載的實施例。此外，為了清楚起見，各個區域或膜層的相對厚度、距離及位置可能縮小或放大。另外，在圖式中使用相似或相同的元件符號表示相似或相同的部位或特徵的存在。
圖1是依照本發明的第一實施例的一種半導體裝置的剖面示意圖。圖2是圖1的半導體裝置的等效電路圖。
請先參照圖2，本實施例的半導體裝置包括常開型金屬-絕緣體-半導體高電子遷移率電晶體（MISHEMT）110、蕭特基閘極高電子遷移率電晶體（HEMT）120以及低壓矽場效電晶體130。常開型MISHEMT 110具有第一源極S1、第一閘極G1與第一汲極D1。蕭特基閘極高電子遷移率電晶體120與常開型MISHEMT 110串聯，因此通過串聯的電晶體能緩和電壓過沖（voltage overshooting）現象，並藉此提升半導體裝置整體的崩潰電壓。所述蕭特基閘極高電子遷移率電晶體120的蕭特基閘極SKG與常開型MISHEMT 110的第一源極S1電性連接，形成從第一源極S1往第一汲極D1的正向二極體（forward diode）FD。低壓矽場效電晶體130則耦接至常開型MISHEMT 110，以形成疊接電路（Cascode circuit）。
從結構來看，請參照圖1，常開型MISHEMT 110的結構具體可包括形成於一基板100上的通道層112、形成於通道層112上的障壁層114、形成於障壁層114上的頂蓋層116、形成於頂蓋層116上的閘極介電層118、形成於閘極介電層118上的第一閘極G1、以及第一源極S1與第一汲極D1。第一源極S1與第一汲極D1分別設置在第一閘極G1兩側且穿過閘極介電層118、頂蓋層116與障壁層114，而與通道層112接觸。通道層112可以是由未摻雜的氮化鎵(GaN)所形成。障壁層114的材料是未摻雜的III-V族半導體材料，可列舉但不限於氮化鎵鋁(AlGaN)或者其他適當的III-V族材料。通道層112與障壁層114為異質材料，因此會在通道層112與障壁層114之間形成一異質界面，藉由異質材料的能隙差(band gap)，可使二維電子氣(two-dimensional electron gas) 2DEG形成於此異質界面上。在一實施例中，上述通道層112可以是未摻雜氮化鎵層，上述障壁層114是氮化鋁鎵層，上述頂蓋層116是氮化鎵層。常開型MISHEMT 110中的通道層112、障壁層114、頂蓋層116各層均可利用磊晶製程形成磊晶結構，其中磊晶製程例如金屬有機化學氣相沉積(MOCVD)、氫化物氣相磊晶法(HVPE)、分子束磊晶法(MBE)或前述方法之組合。閘極介電層118可採用高介電常數(high-k)的絕緣介電質材料，例如Al 2O 3、HfO 2、Ta 2O 5、Si 3N 4或其組合。
請繼續參照圖1，蕭特基閘極高電子遷移率電晶體120的蕭特基閘極SKG可設置於第一閘極G1與第一汲極D1之間的頂蓋層116上，其形成方式例如是在閘極介電層118中形成露出底下頂蓋層116的溝槽，再於其中沉積形成蕭特基閘極SKG。蕭特基閘極SKG是金屬閘極，其材料可列舉但不限於：TiN、Ni等高功函數(work function)的金屬組合的複合層(multi-layer)。至於蕭特基閘極SKG與常開型MISHEMT 110的第一源極S1電性連接的方式，可通過一源極場板(source field plate)122進行連接。在一實施例中，源極場板122的形成方式可先形成一層內層介電層124覆蓋第一閘極G1以及其他結構，然後於第一源極S1與第一汲極D1形成之後，在內層介電層124中形成露出蕭特基閘極SKG的開口126，然後於內層介電層124上形成源極場板122，並通過上述開口126與蕭特基閘極SKG直接接觸。在另一實施例中，源極場板122的形成方式可先形成內層介電層124並於其中形成露出蕭特基閘極SKG的開口126後，先在開口126中填入導體材料並將其平坦化之後，再於內層介電層124上沉積源極場板122，並通過開口126內的導體材料與蕭特基閘極SKG電性連接。
在圖2中，低壓矽場效電晶體130具有第二源極S2、第二閘極G2與第二汲極D2，其中第二源極S2電性連接至常開型MISHEMT 110的第一閘極G1，且第二汲極D2電性連接至常開型MISHEMT 110的第一源極S1，而構成所謂的疊接電路。由於電流路徑P1可經由其正向二極體FD’ 從低壓矽場效電晶體130的第二源極S2往第二汲極D2，再自常開型MISHEMT 110的第一源極S1經由其正向二極體FD往第一汲極D1，不需經過多層的磊晶層(如通道層、障壁層114)，因此功率損失可大幅減少。
在本實施例中，基板100若是矽基板，低壓矽場效電晶體130可直接形成在基板100上；在另一實施例中，若在基板100上磊晶成長矽層(未繪示)，則低壓矽場效電晶體130也可形成在此矽層上；在又一實施例中，低壓矽場效電晶體130可以形成在其他基板，再利用封裝製程將其與圖2的常開型MISHEMT 110電性連接。
圖3是依照本發明的第二實施例的一種半導體裝置的剖面示意圖，其中使用與第一實施例相同的元件符號來表示相同或近似的部分與構件，且相同或近似的部分與構件的相關內容也可參照第一實施例的內容，不再贅述。
請參照圖3，本實施例的半導體裝置包括常關型金屬-絕緣體-半導體高電子遷移率電晶體（MISHEMT）210以及蕭特基閘極高電子遷移率電晶體（HEMT）120。常關型MISHEMT 210具有第一源極S1、第一閘極G1與第一汲極D1。蕭特基閘極高電子遷移率電晶體120與常關型MISHEMT 210串聯，且蕭特基閘極高電子遷移率電晶體120的蕭特基閘極SKG與常關型MISHEMT 210的第一源極S1電性連接，以形成從常關型MISHEMT 210的第一源極S1往第一汲極D1的正向二極體（forward diode）。
圖4是圖3的半導體裝置的等效電路圖。
在圖4中，串聯的常關型MISHEMT 210與蕭特基閘極高電子遷移率電晶體120能緩和電壓過沖現象，從而提升半導體裝置整體的崩潰電壓。而且，第一源極S1往第一汲極D1的正向二極體FD提供電流從電流路徑P2從常關型MISHEMT 210的第一源極S1往第一汲極D1，不需經過多層的磊晶層(如P型氮化鎵層206、通道層2024)，因此能減少裝置的功率損失。
從結構來看，請參照圖3，常關型MISHEMT 210的結構包括形成於一基板200上的通道層202、形成於通道層202上的障壁層204、形成於障壁層204上的第一閘極G1、設置於障壁層204與第一閘極G1之間的P型氮化鎵層206、以及第一源極S1與第一汲極D1。第一源極S1與第一汲極D1分別設置在第一閘極G1兩側且穿過上述障壁層204而與通道層202接觸。通道層202可以是由未摻雜的氮化鎵所形成。障壁層204的材料是未摻雜的III-V族半導體材料，可列舉但不限於氮化鎵鋁或者其他適當的III-V族材料。通道層202與障壁層204為異質材料，因此會在通道層202與障壁層204之間形成一異質界面，藉由異質材料的能隙差，可使二維電子氣2DEG形成於此異質界面上。而帶正電的P型GaN層206形成在障壁層204上，因此P型GaN層206中的正電荷它會耗盡2DEG中的電子，形成增強型(E-mode)結構。常關型MISHEMT 210中的通道層202、障壁層204、P型GaN層206各層均可利用磊晶製程形成磊晶結構，其中磊晶製程例如金屬有機化學氣相沉積(MOCVD)、氫化物氣相磊晶法(HVPE)、分子束磊晶法(MBE)或前述方法之組合。
請繼續參照圖4，蕭特基閘極高電子遷移率電晶體120的蕭特基閘極SKG可設置於第一閘極G1與第一汲極D1之間的障壁層204上，其形成方式例如是在一層內層介電層中形成露出底下障壁層204的溝槽，再於其中沉積形成蕭特基閘極SKG；或者，直接在障壁層204上形成經由沉積與蝕刻製程形成。蕭特基閘極SKG與常關型MISHEMT 210的第一源極S1電性連接的方式，可通過一源極場板122進行連接。在一實施例中，源極場板122的形成方式可先形成一層內層介電層220覆蓋第一閘極G1以及其他結構，然後於第一源極S1與第一汲極D1形成之後，在內層介電層220中形成露出蕭特基閘極SKG的開口222，然後於內層介電層220上形成源極場板122，並通過上述開口222與蕭特基閘極SKG直接接觸。在另一實施例中，源極場板122的形成方式可先形成內層介電層220並於其中形成露出蕭特基閘極SKG的開口222後，先在開口222中填入導體材料並將其平坦化之後，再於內層介電層220上沉積源極場板122，並通過開口222內的導體材料與蕭特基閘極SKG電性連接。
綜上所述，本發明通過串聯一個蕭特基閘極高電子遷移率電晶體到金屬-絕緣體-半導體高電子遷移率電晶體內，使電壓過沖（voltage overshooting）現象得以緩解，從而提升半導體裝置整體的崩潰電壓。而且，上述蕭特基閘極高電子遷移率電晶體的蕭特基閘極與MISHEMT的源極電性連接，可形成正向二極體，因此當Vgs關閉時，電流會經由上述正向二極體由源極到汲極，所以可減少功率損失。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200:基板 110:常開型金屬-絕緣體-半導體高電子遷移率電晶體 112、202:通道層 114、204:障壁層 116:頂蓋層 118:閘極介電層 120:蕭特基閘極高電子遷移率電晶體 122:源極場板 124、220:內層介電層 126、222:開口 130:低壓矽場效電晶體 210:常關型金屬-絕緣體-半導體高電子遷移率電晶體 206:P型氮化鎵 2DEG:二維電子氣 D1:第一汲極 D2:第二汲極 FD、FD’:正向二極體 G1:第一閘極 G2:第二閘極 P1、P2:電流路徑 S1:第一源極 S2:第二源極 SKG:蕭特基閘極
圖1是依照本發明的第一實施例的一種半導體裝置的剖面示意圖。 圖2是圖1的半導體裝置的等效電路圖。 圖3是依照本發明的第二實施例的一種半導體裝置的剖面示意圖。 圖4是圖3的半導體裝置的等效電路圖。
100:基板
110:常開型金屬-絕緣體-半導體高電子遷移率電晶體
112:通道層
114:障壁層
116:頂蓋層
118:閘極介電層
120:蕭特基閘極高電子遷移率電晶體
122:源極場板
124:內層介電層
126:開口
2DEG:二維電子氣
D1:第一汲極
G1:第一閘極
S1:第一源極
SKG:蕭特基閘極閘極

Claims (11)

  1. 一種半導體裝置，包括： 常開型金屬-絕緣體-半導體高電子遷移率電晶體（MISHEMT），具有第一源極、第一閘極與第一汲極； 蕭特基閘極高電子遷移率電晶體（HEMT），與所述常開型金屬-絕緣體-半導體高電子遷移率電晶體串聯，且所述蕭特基閘極高電子遷移率電晶體的蕭特基閘極與所述常開型金屬-絕緣體-半導體高電子遷移率電晶體的所述第一源極電性連接，以形成從所述第一源極至所述第一汲極的正向二極體（forward diode）；以及 低壓矽場效電晶體，耦接至所述常開型金屬-絕緣體-半導體高電子遷移率電晶體，以形成疊接電路（Cascode circuit）。
  2. 如請求項1所述的半導體裝置，其中所述低壓矽場效電晶體具有第二源極、第二閘極與第二汲極，且所述第二源極電性連接至所述第一閘極，且所述第二汲極電性連接至所述第一源極。
  3. 如請求項1所述的半導體裝置，其中所述常開型金屬-絕緣體-半導體高電子遷移率電晶體的結構包括： 通道層，形成於一基板上； 障壁層，形成於所述通道層上； 頂蓋層，形成於所述障壁層上； 閘極介電層，形成於所述頂蓋層上； 所述第一閘極，形成於所述閘極介電層上；以及 所述第一源極與所述第一汲極，分別設置在所述第一閘極兩側且穿過所述閘極介電層、所述頂蓋層與所述障壁層，而與所述通道層接觸。
  4. 如請求項3所述的半導體裝置，其中所述蕭特基閘極高電子遷移率電晶體的所述蕭特基閘極設置於所述第一閘極與所述第一汲極之間的所述頂蓋層上，且所述蕭特基閘極高電子遷移率電晶體更包括一源極場板，連接所述蕭特基閘極與常開型金屬-絕緣體-半導體高電子遷移率電晶體的所述第一源極。
  5. 如請求項4所述的半導體裝置，更包括內層介電層，覆蓋所述第一閘極並具有露出所述蕭特基閘極的開口，且所述源極場板形成於所述內層介電層上並通過所述開口與所述蕭特基閘極直接接觸。
  6. 如請求項3所述的半導體裝置，其中所述通道層為未摻雜氮化鎵層，所述障壁層為氮化鋁鎵層，所述頂蓋層為氮化鎵層。
  7. 一種半導體裝置，包括： 常關型金屬-絕緣體-半導體高電子遷移率電晶體（MISHEMT），具有第一源極、第一閘極與第一汲極；以及 蕭特基閘極高電子遷移率電晶體（HEMT），與所述常關型金屬-絕緣體-半導體高電子遷移率電晶體串聯，且所述蕭特基閘極高電子遷移率電晶體的蕭特基閘極與所述常關型金屬-絕緣體-半導體高電子遷移率電晶體的所述第一源極電性連接，以形成從所述第一源極至所述第一汲極的正向二極體（forward diode）。
  8. 如請求項7所述的半導體裝置，其中所述常關型金屬-絕緣體-半導體高電子遷移率電晶體的結構包括： 通道層，形成於一基板上； 障壁層，形成於所述通道層上； 所述第一閘極，形成於所述障壁層上； P型氮化鎵層，設置於所述障壁層與所述第一閘極之間；以及 所述第一源極與所述第一汲極，分別設置在所述第一閘極兩側且穿過所述障壁層，而與所述通道層接觸。
  9. 如請求項8所述的半導體裝置，其中所述蕭特基閘極高電子遷移率電晶體的所述蕭特基閘極設置於所述第一閘極與所述第一汲極之間的所述障壁層上，且所述蕭特基閘極高電子遷移率電晶體更包括一源極場板，連接所述蕭特基閘極與常關型金屬-絕緣體-半導體高電子遷移率電晶體的所述第一源極。
  10. 如請求項9所述的半導體裝置，更包括內層介電層，覆蓋所述第一閘極並具有露出所述蕭特基閘極的開口，且所述源極場板形成於所述內層介電層上並通過所述開口與所述蕭特基閘極直接接觸。
  11. 如請求項8所述的半導體裝置，其中所述通道層為未摻雜氮化鎵層，且所述障壁層為氮化鋁鎵層。
TW111127823A 2022-07-25 2022-07-25 半導體裝置 TWI820820B (zh)

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