TW202404135A - 壓電絕緣體(poi)基板及製造壓電絕緣體基板之方法 - Google Patents

壓電絕緣體(poi)基板及製造壓電絕緣體基板之方法 Download PDF

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Publication number
TW202404135A
TW202404135A TW112112150A TW112112150A TW202404135A TW 202404135 A TW202404135 A TW 202404135A TW 112112150 A TW112112150 A TW 112112150A TW 112112150 A TW112112150 A TW 112112150A TW 202404135 A TW202404135 A TW 202404135A
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TW
Taiwan
Prior art keywords
layer
substrate
piezoelectric
trapping
poi
Prior art date
Application number
TW112112150A
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English (en)
Chinese (zh)
Inventor
布萊斯 泰維爾
伊莎貝 柏崔德
克莉絲朵 梵媞蘇
Original Assignee
法商梭意泰科公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 法商梭意泰科公司 filed Critical 法商梭意泰科公司
Publication of TW202404135A publication Critical patent/TW202404135A/zh

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/704Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H10N30/708Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/01Manufacture or treatment
    • H10N30/03Assembling devices that include piezoelectric or electrostrictive parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/01Manufacture or treatment
    • H10N30/07Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/80Constructional details
    • H10N30/85Piezoelectric or electrostrictive active materials
    • H10N30/853Ceramic compositions
    • H10N30/8542Alkali metal based oxides, e.g. lithium, sodium or potassium niobates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02Details
    • H03H9/02535Details of surface acoustic wave devices
    • H03H9/02543Characteristics of substrate, e.g. cutting angles
    • H03H9/02574Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
TW112112150A 2022-03-30 2023-03-30 壓電絕緣體(poi)基板及製造壓電絕緣體基板之方法 TW202404135A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2202897 2022-03-30
FR2202897A FR3134239B1 (fr) 2022-03-30 2022-03-30 Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)

Publications (1)

Publication Number Publication Date
TW202404135A true TW202404135A (zh) 2024-01-16

Family

ID=82319873

Family Applications (1)

Application Number Title Priority Date Filing Date
TW112112150A TW202404135A (zh) 2022-03-30 2023-03-30 壓電絕緣體(poi)基板及製造壓電絕緣體基板之方法

Country Status (8)

Country Link
US (1) US20250255187A1 (https=)
EP (1) EP4500582A1 (https=)
JP (1) JP2025511029A (https=)
KR (1) KR20240167880A (https=)
CN (1) CN118974909A (https=)
FR (1) FR3134239B1 (https=)
TW (1) TW202404135A (https=)
WO (1) WO2023187030A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117460388B (zh) * 2023-12-25 2024-07-23 天通瑞宏科技有限公司 一种复合衬底及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3048306B1 (fr) * 2016-02-26 2018-03-16 Soitec Support pour une structure semi-conductrice
US12525483B2 (en) * 2020-07-28 2026-01-13 Soitec Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer

Also Published As

Publication number Publication date
CN118974909A (zh) 2024-11-15
JP2025511029A (ja) 2025-04-15
WO2023187030A1 (fr) 2023-10-05
EP4500582A1 (fr) 2025-02-05
FR3134239A1 (fr) 2023-10-06
US20250255187A1 (en) 2025-08-07
FR3134239B1 (fr) 2025-02-14
KR20240167880A (ko) 2024-11-28

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