Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
  • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
  • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
  • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/01—Manufacture or treatment
  • H10N30/03—Assembling devices that include piezoelectric or electrostrictive parts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/01—Manufacture or treatment
  • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
  • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
  • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/80—Constructional details
  • H10N30/85—Piezoelectric or electrostrictive active materials
  • H10N30/853—Ceramic compositions
  • H10N30/8542—Alkali metal based oxides, e.g. lithium, sodium or potassium niobates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
  • H03H9/02—Details
  • H03H9/02535—Details of surface acoustic wave devices
  • H03H9/02543—Characteristics of substrate, e.g. cutting angles
  • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate

Definitions

• Piezoelectric substrate on insulator (POI) and method of manufacturing a piezoelectric substrate on insulator (POI)
• the invention relates to a piezoelectric substrate on insulator (POI) comprising in this order a support substrate, a trapping structure, a dielectric layer and a piezoelectric layer, as well as a method of manufacturing such a POI substrate.
• POI piezoelectric substrate on insulator
• Such substrates are known in the state of the art, for example a POI substrate comprising a monocrystalline silicon substrate, a polycrystalline silicon trapping structure, a silicon oxide layer and a piezoelectric layer, in particular a layer of lithium tantalate (LTO) or lithium niobate (LNO).
• LTO lithium tantalate
• LNO lithium niobate
• the trapping structure makes it possible to reduce losses linked to parasitic conduction effects at the interface between the support substrate and the dielectric layer.
• the trapping layer which is inserted between the support substrate and the dielectric layer, serves to reduce the lifespan of the charges in this region.
• the object of the invention is therefore to increase the number of traps with less risk of the appearance of parasitic effects.
• a piezoelectric substrate on insulator comprising: a support substrate, in particular a silicon-based substrate, a piezoelectric layer, in particular a layer of lithium tantalate (LTO) or lithium niobate (LNO), a dielectric layer, in particular a silicon oxide layer, sandwiched between the piezoelectric layer and the support substrate, and a trapping structure sandwiched between the dielectric layer and the support substrate comprising a first trapping layer based on polycrystalline or amorphous or porous silicon, preferably based on polycrystalline silicon.
• LTO lithium tantalate
• LNO lithium niobate
• a dielectric layer in particular a silicon oxide layer
• a trapping structure sandwiched between the dielectric layer and the support substrate comprising a first trapping layer based on polycrystalline or amorphous or porous silicon, preferably based on polycrystalline silicon.
• This POI substrate is characterized in that the trapping structure comprises a second trapping layer based on a different material
• the second trapping layer may be based on silicon carbide.
• a second layer based on silicon carbide effectively reduces parasitic currents.
• the second trapping layer based on silicon carbide may be thinner than the first layer.
• a thinner layer of silicon carbide makes it possible to increase the number of traps, while limiting the appearance of parasitic modes due to the presence of the trapping structure, particularly in comparison with a trapping layer silicon-based mono-material having the same trap number.
• the second trapping layer based on silicon carbide may have a thickness less than or equal to 500nm, in particular a thickness less than or equal to 200nm, more in particular less than or equal to 50nm. Even for such small thicknesses, a sufficient increase in the number of traps is observed.
• the first silicon-based trapping layer may have a thickness less than or equal to 2 pm, in particular a thickness less than or equal to 1 pm.
• the second trapping layer can be directly formed on the first trapping layer.
• a compact structure can be maintained.
• the first trapping layer is positioned between the support substrate and the second trapping layer. This facilitates the formation of the trapping structure, because a layer of silicon carbide is deposited at a lower temperature than a layer of silicon.
• the trapping structure comprises only the first trapping layer and the second trapping layer.
• the trapping structure is arranged directly on the substrate and the dielectric layer is arranged directly on the trapping structure.
• the object of the invention is also achieved by a method of manufacturing a piezoelectric substrate on insulator (POI) as described above and comprising the steps of: providing a support substrate, in particular a silicon-based substrate , provide a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), form a trapping structure over the support substrate, form a dielectric layer, in particular a silicon oxide layer, over the substrate comprising a piezoelectric layer and/or over the trapping structure, assembling the piezoelectric substrate with the support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate, characterized in that the formation of the trapping structure comprises the formation of a first layer to based on polycrystalline or amorphous or porous silicon, preferably based on polycrystalline silicon, and the formation of a second trapping layer based on a different material.
• LTO lithium tantalate
• the method of manufacturing a piezoelectric substrate may further comprise a step of: forming a weakening zone inside the piezoelectric layer, in particular before the assembly step, and carrying out a fracture along the weakening zone to separate part of the piezoelectric layer from the remainder of the substrate comprising the piezoelectric layer after the assembly step to transfer the part of the piezoelectric layer to the support substrate.
• This process makes it possible to manufacture the POI substrates according to the invention in an industrial manner.
• Figure 1 schematically represents a piezoelectric substrate on insulator (POI) according to a first embodiment of the invention.
• Figure 2 schematically represents a method of manufacturing a piezoelectric substrate on insulator (POI) according to a second embodiment of the invention.
• Figure 1 schematically represents a piezoelectric substrate on insulator (POI) 100 according to the first embodiment of the invention.
• the piezoelectric substrate on insulator 100 comprises a support substrate 102.
• the support substrate 102 is a silicon-based substrate, in particular a monocrystalline silicon wafer.
• a trapping structure 104 is arranged over the support substrate 102.
• the trapping structure 104 may be in direct contact with the support substrate 102.
• the trapping structure 104 has a thickness equal to or less than 2 pm, preferably equal to or less at 1 pm, even more preferably equal to or less than 600nm.
• the trapping structure 104 comprises two layers: a first trapping layer 104a and a second trapping layer 104b having a material different from the material of the first trapping layer 104a.
• the trapping structure 104 comprises only the first trapping layer 104a and the second trapping layer 104b.
• the first trapping layer 104a is based on polycrystalline silicon or based on amorphous silicon or based on porous silicon.
• the second trapping layer 104b is based on silicon carbide (SiC).
• SiC silicon carbide
• these are layers deposited by low pressure chemical vapor deposition (LPCVD) or by chemical vapor deposition activated by plasma (PECVD) or by high density plasma activated chemical vapor deposition (HDP-CVD).
• the two trapping layers 104a, 104b have different thicknesses.
• the silicon-based trapping layer 104a preferably has a thickness less than or equal to 2 pm, in particular a thickness less than or equal to 1 pm.
• the trapping layer based on silicon carbide 104b preferably has a thickness less than or equal to 500nm, in particular a thickness less than or equal to 200nm, and more particularly a thickness less than or equal to 50nm.
• the first trapping layer 104a has a thickness of 500nm and the second trapping layer 104b has a thickness of 50nm.
• a dielectric layer 106 is arranged above, in particular directly on the trapping structure 104.
• the dielectric layer 106 is preferably a layer based on silicon oxide.
• the dielectric layer 106 preferably has a thickness between 100nm and 1 pm, in particular between 200nm and 700nm.
• the dielectric layer 106 can be formed by CVD deposition or any other suitable deposition process.
• a piezoelectric layer 108 is arranged above, in particular directly on the dielectric layer 106. This is preferably a layer of lithium tantalate (LTO) or lithium niobate (LNO). The piezoelectric layer 108 typically has a thickness of between 200nm and 1 pm.
• LTO lithium tantalate
• LNO lithium niobate
• the order of the first trapping layer 104a and the second trapping layer 104b can be reversed.
• it is the second trapping layer based on silicon carbide which is located between the support substrate 102 and the first trapping layer 104a based on polycrystalline silicon or based on amorphous silicon or based on porous silicon.
• Figure 2 schematically represents a method of manufacturing a piezoelectric substrate on insulator (POI) according to the second embodiment of the invention to obtain a POI substrate 100 according to the first embodiment as described above in relation with Figure 1.
• POI piezoelectric substrate on insulator
• step II) provides for the formation of the trapping structure 104 on a free surface 120 of the support substrate 102.
• the formation of the trapping structure 104 begins with the formation of a first trapping layer 104a produced by low pressure chemical vapor deposition (LPCVD).
• LPCVD low pressure chemical vapor deposition
• the formation of the first trapping layer 104a of step II) can be carried out by a thermal growth technique or by physical vapor deposition (PVD).
• the trapping layer 104a formed on the support substrate 102 is a layer based on polycrystalline silicon, based on amorphous silicon or based on porous silicon.
• the thickness of the trapping layer 104a is equal to or less than 2 pm, in particular equal to or less than 1 pm.
• a second trapping layer 104b is formed on the first trapping layer 104b.
• This second trapping layer 104b is based on silicon carbide.
• the second trapping layer 104b is formed with a thickness less than the first trapping layer, preferably with a thickness equal to or less than 500nm, in particular a thickness less than or equal to 200nm, more particularly with a thickness equal to or less at 50nm.
• the second trapping layer 104b is produced by low-pressure chemical vapor deposition (LPCVD) or by plasma-activated chemical vapor deposition (PECVD) or by high-density plasma-activated chemical vapor deposition (HDP-CVD). .
• LPCVD low-pressure chemical vapor deposition
• PECVD plasma-activated chemical vapor deposition
• HDP-CVD high-density plasma-activated chemical vapor deposition
• the formation of the second trapping layer 104b during step II) can be carried out by a thermal growth technique or by physical vapor deposition (PVD).
• PVD physical vapor deposition
• the formation of the second trapping layer 104b is carried out at a lower temperature than the first trapping layer 104a.
• one or more treatments of the surface of the first trapping layer 104a can take place, such as polishing, in particular CMP type polishing, or activation of the surface by plasma treatment or ozone.
• a dielectric layer 106a is formed on the free surface 122 of the second trapping layer 104b.
• the dielectric layer 106a is preferably a silicon oxide layer formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).
• the dielectric layer 106a preferably has a thickness equal to or less than 1 pm, in particular equal to or less than 700 nm.
• a heat treatment can be carried out after deposition of the dielectric layer 106a to densify it.
• a substrate 124 comprising a piezoelectric layer 126 in particular a substrate 124 comprising lithium tantalate (LTO) or lithium niobate (LNO), is provided.
• the piezoelectric layer 124 is, in this embodiment, arranged over a base substrate 126.
• the piezoelectric layer 126 is a solid layer and forms the entire substrate 124.
• a second dielectric layer 106b in particular a layer of silicon oxide, is produced on the free surface 130 of the piezoelectric layer 126.
• This layer is produced in the same manner as the dielectric layer 106a formed during stage III).
• the thickness is chosen such that the sum of the thicknesses of the two dielectric layers 106a and 106b is between 10Onm and 1 pm, in particular between 200nm and 700nm.
• one or more surface treatment steps of the free surface 130 of the substrate 124 comprising a piezoelectric layer can be carried out before the formation of the dielectric layer 106b.
• a surface activation treatment can be carried out, such as a plasma treatment and/or an ozone-based treatment.
• step VI) the substrate 124 obtained after step V) is assembled with the support substrate 102 obtained in step III) to form a support substrate - substrate assembly 132 comprising a piezoelectric layer.
• the assembly is implemented in such a way that the dielectric layers 106a and 106b are placed in direct contact. Assembly is preferably carried out by molecular adhesion.
• a thinning step VII) of the assembly 132 is carried out to obtain the POI substrate 100 with a thinner piezoelectric layer 108, as illustrated in Figure 1.
• the thinning step can be carried out by grinding, or by a step of forming a weakening zone in the piezoelectric layer 126 before the assembly step VI), so as to delimit the piezoelectric layer 108 to be transferred to the support substrate 102, followed by fracturing.
• This step of forming a weakened zone is carried out by implantation of atomic or ionic species in the piezoelectric layer 126.
• the atomic or ionic implantation can be carried out in such a way that the weakened zone is located inside of the piezoelectric layer 126 and delimits a piezoelectric layer 108 to be transferred from the rest of the piezoelectric layer 126.
• a step of fracturing the assembly 132 by providing thermal and/or mechanical energy at the level of the weakening zone of the piezoelectric layer 126 is then produced, in order to obtain the piezoelectric substrate on insulator (POI) 100.
• the bonding between the support substrate 102 and the substrate 124 can also be done between the trapping structure 104 and the dielectric layer 106b, that is to say without carrying out step III), or between the layer dielectric 106a and the piezoelectric layer 126.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Chemical & Material Sciences (AREA)
• Materials Engineering (AREA)
• Ceramic Engineering (AREA)
• Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
• Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Applications Claiming Priority (2)

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• 2022
  • 2022-03-30 FR FR2202897A patent/FR3134239B1/fr active Active
• 2023
  • 2023-03-30 EP EP23715149.3A patent/EP4500582A1/fr active Pending
  • 2023-03-30 KR KR1020247035672A patent/KR20240167880A/ko active Pending
  • 2023-03-30 TW TW112112150A patent/TW202404135A/zh unknown
  • 2023-03-30 US US18/852,822 patent/US20250255187A1/en active Pending
  • 2023-03-30 CN CN202380031788.XA patent/CN118974909A/zh active Pending
  • 2023-03-30 WO PCT/EP2023/058244 patent/WO2023187030A1/fr not_active Ceased
  • 2023-03-30 JP JP2024557646A patent/JP2025511029A/ja active Pending

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