JP2025511029A - ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法 - Google Patents

ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法 Download PDF

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Publication number
JP2025511029A
JP2025511029A JP2024557646A JP2024557646A JP2025511029A JP 2025511029 A JP2025511029 A JP 2025511029A JP 2024557646 A JP2024557646 A JP 2024557646A JP 2024557646 A JP2024557646 A JP 2024557646A JP 2025511029 A JP2025511029 A JP 2025511029A
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JP
Japan
Prior art keywords
layer
substrate
piezoelectric
trapping
poi
Prior art date
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Pending
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JP2024557646A
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English (en)
Japanese (ja)
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JP2025511029A5 (https=
Inventor
ブライス タベル，
イザベル ベルトラン，
クリステル ヴェイティゾウ，
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Soitec SA
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Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2025511029A publication Critical patent/JP2025511029A/ja
Publication of JP2025511029A5 publication Critical patent/JP2025511029A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/03—Assembling devices that include piezoelectric or electrostrictive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H10N30/8542—Alkali metal based oxides, e.g. lithium, sodium or potassium niobates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
JP2024557646A 2022-03-30 2023-03-30 ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法 Pending JP2025511029A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2202897 2022-03-30
FR2202897A FR3134239B1 (fr) 2022-03-30 2022-03-30 Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
PCT/EP2023/058244 WO2023187030A1 (fr) 2022-03-30 2023-03-30 Substrat piézoélectrique sur isolant (poi) et procédé de fabrication d'un substrat piézoélectrique sur isolant (poi)

Publications (2)

Publication Number Publication Date
JP2025511029A true JP2025511029A (ja) 2025-04-15
JP2025511029A5 JP2025511029A5 (https=) 2026-03-10

Family

ID=82319873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024557646A Pending JP2025511029A (ja) 2022-03-30 2023-03-30 ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法

Country Status (8)

Country Link
US (1) US20250255187A1 (https=)
EP (1) EP4500582A1 (https=)
JP (1) JP2025511029A (https=)
KR (1) KR20240167880A (https=)
CN (1) CN118974909A (https=)
FR (1) FR3134239B1 (https=)
TW (1) TW202404135A (https=)
WO (1) WO2023187030A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117460388B (zh) * 2023-12-25 2024-07-23 天通瑞宏科技有限公司 一种复合衬底及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3048306B1 (fr) * 2016-02-26 2018-03-16 Soitec Support pour une structure semi-conductrice
US12525483B2 (en) * 2020-07-28 2026-01-13 Soitec Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer

Also Published As

Publication number Publication date
CN118974909A (zh) 2024-11-15
WO2023187030A1 (fr) 2023-10-05
EP4500582A1 (fr) 2025-02-05
FR3134239A1 (fr) 2023-10-06
US20250255187A1 (en) 2025-08-07
FR3134239B1 (fr) 2025-02-14
KR20240167880A (ko) 2024-11-28
TW202404135A (zh) 2024-01-16

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