TW202343535A - 用於製作供體底材之方法 - Google Patents

用於製作供體底材之方法 Download PDF

Info

Publication number
TW202343535A
TW202343535A TW111148517A TW111148517A TW202343535A TW 202343535 A TW202343535 A TW 202343535A TW 111148517 A TW111148517 A TW 111148517A TW 111148517 A TW111148517 A TW 111148517A TW 202343535 A TW202343535 A TW 202343535A
Authority
TW
Taiwan
Prior art keywords
substrate
layer
donor
hours
donor substrate
Prior art date
Application number
TW111148517A
Other languages
English (en)
Chinese (zh)
Inventor
艾佛列 塞德里克 查爾斯
賽巴斯丁 帝柏特
克雷蒙 高莫
Original Assignee
法商索泰克公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 法商索泰克公司 filed Critical 法商索泰克公司
Publication of TW202343535A publication Critical patent/TW202343535A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
TW111148517A 2021-12-23 2022-12-16 用於製作供體底材之方法 TW202343535A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2114469A FR3131436B1 (fr) 2021-12-23 2021-12-23 Procede de fabrication d’un substrat donneur
FRFR2114469 2021-12-23

Publications (1)

Publication Number Publication Date
TW202343535A true TW202343535A (zh) 2023-11-01

Family

ID=81345982

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111148517A TW202343535A (zh) 2021-12-23 2022-12-16 用於製作供體底材之方法

Country Status (8)

Country Link
US (1) US20250054745A1 (https=)
EP (1) EP4453996A1 (https=)
JP (1) JP2025501705A (https=)
KR (1) KR20240128923A (https=)
CN (1) CN118476009A (https=)
FR (1) FR3131436B1 (https=)
TW (1) TW202343535A (https=)
WO (1) WO2023118574A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI919630B (zh) 2023-12-19 2026-03-21 法商索泰克公司 用於製造一絕緣體上壓電（ｐｏｉ）結構生產用供體底材的方法，用於製造一絕緣體上壓電（ｐｏｉ）結構之方法，該絕緣體上壓電（ｐｏｉ）結構，及包含該絕緣體上壓電（ｐｏｉ）結構之元件或系統

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3157060A1 (fr) * 2023-12-19 2025-06-20 Soitec Régénération d'un substrat donneur pour la fabrication d'une structure POI

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005229455A (ja) * 2004-02-16 2005-08-25 Shin Etsu Chem Co Ltd 複合圧電基板
FR3079346B1 (fr) * 2018-03-26 2020-05-29 Soitec Procede de fabrication d'un substrat donneur pour le transfert d'une couche piezoelectrique, et procede de transfert d'une telle couche piezoelectrique
FR3079345B1 (fr) * 2018-03-26 2020-02-21 Soitec Procede de fabrication d'un substrat pour dispositif radiofrequence

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI919630B (zh) 2023-12-19 2026-03-21 法商索泰克公司 用於製造一絕緣體上壓電（ｐｏｉ）結構生產用供體底材的方法，用於製造一絕緣體上壓電（ｐｏｉ）結構之方法，該絕緣體上壓電（ｐｏｉ）結構，及包含該絕緣體上壓電（ｐｏｉ）結構之元件或系統

Also Published As

Publication number Publication date
WO2023118574A1 (fr) 2023-06-29
US20250054745A1 (en) 2025-02-13
JP2025501705A (ja) 2025-01-23
CN118476009A (zh) 2024-08-09
KR20240128923A (ko) 2024-08-27
FR3131436A1 (fr) 2023-06-30
EP4453996A1 (fr) 2024-10-30
FR3131436B1 (fr) 2025-04-25

Similar Documents

Publication Publication Date Title
US12603629B2 (en) Composite structure and associated production method
KR102312794B1 (ko) 압전성 재료 기판과 지지 기판의 접합체
US11689172B2 (en) Assembly of piezoelectric material substrate and support substrate, and method for manufacturing said assembly
CN112272920B (zh) 接合体及弹性波元件
KR101573812B1 (ko) Ｓｏｉ 웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼
KR102312795B1 (ko) 압전성 재료 기판과 지지 기판의 접합체
TW202343535A (zh) 用於製作供體底材之方法
CN102810466A (zh) 用于制造半导体衬底的方法
TWI430339B (zh) 用於製備一多層結晶結構之方法
US12490656B2 (en) Hybrid structure and a method for manufacturing the same
US20250323210A1 (en) Manufacturing method and joining method of joined body
US11700771B2 (en) Assembly of piezoelectric material substrate and support substrate, and method for manufacturing said assembly
US7863156B2 (en) Method of producing a strained layer
JP7752128B2 (ja) 高周波デバイスのための、圧電層を転写するのに使用できる圧電構造体を製造するための方法、及びそのような圧電層を転写するための方法
Mishin et al. Optimizing high concentration scandium aluminum nitride films
TW202544875A (zh) 接合體、元件及接合體之製造方法
US6521100B2 (en) Method of producing a piezoelectric thin film and bulk acoustic wave resonator fabricated according to the method
US20250192749A1 (en) Piezoelectric-on-insulator (poi) substrate and method for producing a piezoelectric-on-insulator (poi) substrate
US12212301B2 (en) Composite substrate and surface acoustic wave element
Mishin et al. Reducing Impact of Stress on Coupling Coefficient in 30% Scandium Aluminum Nitride Films
JP2025533337A (ja) 圧電薄膜転写方法に用いられるドナー基板を製造する方法
CN119317345A (zh) 一种压电复合衬底的制备方法