JP2025501705A - ドナー基板を製作するための方法 - Google Patents

ドナー基板を製作するための方法 Download PDF

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Publication number
JP2025501705A
JP2025501705A JP2024535252A JP2024535252A JP2025501705A JP 2025501705 A JP2025501705 A JP 2025501705A JP 2024535252 A JP2024535252 A JP 2024535252A JP 2024535252 A JP2024535252 A JP 2024535252A JP 2025501705 A JP2025501705 A JP 2025501705A
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JP
Japan
Prior art keywords
substrate
donor
hours
layer
donor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024535252A
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English (en)
Japanese (ja)
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JP2025501705A5 (https=
Inventor
セバスチャン ティベール，
クレマン ガウマー，
セドリック チャールズ‐アルフレッド，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2025501705A publication Critical patent/JP2025501705A/ja
Publication of JP2025501705A5 publication Critical patent/JP2025501705A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
JP2024535252A 2021-12-23 2022-12-23 ドナー基板を製作するための方法 Pending JP2025501705A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2114469A FR3131436B1 (fr) 2021-12-23 2021-12-23 Procede de fabrication d’un substrat donneur
FR2114469 2021-12-23
PCT/EP2022/087749 WO2023118574A1 (fr) 2021-12-23 2022-12-23 Procede de fabrication d'un substrat donneur

Publications (2)

Publication Number Publication Date
JP2025501705A true JP2025501705A (ja) 2025-01-23
JP2025501705A5 JP2025501705A5 (https=) 2025-12-04

Family

ID=81345982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024535252A Pending JP2025501705A (ja) 2021-12-23 2022-12-23 ドナー基板を製作するための方法

Country Status (8)

Country Link
US (1) US20250054745A1 (https=)
EP (1) EP4453996A1 (https=)
JP (1) JP2025501705A (https=)
KR (1) KR20240128923A (https=)
CN (1) CN118476009A (https=)
FR (1) FR3131436B1 (https=)
TW (1) TW202343535A (https=)
WO (1) WO2023118574A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3157060A1 (fr) * 2023-12-19 2025-06-20 Soitec Régénération d'un substrat donneur pour la fabrication d'une structure POI

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005229455A (ja) * 2004-02-16 2005-08-25 Shin Etsu Chem Co Ltd 複合圧電基板
FR3079346B1 (fr) * 2018-03-26 2020-05-29 Soitec Procede de fabrication d'un substrat donneur pour le transfert d'une couche piezoelectrique, et procede de transfert d'une telle couche piezoelectrique
FR3079345B1 (fr) * 2018-03-26 2020-02-21 Soitec Procede de fabrication d'un substrat pour dispositif radiofrequence

Also Published As

Publication number Publication date
WO2023118574A1 (fr) 2023-06-29
TW202343535A (zh) 2023-11-01
US20250054745A1 (en) 2025-02-13
CN118476009A (zh) 2024-08-09
KR20240128923A (ko) 2024-08-27
FR3131436A1 (fr) 2023-06-30
EP4453996A1 (fr) 2024-10-30
FR3131436B1 (fr) 2025-04-25

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