TW202343248A - Abnormal display method and abnormal display device for motherboard - Google Patents
Abnormal display method and abnormal display device for motherboard Download PDFInfo
- Publication number
- TW202343248A TW202343248A TW111114834A TW111114834A TW202343248A TW 202343248 A TW202343248 A TW 202343248A TW 111114834 A TW111114834 A TW 111114834A TW 111114834 A TW111114834 A TW 111114834A TW 202343248 A TW202343248 A TW 202343248A
- Authority
- TW
- Taiwan
- Prior art keywords
- abnormal
- message
- light
- light signal
- signal
- Prior art date
Links
- 230000002159 abnormal effect Effects 0.000 title claims abstract description 126
- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000005856 abnormality Effects 0.000 claims abstract description 96
- 238000012360 testing method Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 description 12
- 101100152436 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) TAT2 gene Proteins 0.000 description 7
- 238000011161 development Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 101150031663 LAB5 gene Proteins 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/325—Display of status information by lamps or LED's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Controls And Circuits For Display Device (AREA)
- Alarm Systems (AREA)
Abstract
Description
本發明是有關於一種異常顯示方法以及異常顯示裝置,且特別是有關於一種用於主機板的異常顯示方法以及異常顯示裝置。The present invention relates to an abnormality display method and an abnormality display device, and in particular to an abnormality display method and an abnormality display device for a motherboard.
一般來說,電子裝置的主機板的上電時序的開發階段是在客戶端或生產製造端執行。當客戶端或生產製造端遭遇到主機板無法完成上電時序時,客戶端或生產製造端都無法在第一時間獲知主機板的異常原因。因此,都會交由開發端的硬體工程師來負責量測主機板上的時序訊號並找出問題點,從而找出主機板的異常原因。然而,上述的流程會延長開發階段的時程。如何有效縮短排除主機板異常的時程,是本領域技術人員的研究重點之一。Generally speaking, the development stage of the power-on sequence of the motherboard of the electronic device is performed on the client side or the manufacturing side. When the client or the manufacturing end encounters that the motherboard cannot complete the power-on sequence, neither the client nor the manufacturing end is able to know the cause of the motherboard abnormality at the first time. Therefore, it is left to the hardware engineers on the development side to measure the timing signals on the motherboard and find the problem points, so as to find out the cause of the motherboard anomaly. However, the above process will extend the development phase. How to effectively shorten the time required to troubleshoot motherboard abnormalities is one of the research focuses of those skilled in the art.
本發明提供一種用於主機板的異常顯示方法以及異常顯示裝置,能夠有效縮短排除主機板異常的時程。The present invention provides an abnormality display method and an abnormality display device for a motherboard, which can effectively shorten the time required to eliminate motherboard abnormalities.
本發明的異常顯示方法包括:在主機板上電時接收主機板在進行上電自我測試前的多個訊號;依據所述多個訊號的至少其中之一的異常以產生異常訊息;依據異常訊息以及訊息與燈號對照表來控制顯示燈,以使顯示燈產生對應於異常訊息的異常燈號。The abnormality display method of the present invention includes: receiving a plurality of signals from the motherboard before power-on self-test when the motherboard is powered on; generating an abnormality message based on the abnormality of at least one of the plurality of signals; and generating an abnormality message based on the abnormality message. And a message and light signal comparison table to control the display light, so that the display light generates abnormal light signals corresponding to the abnormal message.
本發明的異常顯示裝置包括顯示燈以及控制器。控制器耦接於顯示燈以及主機板。控制器存有訊息與燈號對照表。控制器在主機板上電時接收主機板在進行上電自我測試前的多個訊號,依據所述多個訊號的至少其中之一的異常以產生異常訊息,依據異常訊息以及訊息與燈號對照表來控制顯示燈,以使顯示燈產生對應於異常訊息的異常燈號。The abnormality display device of the present invention includes a display light and a controller. The controller is coupled to the display light and the motherboard. The controller has a message and light signal comparison table. When the motherboard is powered on, the controller receives multiple signals from the motherboard before power-on self-test, generates an abnormal message based on the abnormality of at least one of the multiple signals, and compares the abnormal message and the message with the light signal. The table is used to control the display light so that the display light generates an abnormal light signal corresponding to the abnormal message.
基於上述,本發明的異常顯示方法以及異常顯示裝置是在主機板上電時接收主機板在進行上電自我測試前的多個訊號,依據所述多個訊號的異常以產生異常訊息。此外,本發明利用異常訊息來使顯示燈產生對應於所述多個訊號的異常的異常燈號。由於上電時的所述多個訊號是在進行上電自我測試前被接收,因此本發明的異常顯示方法以及異常顯示裝置能夠在較早的時間就產生異常燈號。如此一來,客戶端或生產製造端能夠依據異常燈號來及早獲知主機板的異常原因,從而有效縮短排除主機板異常的時程。Based on the above, the abnormality display method and the abnormality display device of the present invention receive a plurality of signals from the motherboard before power-on self-test when the motherboard is powered on, and generate an abnormality message based on the abnormalities of the plurality of signals. In addition, the present invention uses abnormal information to cause the display lamp to generate an abnormal light signal corresponding to the abnormality of the plurality of signals. Since the plurality of signals during power-on are received before the power-on self-test is performed, the abnormality display method and the abnormality display device of the present invention can generate abnormal light signals at an earlier time. In this way, the client or manufacturing end can learn the cause of the motherboard abnormality as early as possible based on the abnormal light signal, thereby effectively shortening the time to troubleshoot the motherboard abnormality.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.
本發明的部份實施例接下來將會配合附圖來詳細描述,以下的描述所引用的元件符號,當不同附圖出現相同的元件符號將視為相同或相似的元件。這些實施例只是本發明的一部份,並未揭示所有本發明的可實施方式。更確切的說,這些實施例只是本發明的專利申請範圍中的範例。Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the invention.
請同時參考圖1以及圖2,圖1是依據本發明一實施例所繪示的異常顯示方法的流程圖圖。圖2是依據本發明一實施例所繪示的異常顯示裝置的的示意圖。在本實施例中,異常顯示方法S100會基於在主機板MB上電(power-on)時的多個訊號的異常來提供異常燈號。在本實施例中,異常顯示方法S100適用於異常顯示裝置100。異常顯示裝置100包括顯示燈110以及控制器120。控制器120耦接於顯示燈110以及主機板MB。在步驟S110中,在主機板MB上電時,控制器120接收主機板MB在進行上電自我測試(Power On Self Test,POST)之前的訊號S1~Sm。在本實施例中,訊號S1~Sm分別可以是在主機板MB上電時的狀態指示訊號或電源訊號。m是大於1的正整數。Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 1 is a flow chart of an exception display method according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an abnormality display device according to an embodiment of the present invention. In this embodiment, the abnormality display method S100 provides abnormal light signals based on the abnormality of multiple signals when the motherboard MB is powered on. In this embodiment, the abnormality display method S100 is applicable to the
在步驟S120中,控制器120依據訊號S1~Sm的至少其中之一的異常以產生異常訊息SAB1~SABn的其中之一。n是大於1的正整數。在本實施例中,一旦控制器120判斷出訊號S1~Sm的至少其中一者的波型發生異常,控制器120產生對應的異常訊息SAB1~SABn。也就是說,異常訊息SAB1~SABn分別對應於訊號S1~Sm的至少其中之一的波型異常。舉例來說,當訊號S1的波型被判斷出發生異常時,控制器120產生對應於訊號S1的異常的異常訊息SAB1。另舉例來說,當訊號S2的波型被判斷出發生異常時,控制器120產生對應於訊號S2的異常的異常訊息SAB2。再舉例來說,當訊號S1、S2的波型被判斷出發生異常時,控制器120產生對應於訊號S1、S2的異常的異常訊息SAB3。In step S120, the
在步驟S130中,控制器120依據異常訊息SAB1~SABn的其中之一以及訊息與燈號對照表TB來控制顯示燈110,從而使顯示燈110產生對應的異常燈號(即,異常燈號LAB1~LABn的其中之一)。In step S130, the
在本實施例中,異常燈號LAB1~LABn可以是在主機板進行上電自我測試之前以及進行上電自我測試的期間被產生。In this embodiment, the abnormal light signals LAB1 ~ LABn may be generated before and during the power-on self-test of the motherboard.
在此值得一提的是,在主機板MB上電時,訊號S1~Sm是在主機板MB進行上電自我測試前就被接收。異常顯示方法S100以及 100能夠在較早的時間就產生異常燈號LAB1~LABn的其中之一。因此,客戶端或生產製造端能夠依據異常燈號LAB1~LABn的其中之一來及早獲知主機板MB的異常原因並告知開發端的硬體工程師。如此一來,排除主機板MB異常的時程能夠有效地被縮短。It is worth mentioning here that when the motherboard MB is powered on, the signals S1~Sm are received before the motherboard MB performs a power-on self-test. Abnormal display methods S100 and 100 can generate one of the abnormal light signals LAB1~LABn at an earlier time. Therefore, the client or manufacturing side can early learn the cause of the abnormality of the motherboard MB based on one of the abnormal signals LAB1~LABn and inform the hardware engineer on the development side. In this way, the time required to troubleshoot motherboard MB abnormalities can be effectively shortened.
進一步來說明,在步驟S120中,控制器120會判斷訊號S1~Sm的時序分別是否符合上電時序。當所有的訊號S1~Sm的時序都符合上電時序時,控制器120停止提供異常訊息SAB1~SABn的其中之一。因此,異常燈號LAB1~LABn不會被產生。在另一方面,當訊號S1~Sm的至少其中之一不符合上電時序時,控制器120提供異常訊息SAB1~SABn的其中之一。To further explain, in step S120, the
在本實施例中,控制器儲存了訊息與燈號對照表TB。控制器120依據異常訊息SAB1~SABn的其中之一以及訊息與燈號對照表TB來產生對應的控制訊號SC1~SCn。基於訊息與燈號對照表TB,控制器120會依據異常訊息SAB1來產生控制訊號SC1,並依據異常訊息SAB2來產生控制訊號SC2。同理可推,控制器120會依據異常訊息SABn來產生控制訊號SCn。在此例中,顯示燈110反應於控制訊號SC1來產生異常燈號LAB1。因此,異常燈號LAB1對應於異常訊息SAB1。舉例來說,顯示燈110反應於控制訊號SC2來產生異常燈號LAB2。因此,異常燈號LAB2對應於異常訊息SAB2。在本實施例中,異常燈號LAB1~LABn彼此不相同。In this embodiment, the controller stores the message and light signal comparison table TB. The
在本實施例中,控制器120可以是外接於主機板MB的控制電路或轉換電路,本發明並不以此為限。顯示燈110例如是設置於電源按鈕、主機機殼或主機板MB上的任意形式的指示燈,本發明並不以此為限。控制器120例如是內嵌式控制器、數位訊號處理器(Digital Signal Processor,DSP)、現場可程式化邏輯閘陣列(Field Programmable Gate Array,FPGA)、可程式化控制器、特殊應用積體電路(Application Specific Integrated Circuits,ASIC)、可程式化邏輯裝置(Programmable Logic Device,PLD)或其他類似裝置或這些裝置的組合。顯示燈110可以是任意形式的指示燈。在一些實施例中,控制器120可以被設置於主機板MB上的既有控制電路。因此,控制器120以及顯示燈110不需要由額外的外部電路或外部元件來實現。In this embodiment, the
請同時參考圖3,圖3是依據本發明另一實施例所繪示的異常顯示裝置的的示意圖。在本實施例中,異常顯示裝置200包括顯示燈210以及控制器220。控制器220耦接於顯示燈110以及主機板MB。控制器220被設置於主機板MB上。在主機板MB上電時,控制器220接收主機板MB在進行上電自我測試之前的訊號S1~Sm。Please also refer to FIG. 3 , which is a schematic diagram of an abnormality display device according to another embodiment of the present invention. In this embodiment, the
在本實施例中,訊號S1~Sm分別可以是在主機板MB上電時的狀態指示訊號或電源訊號。舉例來說,訊號S1~S4分別是電源訊號。進一步來說,訊號S1是用於主機板MB上的記憶體元件的電源訊號。訊號S2是電源軌的電源訊號(如,Vbus或VDD)。訊號S3是用於風扇的電源訊號。訊號S4是深度睡眠喚醒電源(Deep Sleep Well,DSW)訊號。訊號S5~Sm分別是狀態指示訊號。訊號S5是控制器220本身所產生的待機狀態指示訊號(如,PCH_DPWROK)。訊號S6~Sm來自於路徑控制晶片C1。路徑控制晶片C1例如是平台路徑控制器(Platform Controller Hub,PCH)。進一步來說,訊號S6是深度睡眠狀態指示訊號(如,SLP_SUS#)。訊號S7是eSPI匯流排介面的指示訊號,例如是Virtual Wire(VW)上的訊號。訊號S8是睡眠模式狀態指示訊號,例如是SLP_S3、SLP_S4。訊號S9是路徑控制晶片C1的重置訊號(如,PCH PLTRST#)。In this embodiment, the signals S1 ~ Sm may respectively be status indication signals or power signals when the motherboard MB is powered on. For example, the signals S1~S4 are power signals respectively. Furthermore, the signal S1 is a power signal for the memory device on the motherboard MB. Signal S2 is the power supply signal of the power rail (eg, Vbus or VDD). Signal S3 is the power signal for the fan. Signal S4 is a Deep Sleep Well (DSW) signal. Signals S5~Sm are status indication signals respectively. Signal S5 is a standby state indication signal (eg, PCH_DPWROK) generated by the
在本實施例中,控制器220依據訊號S1~Sm的至少其中之一的異常以產生異常訊息SAB1~SABn的其中之一。控制器220依據異常訊息SAB1~SABn的其中之一以及訊息與燈號對照表TB來控制顯示燈210產生異常燈號LAB1~LABn。在本實施例中,控制器220包括記憶體221。控制器220會透過記憶體221儲存訊息與燈號對照表TB。記憶體221可以是任何型態的固定或可移動隨機存取記憶體(random access memory,RAM)、唯讀記憶體(read-only memory,ROM)、快閃記憶體(flash memory)或類似元件或上述元件的組合。In this embodiment, the
舉例來說,訊息與燈號對照表TB的至少部分如表1所示。For example, at least part of the message and light signal comparison table TB is shown in Table 1.
表1:
在表1中,控制器220會基於訊號S5所發生的異常來產生異常訊息SAB1,並依據異常訊息SAB1以及表1來控制顯示燈210產生異常燈號LAB1。控制器220會基於訊號S6所發生的異常來產生異常訊息SAB2,並依據異常訊息SAB2以及表1來控制顯示燈210產生異常燈號LAB2。控制器220會基於訊號S7所發生的異常來產生異常訊息SAB3,並依據異常訊息SAB3以及表1來控制顯示燈210產生異常燈號LAB3。控制器220會基於訊號S8所發生的異常來產生異常訊息SAB4,並依據異常訊息SAB4以及表1來控制顯示燈210產生異常燈號LAB4。此外,控制器220會基於訊號S9所發生的異常來產生異常訊息SAB5,並依據異常訊息SAB5以及表1來控制顯示燈210產生異常燈號LAB5。在本實施例中,異常燈號LAB1~LABn是在主機板進行上電自我測試之前以及進行上電自我測試的期間被產生。In Table 1, the
舉例來說,客戶端或生產製造端依據異常燈號LAB1而直接獲知訊號S5(如,PCH_DPWROK)的波型或時序發生異常,並將訊號S5的異常告知開發端的硬體工程師。硬體工程師則可以對訊號S5的異常進行排除。如此一來,排除主機板MB異常的時程能夠有效地被縮短。For example, the client or manufacturing side directly learns that the waveform or timing of signal S5 (for example, PCH_DPWROK) is abnormal based on the abnormal signal LAB1, and notifies the hardware engineer of the development side of the abnormality of signal S5. Hardware engineers can eliminate abnormalities in signal S5. In this way, the time required to troubleshoot motherboard MB abnormalities can be effectively shortened.
在本實施例中,異常燈號LAB1~LABn彼此不同。舉例來說,異常燈號LAB1~LABn的閃爍次數彼此不同。因此,客戶端或生產製造端依據當前異常燈號的閃爍次數來獲知對應的異常訊息。進一步地,異常燈號LAB1~LABn的閃爍次數彼此不同但異常燈號LAB1~LABn的閃爍頻率大致相同。在一些實施例中,異常燈號LAB1~LABn的閃爍次數以及閃爍頻率彼此不同。In this embodiment, the abnormal light signals LAB1~LABn are different from each other. For example, the number of flashes of the abnormal light signals LAB1~LABn are different from each other. Therefore, the client or manufacturing end obtains the corresponding abnormal information based on the number of flashes of the current abnormal light signal. Furthermore, the flashing times of the abnormal light signals LAB1~LABn are different from each other but the flashing frequencies of the abnormal light signals LAB1~LABn are approximately the same. In some embodiments, the number of flashes and the flashing frequency of the abnormal light signals LAB1 ~ LABn are different from each other.
請同時參考圖1、圖3以及圖4,圖4是依據本發明一實施例所繪示的異常燈號的循環顯示流程圖。在本實施例中,步驟S130包括步驟S131、S132。在步驟S131中,控制器220控制顯示燈210產生起始燈號。在步驟S132中,控制器220控制顯示燈210產生當前異常燈號(異常燈號LAB1~LABn的其中之一)。接下來,控制器220回到步驟S131以控制顯示燈210產生起始燈號。步驟S131、S132分別是不同的時段。也就是說,控制器220在第一時段(即,步驟S131)控制顯示燈210產生起始燈號,並且在第二時段(即,步驟S132)控制顯示燈210產生異常燈號。基於第一時段以及第二時段,起始燈號以及異常燈號被循環產生。此外,起始燈號的閃爍頻率不同於異常燈號的閃爍頻率。步驟S131與S132以及步驟S132與S131之間都具有一預設時間間隔。Please refer to FIG. 1 , FIG. 3 and FIG. 4 at the same time. FIG. 4 is a cycle display flow chart of abnormal light signals according to an embodiment of the present invention. In this embodiment, step S130 includes steps S131 and S132. In step S131, the
舉例來說明,當訊號S5發生異常時,異常訊息SAB1被產生。因此,在步驟S131中,起始燈號每1秒閃爍4次。在預設時間間隔(如,1秒)後,異常燈號LAB1在步驟S132中被產生。異常燈號LAB1每1秒閃爍1次,共閃爍1次。也就是說,起始燈號的閃爍頻率是異常燈號LAB1的閃爍頻率的4倍。隨後,在預設時間間隔(如,1秒)後,起始燈號在步驟S131中每1秒閃爍4次。因此,步驟S131、S132會持續循環下去,直到主機板MB關機、斷電或排除訊號S5的異常為止。For example, when an abnormality occurs in the signal S5, the abnormal message SAB1 is generated. Therefore, in step S131, the start light flashes 4 times every 1 second. After a preset time interval (eg, 1 second), the abnormal light signal LAB1 is generated in step S132. Abnormal light LAB1 flashes once every 1 second, flashing once in total. In other words, the flashing frequency of the initial light signal is four times the flashing frequency of the abnormal light signal LAB1. Subsequently, after a preset time interval (eg, 1 second), the start light flashes 4 times every 1 second in step S131. Therefore, steps S131 and S132 will continue to loop until the motherboard MB is shut down, powered off, or the abnormality of the signal S5 is eliminated.
另舉例來說明,當訊號S6發生異常時,異常訊息SAB2被產生。因此,在步驟S131中,起始燈號每1秒閃爍4次。在預設時間間隔(如,1秒)後,異常燈號LAB1在步驟S132中被產生。異常燈號LAB1每1秒閃爍1次,共閃爍2次。接下來,步驟S131、S132會持續循環下去,直到主機板MB關機、斷電或排除訊號S6的異常為止。異常燈號LAB1、LAB2的閃爍次數彼此不同。For another example, when an abnormality occurs in the signal S6, the abnormal message SAB2 is generated. Therefore, in step S131, the start light flashes 4 times every 1 second. After a preset time interval (eg, 1 second), the abnormal light signal LAB1 is generated in step S132. Abnormal light LAB1 flashes once every 1 second, flashing 2 times in total. Next, steps S131 and S132 will continue to loop until the motherboard MB is shut down, powered off, or the abnormality of the signal S6 is eliminated. The number of flashes of the abnormal lights LAB1 and LAB2 are different from each other.
應注意的是,異常燈號LAB1、LAB2的閃爍頻率彼此相同,並且不同於起始燈號的閃爍頻率。因此,客戶端或生產製造端能夠依據起始燈號以及當前異常燈號的閃爍頻率的差異來直觀地獲知當前異常燈號的產生。此外,透過當前異常燈號的閃爍次數,客戶端或生產製造端能夠來輕易地識別出當前異常燈號是異常燈號LAB1~LABn的其中之一。It should be noted that the flashing frequencies of the abnormal light signals LAB1 and LAB2 are the same as each other and different from the flashing frequency of the initial light signal. Therefore, the client or manufacturing end can intuitively know the occurrence of the current abnormal light signal based on the difference between the initial light signal and the flashing frequency of the current abnormal light signal. In addition, through the number of flashes of the current abnormal light signal, the client or manufacturing end can easily identify that the current abnormal light signal is one of the abnormal light signals LAB1~LABn.
綜上所述,由於上電時的所述多個訊號是在進行上電自我測試前被接收,因此本發明的異常顯示方法以及異常顯示裝置能夠在較早的時間就產生異常燈號。如此一來,客戶端或生產製造端能夠依據異常燈號來及早獲知主機板的異常原因,從而有效縮短排除主機板異常的時程。此外,起始燈號以及當前異常燈號的閃爍頻率明顯不同。因此,客戶端或生產製造端能夠依據起始燈號以及當前異常燈號的閃爍頻率的差異來直觀地獲知當前異常燈號的產生。此外,透過當前異常燈號的閃爍次數,客戶端或生產製造端能夠來輕易地識別出當前異常燈號。To sum up, since the plurality of signals during power-on are received before the power-on self-test is performed, the abnormality display method and the abnormality display device of the present invention can generate abnormal light signals at an earlier time. In this way, the client or manufacturing end can learn the cause of the motherboard abnormality as early as possible based on the abnormal light signal, thereby effectively shortening the time to troubleshoot the motherboard abnormality. In addition, the flashing frequencies of the initial light signal and the current abnormal light signal are obviously different. Therefore, the client or manufacturing end can intuitively know the occurrence of the current abnormal light signal based on the difference between the initial light signal and the flashing frequency of the current abnormal light signal. In addition, through the number of flashes of the current abnormal light signal, the client or manufacturing end can easily identify the current abnormal light signal.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.
100、200:異常顯示裝置
110、210:顯示燈
120、220:控制器
221:記憶體
C1:路徑控制晶片
LAB1~LABn:異常燈號
MB:主機板
S1~Sm:訊號
S100:異常顯示方法
S110、S120、S130、S131、S132:步驟
SAB1~SABn:異常訊息
SC1~SCn:控制訊號
TB:訊息與燈號對照表
100, 200:
圖1是依據本發明一實施例所繪示的異常顯示方法的流程圖圖。 圖2是依據本發明一實施例所繪示的異常顯示裝置的的示意圖。 圖3是依據本發明另一實施例所繪示的異常顯示裝置的的示意圖。 圖4是依據本發明一實施例所繪示的異常燈號的循環顯示流程圖。 FIG. 1 is a flowchart of an exception display method according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an abnormality display device according to an embodiment of the present invention. FIG. 3 is a schematic diagram of an abnormality display device according to another embodiment of the present invention. FIG. 4 is a cycle display flow chart of abnormal light signals according to an embodiment of the present invention.
S100:異常顯示方法 S100: Abnormal display method
S110、S120、S130:步驟 S110, S120, S130: steps
Claims (10)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111114834A TWI807789B (en) | 2022-04-19 | 2022-04-19 | Abnormal display method and abnormal display device for motherboard |
CN202310146101.9A CN116909850A (en) | 2022-04-19 | 2023-02-21 | Abnormality display method and abnormality display device for motherboard |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111114834A TWI807789B (en) | 2022-04-19 | 2022-04-19 | Abnormal display method and abnormal display device for motherboard |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI807789B TWI807789B (en) | 2023-07-01 |
TW202343248A true TW202343248A (en) | 2023-11-01 |
Family
ID=88149247
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111114834A TWI807789B (en) | 2022-04-19 | 2022-04-19 | Abnormal display method and abnormal display device for motherboard |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN116909850A (en) |
TW (1) | TWI807789B (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1760840A (en) * | 2004-10-11 | 2006-04-19 | 佛山市顺德区顺达电脑厂有限公司 | Method for displaying debugging codes by using LED lamps on keyboard of computer |
CN100517262C (en) * | 2006-03-29 | 2009-07-22 | 鸿富锦精密工业(深圳)有限公司 | Master plate monitoring system and method |
TW200819971A (en) * | 2006-10-27 | 2008-05-01 | Inventec Corp | Debugging method for a motherboard |
TW201109913A (en) * | 2009-09-02 | 2011-03-16 | Inventec Corp | Main system board error-detecting system and its pluggable error-detecting board |
-
2022
- 2022-04-19 TW TW111114834A patent/TWI807789B/en active
-
2023
- 2023-02-21 CN CN202310146101.9A patent/CN116909850A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
TWI807789B (en) | 2023-07-01 |
CN116909850A (en) | 2023-10-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8627132B2 (en) | Autonomous multi-device event synchronization and sequencing technique eliminating master and slave assignments | |
TWI786228B (en) | Semiconductor device and failure detection method of the semiconductor device | |
JP2006251886A (en) | Microcomputer | |
JP2020155975A (en) | Semiconductor device and control method of semiconductor device | |
US20020130695A1 (en) | System and method for dynamically controlling an integrated circuit's clock | |
TW202343248A (en) | Abnormal display method and abnormal display device for motherboard | |
JP2012003692A (en) | Voltage detection system and control method thereof | |
TWI668563B (en) | Data storage determining device | |
JPH09146653A (en) | Information processor | |
KR101679375B1 (en) | Semiconductor ic monitoring aging and method thereof | |
JP2020009398A (en) | Method for controlling fan in electronic system | |
JP2010109717A (en) | Semiconductor integrated circuit, and method of controlling the same | |
TWI779930B (en) | Clock monitor circuit, microcontroller, and control method thereof | |
TWI767831B (en) | Driving device and driving program updating method for fan | |
US11764771B2 (en) | Event detection control device and method for circuit system controlled by pulse wave modulation signal | |
JP2014215178A (en) | Semiconductor device | |
JP2019121033A (en) | Control device for aircrafts and mutual diagnosis method | |
CN111522423B (en) | Reset signal generating circuit and computer system | |
JP2015176349A (en) | Information processor, failure detection method and program | |
JP2842840B2 (en) | Semiconductor device burn-in test equipment | |
JP2004061114A (en) | Self-diagnosis test circuit and method | |
JP2000003945A (en) | Semiconductor chip and semiconductor wafer | |
JP2010003199A (en) | Semiconductor integrated circuit device | |
JPH01183148A (en) | Semiconductor integrated circuit | |
KR101332078B1 (en) | Device for power on reset |