TW202343248A - Abnormal display method and abnormal display device for motherboard - Google Patents

Abstract

An abnormal display method and an abnormal display device for a motherboard are provided. The abnormal display method includes: receiving a plurality of signals before a power-on self-test of the mainboard when the mainboard is powered on; generating an abnormal message according to the abnormality of at least one of the plurality of signals; controlling a display light according to the abnormality message and a message and light comparison table to, so that a display light generates an abnormal light signal corresponding to the abnormal message.

Description

Abnormality display method and abnormality display device for motherboard

The present invention relates to an abnormality display method and an abnormality display device, and in particular to an abnormality display method and an abnormality display device for a motherboard.

Generally speaking, the development stage of the power-on sequence of the motherboard of the electronic device is performed on the client side or the manufacturing side. When the client or the manufacturing end encounters that the motherboard cannot complete the power-on sequence, neither the client nor the manufacturing end is able to know the cause of the motherboard abnormality at the first time. Therefore, it is left to the hardware engineers on the development side to measure the timing signals on the motherboard and find the problem points, so as to find out the cause of the motherboard anomaly. However, the above process will extend the development phase. How to effectively shorten the time required to troubleshoot motherboard abnormalities is one of the research focuses of those skilled in the art.

The present invention provides an abnormality display method and an abnormality display device for a motherboard, which can effectively shorten the time required to eliminate motherboard abnormalities.

The abnormality display method of the present invention includes: receiving a plurality of signals from the motherboard before power-on self-test when the motherboard is powered on; generating an abnormality message based on the abnormality of at least one of the plurality of signals; and generating an abnormality message based on the abnormality message. And a message and light signal comparison table to control the display light, so that the display light generates abnormal light signals corresponding to the abnormal message.

The abnormality display device of the present invention includes a display light and a controller. The controller is coupled to the display light and the motherboard. The controller has a message and light signal comparison table. When the motherboard is powered on, the controller receives multiple signals from the motherboard before power-on self-test, generates an abnormal message based on the abnormality of at least one of the multiple signals, and compares the abnormal message and the message with the light signal. The table is used to control the display light so that the display light generates an abnormal light signal corresponding to the abnormal message.

Based on the above, the abnormality display method and the abnormality display device of the present invention receive a plurality of signals from the motherboard before power-on self-test when the motherboard is powered on, and generate an abnormality message based on the abnormalities of the plurality of signals. In addition, the present invention uses abnormal information to cause the display lamp to generate an abnormal light signal corresponding to the abnormality of the plurality of signals. Since the plurality of signals during power-on are received before the power-on self-test is performed, the abnormality display method and the abnormality display device of the present invention can generate abnormal light signals at an earlier time. In this way, the client or manufacturing end can learn the cause of the motherboard abnormality as early as possible based on the abnormal light signal, thereby effectively shortening the time to troubleshoot the motherboard abnormality.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the invention.

Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 1 is a flow chart of an exception display method according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an abnormality display device according to an embodiment of the present invention. In this embodiment, the abnormality display method S100 provides abnormal light signals based on the abnormality of multiple signals when the motherboard MB is powered on. In this embodiment, the abnormality display method S100 is applicable to the abnormality display device 100 . The abnormality display device 100 includes a display lamp 110 and a controller 120 . The controller 120 is coupled to the display light 110 and the motherboard MB. In step S110, when the motherboard MB is powered on, the controller 120 receives the signals S1~Sm before the motherboard MB performs a power on self test (Power On Self Test, POST). In this embodiment, the signals S1 ~ Sm may respectively be status indication signals or power signals when the motherboard MB is powered on. m is a positive integer greater than 1.

In step S120, the controller 120 generates one of the abnormal messages SAB1~SABn according to the abnormality of at least one of the signals S1~Sm. n is a positive integer greater than 1. In this embodiment, once the controller 120 determines that the waveform of at least one of the signals S1 to Sm is abnormal, the controller 120 generates the corresponding abnormality messages SAB1 to SABn. That is to say, the abnormal messages SAB1~SABn respectively correspond to the wave pattern abnormality of at least one of the signals S1~Sm. For example, when the wave pattern of the signal S1 is determined to be abnormal, the controller 120 generates the abnormality message SAB1 corresponding to the abnormality of the signal S1. For another example, when the wave pattern of the signal S2 is determined to be abnormal, the controller 120 generates the abnormality message SAB2 corresponding to the abnormality of the signal S2. For another example, when the waveforms of the signals S1 and S2 are determined to be abnormal, the controller 120 generates the abnormality message SAB3 corresponding to the abnormality of the signals S1 and S2.

In step S130, the controller 120 controls the display lamp 110 according to one of the abnormal messages SAB1~SABn and the message and light signal comparison table TB, so that the display lamp 110 generates a corresponding abnormal light signal (ie, the abnormal light signal LAB1 ~ one of LABn).

In this embodiment, the abnormal light signals LAB1 ~ LABn may be generated before and during the power-on self-test of the motherboard.

It is worth mentioning here that when the motherboard MB is powered on, the signals S1~Sm are received before the motherboard MB performs a power-on self-test. Abnormal display methods S100 and 100 can generate one of the abnormal light signals LAB1~LABn at an earlier time. Therefore, the client or manufacturing side can early learn the cause of the abnormality of the motherboard MB based on one of the abnormal signals LAB1~LABn and inform the hardware engineer on the development side. In this way, the time required to troubleshoot motherboard MB abnormalities can be effectively shortened.

To further explain, in step S120, the controller 120 determines whether the timing of the signals S1~Sm respectively meets the power-on timing. When the timing of all signals S1 ~ Sm matches the power-on sequence, the controller 120 stops providing one of the abnormal messages SAB1 ~ SABn. Therefore, abnormal light signals LAB1~LABn will not be generated. On the other hand, when at least one of the signals S1 ~ Sm does not comply with the power-on sequence, the controller 120 provides one of the abnormal messages SAB1 ~ SABn.

In this embodiment, the controller stores the message and light signal comparison table TB. The controller 120 generates corresponding control signals SC1 ~ SCn according to one of the abnormal messages SAB1 ~ SABn and the message and light signal comparison table TB. Based on the message and light signal comparison table TB, the controller 120 generates the control signal SC1 according to the abnormal message SAB1 and generates the control signal SC2 according to the abnormal message SAB2. By the same token, the controller 120 will generate the control signal SCn according to the abnormal message SABn. In this example, the display light 110 responds to the control signal SC1 to generate the abnormal light signal LAB1. Therefore, the abnormal light signal LAB1 corresponds to the abnormal message SAB1. For example, the display light 110 responds to the control signal SC2 to generate the abnormal light signal LAB2. Therefore, the abnormal light signal LAB2 corresponds to the abnormal message SAB2. In this embodiment, the abnormal light signals LAB1 ~ LABn are different from each other.

In this embodiment, the controller 120 may be a control circuit or a conversion circuit external to the motherboard MB, but the invention is not limited thereto. The display light 110 is, for example, any form of indicator light provided on the power button, the host casing or the motherboard MB, and the invention is not limited thereto. The controller 120 is, for example, an embedded controller, a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), a programmable controller, or a special application integrated circuit. (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD) or other similar devices or a combination of these devices. The display light 110 can be any form of indicator light. In some embodiments, the controller 120 may be disposed on an existing control circuit on the motherboard MB. Therefore, the controller 120 and the display light 110 do not need to be implemented by additional external circuits or external components.

Please also refer to FIG. 3 , which is a schematic diagram of an abnormality display device according to another embodiment of the present invention. In this embodiment, the abnormality display device 200 includes a display light 210 and a controller 220 . The controller 220 is coupled to the display light 110 and the motherboard MB. The controller 220 is provided on the motherboard MB. When the motherboard MB is powered on, the controller 220 receives the signals S1 ~ Sm of the motherboard MB before performing a power-on self-test.

In this embodiment, the signals S1 ~ Sm may respectively be status indication signals or power signals when the motherboard MB is powered on. For example, the signals S1~S4 are power signals respectively. Furthermore, the signal S1 is a power signal for the memory device on the motherboard MB. Signal S2 is the power supply signal of the power rail (eg, Vbus or VDD). Signal S3 is the power signal for the fan. Signal S4 is a Deep Sleep Well (DSW) signal. Signals S5~Sm are status indication signals respectively. Signal S5 is a standby state indication signal (eg, PCH_DPWROK) generated by the controller 220 itself. The signals S6~Sm come from the path control chip C1. The path control chip C1 is, for example, a platform path controller (Platform Controller Hub, PCH). Furthermore, the signal S6 is a deep sleep state indication signal (eg, SLP_SUS#). Signal S7 is the indication signal of the eSPI bus interface, such as the signal on Virtual Wire (VW). Signal S8 is a sleep mode status indication signal, such as SLP_S3 and SLP_S4. Signal S9 is the reset signal of path control chip C1 (eg, PCH PLTRST#).

In this embodiment, the controller 220 generates one of the abnormal messages SAB1 to SABn according to the abnormality of at least one of the signals S1 to Sm. The controller 220 controls the display lamp 210 to generate the abnormal light signals LAB1 ~ LABn according to one of the abnormal messages SAB1 ~ SABn and the message and light signal comparison table TB. In this embodiment, the controller 220 includes a memory 221 . The controller 220 will store the message and light signal comparison table TB through the memory 221 . Memory 221 may be any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory (flash memory) or similar components or a combination of the above elements.

For example, at least part of the message and light signal comparison table TB is shown in Table 1.

Table 1: Abnormal light signal Exception message Exception description LAB1 SAB1 An abnormality occurred in signal S5 LAB2 SAB2 An abnormality occurred in signal S6 LAB3 SAB3 An abnormality occurred in signal S7 LAB4 SAB4 An abnormality occurred in signal S8 LAB5 SAB5 An abnormality occurred in signal S9

In Table 1, the controller 220 generates the abnormality message SAB1 based on the abnormality in the signal S5, and controls the display lamp 210 to generate the abnormality light signal LAB1 according to the abnormality message SAB1 and Table 1. The controller 220 will generate the abnormality message SAB2 based on the abnormality in the signal S6, and control the display lamp 210 to generate the abnormality light signal LAB2 according to the abnormality message SAB2 and Table 1. The controller 220 will generate an abnormality message SAB3 based on the abnormality in the signal S7, and control the display lamp 210 to generate the abnormality light signal LAB3 according to the abnormality message SAB3 and Table 1. The controller 220 will generate the abnormality message SAB4 based on the abnormality in the signal S8, and control the display lamp 210 to generate the abnormality light signal LAB4 according to the abnormality message SAB4 and Table 1. In addition, the controller 220 will generate the abnormality message SAB5 based on the abnormality in the signal S9, and control the display lamp 210 to generate the abnormality light signal LAB5 according to the abnormality message SAB5 and Table 1. In this embodiment, the abnormal light signals LAB1 ~ LABn are generated before and during the power-on self-test of the motherboard.

For example, the client or manufacturing side directly learns that the waveform or timing of signal S5 (for example, PCH_DPWROK) is abnormal based on the abnormal signal LAB1, and notifies the hardware engineer of the development side of the abnormality of signal S5. Hardware engineers can eliminate abnormalities in signal S5. In this way, the time required to troubleshoot motherboard MB abnormalities can be effectively shortened.

In this embodiment, the abnormal light signals LAB1~LABn are different from each other. For example, the number of flashes of the abnormal light signals LAB1~LABn are different from each other. Therefore, the client or manufacturing end obtains the corresponding abnormal information based on the number of flashes of the current abnormal light signal. Furthermore, the flashing times of the abnormal light signals LAB1~LABn are different from each other but the flashing frequencies of the abnormal light signals LAB1~LABn are approximately the same. In some embodiments, the number of flashes and the flashing frequency of the abnormal light signals LAB1 ~ LABn are different from each other.

Please refer to FIG. 1 , FIG. 3 and FIG. 4 at the same time. FIG. 4 is a cycle display flow chart of abnormal light signals according to an embodiment of the present invention. In this embodiment, step S130 includes steps S131 and S132. In step S131, the controller 220 controls the display light 210 to generate a starting light signal. In step S132, the controller 220 controls the display lamp 210 to generate the current abnormal light signal (one of the abnormal light signals LAB1~LABn). Next, the controller 220 returns to step S131 to control the display light 210 to generate a starting light signal. Steps S131 and S132 are different time periods respectively. That is to say, the controller 220 controls the display lamp 210 to generate the initial light signal in the first period (ie, step S131 ), and controls the display lamp 210 to generate the abnormal light signal in the second period (ie, step S132 ). Based on the first time period and the second time period, the initial light signal and the abnormal light signal are generated cyclically. In addition, the flashing frequency of the initial light signal is different from the flashing frequency of the abnormal light signal. There is a preset time interval between steps S131 and S132 and between steps S132 and S131.

For example, when an abnormality occurs in the signal S5, the abnormal message SAB1 is generated. Therefore, in step S131, the start light flashes 4 times every 1 second. After a preset time interval (eg, 1 second), the abnormal light signal LAB1 is generated in step S132. Abnormal light LAB1 flashes once every 1 second, flashing once in total. In other words, the flashing frequency of the initial light signal is four times the flashing frequency of the abnormal light signal LAB1. Subsequently, after a preset time interval (eg, 1 second), the start light flashes 4 times every 1 second in step S131. Therefore, steps S131 and S132 will continue to loop until the motherboard MB is shut down, powered off, or the abnormality of the signal S5 is eliminated.

For another example, when an abnormality occurs in the signal S6, the abnormal message SAB2 is generated. Therefore, in step S131, the start light flashes 4 times every 1 second. After a preset time interval (eg, 1 second), the abnormal light signal LAB1 is generated in step S132. Abnormal light LAB1 flashes once every 1 second, flashing 2 times in total. Next, steps S131 and S132 will continue to loop until the motherboard MB is shut down, powered off, or the abnormality of the signal S6 is eliminated. The number of flashes of the abnormal lights LAB1 and LAB2 are different from each other.

It should be noted that the flashing frequencies of the abnormal light signals LAB1 and LAB2 are the same as each other and different from the flashing frequency of the initial light signal. Therefore, the client or manufacturing end can intuitively know the occurrence of the current abnormal light signal based on the difference between the initial light signal and the flashing frequency of the current abnormal light signal. In addition, through the number of flashes of the current abnormal light signal, the client or manufacturing end can easily identify that the current abnormal light signal is one of the abnormal light signals LAB1~LABn.

To sum up, since the plurality of signals during power-on are received before the power-on self-test is performed, the abnormality display method and the abnormality display device of the present invention can generate abnormal light signals at an earlier time. In this way, the client or manufacturing end can learn the cause of the motherboard abnormality as early as possible based on the abnormal light signal, thereby effectively shortening the time to troubleshoot the motherboard abnormality. In addition, the flashing frequencies of the initial light signal and the current abnormal light signal are obviously different. Therefore, the client or manufacturing end can intuitively know the occurrence of the current abnormal light signal based on the difference between the initial light signal and the flashing frequency of the current abnormal light signal. In addition, through the number of flashes of the current abnormal light signal, the client or manufacturing end can easily identify the current abnormal light signal.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100, 200: Abnormal display device 110, 210: Indicator light 120, 220: Controller 221:Memory C1: Path control chip LAB1~LABn: abnormal light signal MB: motherboard S1~Sm: signal S100: Abnormal display method S110, S120, S130, S131, S132: steps SAB1~SABn: exception message SC1~SCn: control signal TB: Message and signal comparison table

FIG. 1 is a flowchart of an exception display method according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an abnormality display device according to an embodiment of the present invention. FIG. 3 is a schematic diagram of an abnormality display device according to another embodiment of the present invention. FIG. 4 is a cycle display flow chart of abnormal light signals according to an embodiment of the present invention.

S100: Abnormal display method

S110, S120, S130: steps

Claims (10)

An abnormality display method for a motherboard, including: Receive multiple signals from the motherboard before performing a power-on self-test when the motherboard is powered on; Generate an abnormal message based on the abnormality of at least one of the signals; A display light is controlled according to the abnormal message and a message and light signal comparison table, so that the display light generates an abnormal light signal corresponding to the abnormal message. The exception display method as described in claim 1, wherein the step of generating the exception message based on the exception of at least one of the signals includes: Determine whether the timing of each of the signals complies with a power-on timing; and When the timing of at least one of the signals does not comply with the power-on timing, the exception message corresponding to the signal that does not comply with the power-on timing is generated. The abnormality display method as described in claim 1, wherein the step of controlling the indicator light based on the abnormal message and the message and light signal comparison table includes: Generate a first control signal based on a first abnormal message and the message and light signal comparison table; and A second control signal is generated according to a second abnormal message and a comparison table between the message and the light signal. The abnormality display method as described in claim 3, wherein the step of causing the display light to generate the abnormal light signal corresponding to the abnormal message includes: The first control signal is used to cause the display light to generate a first abnormal light signal corresponding to the first abnormal message, The second control signal is used to cause the display light to generate a second abnormal light signal corresponding to the second abnormal message, and The second abnormal light signal is different from the first abnormal light signal. The abnormality display method as described in claim 1, wherein the step of causing the display light to generate the abnormal light signal corresponding to the abnormal message includes: Generate a start signal in a first period; and The abnormal light signal is generated during a second period, Wherein based on the first period and the second period, the initial light signal and the abnormal light signal are generated cyclically, and The flashing frequency of the initial light signal is different from the flashing frequency of the abnormal light signal. An abnormality display device for a motherboard, including: a display light; and A controller is coupled to the display light and the motherboard. The controller stores a message and light signal comparison table. The controller is configured to receive the power-on self-test from the motherboard when the motherboard is powered on. A plurality of previous signals, an abnormal message is generated based on the abnormality of at least one of these signals, and the display light is controlled based on the abnormal message and the message and light signal comparison table, so that the display light generates a corresponding signal corresponding to the An exception signal for abnormal messages. The abnormality display device as described in claim 6, wherein the controller determines whether the timing of each of the signals conforms to a power-on sequence, and when the timing of at least one of the signals does not conform to the power-on sequence, a The exception message corresponds to the signal that does not comply with the power-on sequence. The abnormality display device as described in claim 6, wherein the controller includes: Memory, wherein the controller stores the message and the light signal comparison table through the memory. The abnormality display device as described in request item 6, wherein: The controller generates a first control signal based on a first abnormal message and the message and light signal comparison table, and uses the first control signal to cause the display light to generate a first abnormal light corresponding to the first abnormal message. No., The controller generates a second control signal based on a second abnormal message and the message and light signal comparison table, and uses the second control signal to cause the display light to generate a second abnormal light corresponding to the second abnormal message. number, and The second abnormal light signal is different from the first abnormal light signal. The abnormality display device as described in request item 6, wherein: The controller controls the display light to generate an initial light signal in a first period, and controls the display light to generate the abnormal light signal in a second period, Based on the first period and the second period, the initial light signal and the abnormal light signal are generated cyclically, and The flashing frequency of the initial light signal is different from the flashing frequency of the abnormal light signal.

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