TW202322684A - Circuit board structure - Google Patents

Abstract

A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall, and a second annular retaining wall. The conductive through hole penetrates through the third dielectric layer, the second dielectric layer and the fourth dielectric layer, and is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive through hole, and is electrically connected to the first external circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive through hole, and is electrically connected to the second external circuit layer and the second inner circuit layer.

Description

circuit board structure

The present invention relates to a substrate structure, and in particular to a circuit board structure.

In the existing circuit board, the design of the coaxial via (coaxial via) requires one or more insulating layers between the inner conductor layer and the outer conductor layer for insulation, and the way to form the insulating layer is through lamination. way to achieve. Therefore, there will be impedance mismatch at both ends of the coaxial via and electromagnetic interference (EMI) shielding gaps will appear, thereby affecting the integrity of high-frequency signals.

The invention provides a circuit board structure, which can effectively prevent energy loss and reduce noise interference, and can have better signal integrity.

The circuit board structure of the present invention comprises a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive via hole, a first annular A retaining wall and a second annular retaining wall. The base has an opening and includes a first dielectric layer, a second dielectric layer, a first internal circuit layer, a second internal circuit layer and a conductive connection layer. The opening penetrates the first dielectric layer. The first dielectric layer has a first surface and a second surface opposite to each other. The first internal circuit layer is configured on the first surface, and the second internal circuit layer is configured on the second surface. The conductive connection layer covers the inner wall of the opening and connects the first internal circuit layer and the second internal circuit layer. The second dielectric layer fills the opening, and the second dielectric layer has a third surface and a fourth surface opposite to each other. The third dielectric layer covers the first internal circuit layer and the third surface. The fourth dielectric layer covers the second internal circuit layer and the fourth surface. The first outer circuit layer is configured on the third dielectric layer. The second outer circuit layer is configured on the fourth dielectric layer. The conductive via penetrates through the third dielectric layer, the second dielectric layer and the fourth dielectric layer, and electrically connects the first outer circuit layer and the second outer circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive via hole and electrically connects the first outer circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive via hole and electrically connects the second outer circuit layer and the second inner circuit layer.

The circuit board structure of the present invention includes a first base, a second base, a third dielectric layer, a fourth dielectric layer, a first annular retaining wall and a second annular retaining wall. The first substrate includes a first dielectric layer, a first outer circuit layer, a first conductive via and a first inner circuit layer. The first outer circuit layer and the first inner circuit layer are respectively located on opposite sides of the first dielectric layer. The first conductive via penetrates the first dielectric layer and electrically connects the first outer circuit layer and the first inner circuit layer. The second substrate includes a second dielectric layer, a second outer circuit layer, a second conductive via and a second inner circuit layer. The second outer circuit layer and the second inner circuit layer are respectively located on opposite sides of the second dielectric layer. The second conductive via penetrates through the second dielectric layer and electrically connects the second outer circuit layer and the second inner circuit layer. The third dielectric layer covers the first internal circuit layer. The fourth dielectric layer covers the second inner circuit layer. The first annular retaining wall is disposed in the third dielectric layer and electrically connected to the first inner circuit layer. An orthographic projection of the first annular retaining wall on the first base surrounds the first conductive via. The second annular retaining wall is disposed in the fourth dielectric layer and electrically connected to the second inner circuit layer. The orthographic projection of the second annular retaining wall on the second base surrounds the second conductive via. The third dielectric layer is connected to the fourth dielectric layer, and part of the first ring-shaped retaining wall is connected to part of the second ring-shaped retaining wall, so that the first base is connected to the second base.

Based on the above, in the design of the circuit board structure of the present invention, the ring-shaped retaining wall surrounds the conductive through hole, wherein the ring-shaped retaining wall is a closed boundary structure, which can reduce electromagnetic interference (EMI) and completely cover Signal via conductive vias. Compared with the single row of blind holes with gaps around the conductive vias in the prior art, the circuit board structure of the present invention can effectively prevent energy loss and reduce noise interference, and has better signal integrity.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

FIG. 1A is a schematic top view of a circuit board structure according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view along line I-I of FIG. 1A . FIG. 1C is a schematic cross-sectional view along line II-II of FIG. 1A . FIG. 1D is a schematic cross-sectional view along line III-III of FIG. 1A . Please refer to FIG. 1A, FIG. 1B, FIG. 1C and FIG. 1D at the same time. In this embodiment, the circuit board structure 100 includes a base 110, a third dielectric layer 120, a fourth dielectric layer 130, a first outer The circuit layer 140 , a second outer circuit layer 150 , a conductive via 160 , a first annular retaining wall 170 and a second annular retaining wall 180 .

In detail, in this embodiment, the substrate 110 has an opening H, and includes a first dielectric layer 111, a second dielectric layer 113, a first internal circuit layer 115, a second internal circuit layer 117 and a conductive connection layer 119 . The opening H penetrates the first dielectric layer 111 , and the first dielectric layer 111 has a first surface S1 and a second surface S2 opposite to each other. The first internal circuit layer 115 is disposed on the first surface S1 of the first dielectric layer 111 , and the second internal circuit layer 117 is disposed on the second surface S2 of the first dielectric layer 111 . The conductive connection layer 119 covers the inner wall of the opening H and connects the first internal circuit layer 115 and the second internal circuit layer 117 . The second dielectric layer 113 fills the opening H, and the second dielectric layer 113 has a third surface S3 and a fourth surface S4 opposite to each other, wherein the third surface S3 and the fourth surface S4 are respectively aligned with the first interior. The wiring layer 115 and the second inner wiring layer 117 . Here, the first dielectric layer 111 can use general dielectric materials, wherein the dielectric constant of the first dielectric layer 111 can be lower than 4.0, and the dielectric loss (Df) of the first dielectric layer 111 can be lower than 0.01 , thereby providing proper impedance matching. The dielectric constant of the second dielectric layer 113 can be lower than 5.0, and the dielectric loss (Df) of the second dielectric layer 113 is greater than 0 and less than 0.025, so as to provide proper insulation and impedance matching, and can also reduce Dielectric loss.

Furthermore, the third dielectric layer 120 of this embodiment covers the third surface S3 of the first inner wiring layer 115 and the second dielectric layer 113 . The fourth dielectric layer 130 covers the second inner wiring layer 117 and the fourth surface S4 of the second dielectric layer 113 . The first outer circuit layer 140 is disposed on the third dielectric layer 120 , and the second outer circuit layer 150 is disposed on the fourth dielectric layer 130 . The conductive via 160 penetrates through the third dielectric layer 120 , the second dielectric layer 113 and the fourth dielectric layer 130 , and electrically connects the first outer circuit layer 140 and the second outer circuit layer 150 . The conductive via 160 includes a through hole 162 , a conductive material layer 164 and a hole-filling material 166 . The through hole 162 penetrates through the third dielectric layer 120 , the second dielectric layer 113 and the fourth dielectric layer 130 . The conductive material layer 164 covers the inner wall of the through hole 162 and electrically connects the first outer circuit layer 140 and the second outer circuit layer 150 . The hole filling material 166 fills the through hole 162 , and the first outer circuit layer 140 and the second outer circuit layer 150 respectively cover an upper surface 167 and a lower surface 169 of the hole filling material 166 opposite to each other. Here, the first external circuit layer 140 and the second external circuit layer 150 are multilayer structural layers, which are respectively composed of a copper foil layer C1, a copper plating layer C2 and a cover layer C3, wherein the copper plating layer C2 is located on the copper foil layer Between C1 and the cover layer C3, the copper plating layer C2 and the conductive material layer 164 belong to the same film layer. The cover layer C3 is, for example, a copper layer, but not limited thereto, and covers the upper surface 167 and the lower surface 169 of the hole-filling material 166 .

In particular, in this embodiment, the first ring-shaped retaining wall 170 is embedded in the third dielectric layer 120 , surrounds the conductive via 160 and is electrically connected to the first outer circuit layer 140 and the first inner circuit layer 115 . The second annular retaining wall 180 is embedded in the fourth dielectric layer 130 , surrounds the conductive via 160 and is electrically connected to the second outer circuit layer 150 and the second inner circuit layer 117 . The first outer circuit layer 140 , the conductive via 160 and the second outer circuit layer 150 define a signal path L1 . The first outer circuit layer 150, the first annular retaining wall 170, the first inner circuit layer 115, the connection circuit layer 119, the second inner circuit layer 117, the second annular retaining wall 180 and the second outer circuit layer 150 define A ground path L2, and the ground path L2 surrounds the signal path L1.

More specifically, please refer to FIG. 1B , the first external circuit layer 140 includes a first signal circuit 142 and a first ground circuit 144 . The second outer circuit layer 150 includes a second signal circuit 152 and a second ground circuit 154 . The first signal line 142 , the conductive via 160 and the second signal line 152 define a signal path L1 . The first ground circuit 144, the first annular retaining wall 170, the first inner circuit layer 115, the conductive connection layer 119, the second inner circuit layer 117, the second annular retaining wall 180 and the second ground circuit 154 define a ground path L2. Since the signal path L1 is surrounded by the ground path L2 in a closed manner, a good high-frequency and high-speed loop can be formed.

In addition, please refer to FIG. 1C and FIG. 1D , the first signal line 142 is surrounded by the first ring-shaped retaining wall 170 and the ground path L3 defined by the first inner circuit layer 115 and is enclosed in a closed manner, while the second signal line 152 The ground path L4 defined by the second ring-shaped retaining wall 180 and the second inner circuit layer 117 is surrounded and closed, so a good high-frequency and high-speed loop can be formed.

In terms of manufacturing process, if the third dielectric layer 120 and the fourth dielectric layer 130 are photoimageable dielectric (photoimageable dielectric, PID) materials, they can be dry-film laminated (Dry-Film Lamination) to the substrate 110 first. Closed trenches with a width of eg 100 microns and a diameter of eg 600 microns are respectively formed on the third dielectric layer 120 and the fourth dielectric layer 130 on opposite sides through a photolithography process. Alternatively, if the third dielectric layer 120 and the fourth dielectric layer 130 are, for example, pre-preg or Ajinomoto Build-up Film (ABF), they can be ablated by laser Closed trenches with a width of, for example, 100 micrometers and a diameter of, for example, 600 micrometers are respectively formed on the third dielectric layer 120 and the fourth dielectric layer 130 in a manner. Next, apply conductive metal glue (such as conductive copper paste) in the groove by Transient Liquid Phase Sintering (TLPS) and air-dry, which can have the effect of conducting electricity and heat, and is suitable for any metal material Bonding is performed, and the heat will not change back to the liquid state, and the production of the first annular retaining wall 170 and the second annular retaining wall 180 is completed.

It should be noted that, in this embodiment, the first annular retaining wall 170 and the second annular retaining wall 180 are formed by filling the third dielectric layer 120 and the fourth dielectric layer 130 with conductive paste. , so the first annular retaining wall 170 and the second annular retaining wall 180 are solid retaining wall structures respectively, but not limited thereto, the conductive material of the annular retaining wall can also be metal plating or electroless metal plating layer. In another unillustrated embodiment, the first annular retaining wall and the second annular retaining wall can also be coated with a metal electroplating layer or an electroless metal plating layer in the third dielectric layer and the fourth dielectric layer. , or metal conductive paste, so the first annular retaining wall and the second annular retaining wall can be groove-shaped retaining wall structures, which still belong to the scope of protection of the present invention.

In short, in this embodiment, the signal path L1 defined by the first signal line 142, the conductive via 160 and the second signal line 152 is formed by the first ground line 144, the first annular retaining wall 170, the first internal line The ground path L2 defined by the layer 115 , the conductive connection layer 119 , the second inner circuit layer 117 , the second ring-shaped retaining wall 180 and the second ground circuit 154 surrounds it. That is to say, a well-closed grounding path L2 is provided around the signal path L1 capable of transmitting high-frequency and high-speed signals such as 5G, thereby forming a good high-frequency and high-speed loop, so that the circuit board structure 100 of this embodiment can have a higher Good signal integrity. Here, the high frequency refers to a frequency greater than 1 GHz; and the high speed refers to a data transmission speed greater than 100 Mbps. Furthermore, since the first ring-shaped retaining wall 170 and the second ring-shaped retaining wall 180 are a closed boundary closed structure, they can completely cover the signal of the conductive via 160 . Compared with the single row of blind holes with gaps around the conductive vias in the prior art, the circuit board structure 100 of this embodiment can effectively prevent energy loss and reduce noise interference, and can have better signal integrity sex. In addition, the conductive via 160 , the conductive connection layer 119 and the second dielectric layer 113 define a coaxial via, wherein the second dielectric layer 113 is located between the conductive via 160 and the conductive connection layer 119 . Compared with the build-up method of pressing the insulating layer in the prior art to block the inner conductor layer and the outer conductor layer of the coaxial perforation, the manufacturing method of the circuit board structure 100 of this embodiment can avoid impedance mismatch and affect Integrity of high-frequency signals.

FIG. 2A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. FIG. 2B is another partial cross-sectional schematic diagram of the circuit board structure of FIG. 2A . FIG. 2C is a partial perspective view of the circuit board structure in FIG. 2A . FIG. 2D is a schematic partial cross-sectional view of an electronic device including the circuit board structure of FIG. 2A . 3A is a schematic top view of the first substrate, the third dielectric layer and the first ring-shaped retaining wall of the circuit board structure in FIG. 2A . FIG. 3B is a schematic cross-sectional view along line A-A of FIG. 3A , that is, a schematic cross-sectional view at position P1. FIG. 3C is a schematic cross-sectional view along line B-B in FIG. 3A , that is, a schematic cross-sectional view at position P2. FIG. 3D is a schematic cross-sectional view along line C-C of FIG. 3A , that is, a schematic cross-sectional view at position P3. 4A is a schematic top view illustrating the second base, the fourth dielectric layer and the second ring-shaped retaining wall of the circuit board structure of FIG. 2A . FIG. 4B is a schematic cross-sectional view along line A-A of FIG. 4A , that is, a schematic cross-sectional view at position P1. FIG. 4C is a schematic cross-sectional view along line B-B in FIG. 4A , that is, a schematic cross-sectional view at position P2. FIG. 4D is a schematic cross-sectional view along line C-C of FIG. 4A , that is, a schematic cross-sectional view at position P3. It should be noted that FIG. 2A is a schematic cross-sectional view along the line E-E in FIG. 3A and FIG. sectional schematic diagram.

First, please refer to FIG. 2A, FIG. 2C, FIG. 3A and FIG. 4A. In this embodiment, the circuit board structure 200 includes a first base 210, a second base 220, a third dielectric layer 230, a first Four dielectric layers 240 , a first annular retaining wall 250 and a second annular retaining wall 260 .

In detail, please refer to FIG. 2A, FIG. 3A, FIG. 3B, FIG. 3C and FIG. 3D. The first conductive via 216 and a first inner circuit layer 218 . The first outer circuit layer 214 and the first inner circuit layer 218 are respectively located on opposite sides of the first dielectric layer 212 . The first conductive via hole 216 penetrates the first dielectric layer 212 and electrically connects the first outer circuit layer 214 and the first inner circuit layer 218 . Here, as shown in FIG. 3B , the first conductive via hole 216 of this embodiment includes a first through hole T1 , a first conductive material layer M1 and a first hole-filling material F1 . The first through hole T1 penetrates the first dielectric layer 212 , and the first conductive material layer M1 covers the inner wall of the first through hole T1 and electrically connects the first outer circuit layer 214 and the first inner circuit layer 218 . The first hole filling material F1 fills the first through hole T1, and the first inner wiring layer 218 and the first outer wiring layer 214 respectively cover a first upper surface F11 and a first lower surface of the first hole filling material F1 opposite to each other. Surface F12. The third dielectric layer 230 covers the first inner circuit layer 218 of the first substrate 210 . The first annular retaining wall 250 is embedded in the third dielectric layer 230 and is electrically connected to the first internal circuit layer 218, wherein the orthographic projection of the first annular retaining wall 250 on the first base 210 surrounds the first conductive channel. Hole 216.

Further, please refer to FIG. 3A , FIG. 3B and FIG. 3D at the same time, the circuit board structure 200 a of this embodiment further includes a first joint portion 270 and a second joint portion 275 . The first joint portion 270 and the second joint portion 275 are disposed on the first inner circuit layer 218, and the first annular retaining wall 250 surrounds the first joint portion 270 and the second joint portion 275, wherein the first joint portion 270 corresponds to the second joint portion. A conductive via 216 is provided. Furthermore, the first internal circuit layer 218 in this embodiment includes a first signal circuit 218a and a first ground circuit 218b. The first annular retaining wall 250 is disposed on the first ground line 218b, and the first joint portion 270 and the second joint portion 275 are disposed on the first signal line 218a.

In terms of manufacturing process, the first joint portion 270 and the second joint portion 275 are formed simultaneously with the first annular retaining wall 250 . In detail, if the third dielectric layer 230 is, for example, a photoimageable dielectric (PID) material, it can be dry-film laminated (Dry-Film Lamination) on opposite sides of the first substrate 210 first, And a closed trench and an opening are formed on the third dielectric layer 230 through a photolithography process. Alternatively, if the third dielectric layer 230 is, for example, pre-preg or Ajinomoto Build-up Film (ABF), the third dielectric layer 230 can be laser ablated. Closed trenches and openings are formed in layer 230 . Next, apply conductive metal glue (such as conductive copper paste) in the closed groove and opening by Transient Liquid Phase Sintering (TLPS) and air-dry, which can have the effect of conducting electricity and heat, and is suitable for Join with any metal material, and will not turn back to the liquid state due to heat, so as to complete the first annular retaining wall 250 formed in the closed trench and the first joint part 270 and the second joint part formed in the opening 275 made. Here, the width of the first joint portion 270 and the width of the second joint portion 275 are respectively greater than the width of the first annular retaining wall 250 .

Next, please refer to FIG. 2A, FIG. 4A, FIG. 4B, FIG. 4C and FIG. 4D. In this embodiment, the second substrate 220 includes a second dielectric layer 222, a second external circuit layer 224, a second conductive The via hole 226 and a second inner circuit layer 228 . The second outer circuit layer 224 and the second inner circuit layer 228 are respectively located on opposite sides of the second dielectric layer 222 . The second conductive via 226 penetrates through the second dielectric layer 222 and electrically connects the second outer circuit layer 224 and the second inner circuit layer 228 . As shown in FIG. 4B, the second conductive via hole 226 of this embodiment includes a second through hole T2, a second conductive material layer M2, and a second hole-filling material F2. The second through hole T2 penetrates the second dielectric layer 222 , and the second conductive material layer M2 covers the inner wall of the second through hole T2 and electrically connects the second outer circuit layer 224 and the second inner circuit layer 228 . The second hole filling material F2 fills the second through hole T2, and the second inner circuit layer 228 and the second outer circuit layer 224 respectively cover a second upper surface F21 and a second lower surface of the second hole filling material F2 opposite to each other. Surface F22. The fourth dielectric layer 240 covers the second inner circuit layer 228 of the second substrate 220 . The second ring-shaped retaining wall 260 is embedded in the fourth dielectric layer 240 and electrically connected to the second inner circuit layer 228, wherein the orthographic projection of the second ring-shaped retaining wall 260 on the second substrate 220 surrounds the second conductive channel. Hole 226.

Further, please refer to FIG. 4A , FIG. 4B and FIG. 4D at the same time, the circuit board structure 200 a of this embodiment further includes a third joint portion 280 and a fourth joint portion 285 . The third joint portion 280 and the fourth joint portion 285 are disposed on the second inner circuit layer 228, and the second annular retaining wall 260 surrounds the third joint portion 280 and the fourth joint portion 285, wherein the third joint portion 280 corresponds to the second joint portion 280. Two conductive vias 226 are provided. Furthermore, the second internal circuit layer 228 in this embodiment includes a second signal circuit 228a and a second ground circuit 228b. The second ring-shaped retaining wall 260 is disposed on the second ground line 228b, and the third joint portion 280 and the fourth joint portion 285 are disposed on the second signal line 228a.

In terms of manufacturing process, the third joint portion 280 and the fourth joint portion 285 are formed simultaneously with the second annular retaining wall 260 . In detail, if the fourth dielectric layer 240 is, for example, a photoimageable dielectric (PID) material, it can be dry-film laminated (Dry-Film Lamination) on opposite sides of the second substrate 220 first, And a closed trench and an opening are formed on the fourth dielectric layer 240 through a photolithography process. Alternatively, if the fourth dielectric layer 240 is, for example, pre-preg or Ajinomoto Build-up Film (ABF), the fourth dielectric layer can be laser ablated. Closed trenches and openings are formed in layer 240 . Next, apply conductive metal glue (such as conductive copper paste) in the closed groove and opening by Transient Liquid Phase Sintering (TLPS) and air-dry, which can have the effect of conducting electricity and heat, and is suitable for Join with any metal material, and will not turn back to the liquid state due to heat, and complete the second annular retaining wall 260 formed in the closed trench and the third joint part 280 and the fourth joint part formed in the opening 285 made. Here, the width of the third joint portion 280 and the width of the fourth joint portion 285 are respectively greater than the width of the second annular retaining wall 260 .

Next, please refer to FIG. 2A, FIG. 2B and FIG. 2C at the same time, the third dielectric layer 230 is connected to the fourth dielectric layer 240, and part of the first annular retaining wall 250 is connected to part of the second annular retaining wall 260, so that the first annular retaining wall 260 is connected. A base 210 is docked on the second base 220 . At this time, the first bonding portion 270 is bonded to the third bonding portion 280 , and the first conductive via 216 overlaps the second conductive via 226 , the first bonding portion 270 and the third bonding portion 280 . The second grounding line 228b, the second annular retaining wall 260, the first annular retaining wall 250 and the first grounding line 218b define a grounding path L5, and the grounding path L5 surrounds the first joint portion 270 and the third joint portion 280 . That is to say, in this embodiment, the high-frequency and high-speed signals are arranged on the inner layer (namely, the first signal line 218a and the second signal line 228a), and a well-closed grounding path L5 is set around it, thereby forming a good The high-frequency and high-speed loop makes the circuit board structure 200a of this embodiment have better signal integrity.

In addition, please refer to FIG. 2D. In this embodiment, the electronic device 10 includes the above-mentioned circuit board structure 200a and the electronic component 20 such as FIG. pad 22. In addition, the electronic device 10 of this embodiment further includes a plurality of connectors 30 disposed between the first external circuit layer 214 of the first substrate 210 of the circuit board structure 200a and the pads 22 of the electronic component 20, wherein the electronic component 20 It is electrically connected to the circuit board structure 200a through the connecting member 30 . Here, the connecting element 30 is, for example, a solder ball, but not limited thereto. In application, an antenna structure may be disposed on the other side of the circuit board structure 200 a relative to the electronic component 20 , and the antenna structure is electrically connected to the first outer circuit layer 224 of the second substrate 220 of the circuit board structure 200 a. In the application of integrated circuits and antennas, the circuit board structure 200a of this embodiment can solve the problem of signal interference on the same plane, reduce signal energy loss and noise interference, and further improve the reliability of signal transmission.

FIG. 5A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. FIG. 5B is another partial cross-sectional schematic diagram of the circuit board structure of FIG. 5A . Please refer to FIG. 2A, FIG. 2B, FIG. 5A and FIG. 5B at the same time. The circuit board structure 200b of this embodiment is similar to the above-mentioned circuit board structure 200a. to the second substrate 220 at position P3. When the first base 210 is docked on the second base 220 , the first joint part 270 is jointed to the fourth joint part 285 , and part of the first annular retaining wall 250 is jointed to part of the second annular retaining wall 260 . At this time, the first conductive via 216 does not overlap the second conductive via 226, and the first conductive via 216 overlaps the first bonding portion 270 and the fourth bonding portion 285, thereby forming a fan-out (fan-out) The circuit board structure 200b is convenient for subsequent diversified applications.

FIG. 6A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. FIG. 6B is another partial cross-sectional schematic diagram of the circuit board structure of FIG. 6A . Please refer to FIG. 2A, FIG. 2B, FIG. 6A and FIG. 6B at the same time. The circuit board structure 200c of this embodiment is similar to the above-mentioned circuit board structure 200a. The difference between the two is that the first base 210 at position P3 is docked in this embodiment. to the second substrate 220 at position P1. When the first base 210 is docked to the second base 220 , the second joint portion 275 is jointed to the third joint portion 280 , and part of the first annular retaining wall 250 is jointed to part of the second annular retaining wall 260 . At this time, the first conductive via 216 does not overlap the second conductive via 226, and the second conductive via 226 overlaps the third bonding portion 280 and the second bonding portion 275, thereby forming a fan-out (fan-out) The circuit board structure 200c is convenient for subsequent diversified applications.

FIG. 7A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. FIG. 7B is another partial cross-sectional schematic diagram of the circuit board structure of FIG. 7A . Please refer to FIG. 2A, FIG. 2B, FIG. 7A and FIG. 7B at the same time. The circuit board structure 200d of this embodiment is similar to the above-mentioned circuit board structure 200a. The difference between the two is that the first base 210 at position P3 is docked in this embodiment. to the second substrate 220 at position P3. When the first base 210 is docked to the second base 220 , the second joint portion 275 is jointed to the fourth joint portion 285 , and part of the first annular retaining wall 250 is jointed to part of the second annular retaining wall 260 . At this time, the first conductive via 216 does not overlap the second conductive via 226 , the second joint portion 275 and the fourth joint portion 285 , thereby forming a fan-out circuit board structure 200d, which is convenient for subsequent of diverse applications.

To sum up, in the design of the circuit board structure of the present invention, the ring-shaped retaining wall surrounds the conductive through hole, wherein the ring-shaped retaining wall is a closed boundary structure, which can reduce electromagnetic interference (EMI) and Signals that fully cover conductive vias. Compared with the single row of blind holes with gaps around the conductive vias in the prior art, the circuit board structure of the present invention can effectively prevent energy loss and reduce noise interference, and has better signal integrity.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: Electronic device 20: Electronic components 22: Pad 30: connector 100, 200a, 200b, 200c, 200d: circuit board structure 110: base 111, 212: the first dielectric layer 113, 222: second dielectric layer 115, 218: the first internal circuit layer 117, 228: the second internal circuit layer 119: Conductive connection layer 120, 230: the third dielectric layer 130, 240: the fourth dielectric layer 140, 214: the first external line layer 142, 218a: the first signal line 144, 218b: the first grounding line 150, 224: second external line layer 152, 228a: the second signal line 154, 228b: the second grounding line 160: Conductive vias 162: through hole 164: conductive material layer 166: hole filling material 167: upper surface 169: lower surface 170, 250: the first ring retaining wall 180, 260: the second ring retaining wall 210: First base 220:Second Base 216: the first conductive via 226: second conductive via 270: the first junction 275: second junction 280: The third junction 285: The fourth junction C1: copper foil layer C2: copper plating layer C3: cover layer F1: The first filling material F11: first upper surface F12: first lower surface F2: The second hole filling material F21: second upper surface F22: second lower surface H: open L1: signal path L2, L3, L4, L5: Ground paths M1: first conductive material layer M2: second conductive material layer P1, P2, P3: position S1: first surface S2: second surface S3: third surface S4: fourth surface T1: the first through hole T2: Second through hole

FIG. 1A is a schematic top view of a circuit board structure according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view along line I-I of FIG. 1A . FIG. 1C is a schematic cross-sectional view along line II-II of FIG. 1A . FIG. 1D is a schematic cross-sectional view along line III-III of FIG. 1A . FIG. 2A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. FIG. 2B is another partial cross-sectional schematic diagram of the circuit board structure of FIG. 2A . FIG. 2C is a partial perspective view of the circuit board structure in FIG. 2A . FIG. 2D is a schematic partial cross-sectional view of an electronic device including the circuit board structure of FIG. 2A . 3A is a schematic top view of the first substrate, the third dielectric layer and the first ring-shaped retaining wall of the circuit board structure in FIG. 2A . Fig. 3B is a schematic cross-sectional view along line A-A of Fig. 3A. FIG. 3C is a schematic cross-sectional view along line B-B of FIG. 3A . FIG. 3D is a schematic cross-sectional view along line C-C of FIG. 3A . 4A is a schematic top view illustrating the second base, the fourth dielectric layer and the second ring-shaped retaining wall of the circuit board structure of FIG. 2A . FIG. 4B is a schematic cross-sectional view along line A-A of FIG. 4A. FIG. 4C is a schematic cross-sectional view along line B-B of FIG. 4A . FIG. 4D is a schematic cross-sectional view along line C-C of FIG. 4A. FIG. 5A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. FIG. 5B is another partial cross-sectional schematic diagram of the circuit board structure of FIG. 5A . FIG. 6A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. FIG. 6B is another partial cross-sectional schematic diagram of the circuit board structure of FIG. 6A . FIG. 7A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. FIG. 7B is another partial cross-sectional schematic diagram of the circuit board structure of FIG. 7A .

110: base

111: the first dielectric layer

113: second dielectric layer

115: The first internal circuit layer

117: The second internal circuit layer

119: Conductive connection layer

120: the third dielectric layer

130: the fourth dielectric layer

140: the first external line layer

142: The first signal line

144: The first grounding line

150: second external line layer

152: Second signal line

154: Second grounding line

160: Conductive vias

162: through hole

164: conductive material layer

166: hole filling material

167: upper surface

169: lower surface

170: The first ring retaining wall

180: Second ring retaining wall

C1: copper foil layer

C2: copper plating layer

C3: cover layer

H: open

L1: signal path

L2: Ground path

S1: first surface

S2: second surface

S3: third surface

S4: fourth surface

Claims (11)

A circuit board structure comprising: A substrate has an opening, and includes a first dielectric layer, a second dielectric layer, a first internal circuit layer, a second internal circuit layer and a conductive connection layer, wherein the opening penetrates the first dielectric layer An electrical layer, the first dielectric layer has a first surface and a second surface opposite to each other, the first internal circuit layer is disposed on the first surface, and the second internal circuit layer is disposed on the second surface , the conductive connection layer covers the inner wall of the opening and connects the first internal circuit layer and the second internal circuit layer, and the second dielectric layer fills the opening, and the second dielectric layers have opposite a third surface and a fourth surface of; a third dielectric layer covering the first inner circuit layer and the third surface; a fourth dielectric layer covering the second inner circuit layer and the fourth surface; a first outer circuit layer configured on the third dielectric layer; a second outer circuit layer configured on the fourth dielectric layer; a conductive via hole, passing through the third dielectric layer, the second dielectric layer and the fourth dielectric layer, and electrically connecting the first outer circuit layer and the second outer circuit layer; a first annular retaining wall disposed in the third dielectric layer, surrounding the conductive via and electrically connecting the first outer circuit layer and the first inner circuit layer; and A second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive via hole and electrically connects the second outer circuit layer and the second inner circuit layer. The circuit board structure as described in claim 1, wherein the first outer circuit layer, the conductive via and the second outer circuit layer define a signal path, and the first outer circuit layer, the first annular A grounding path is defined by the retaining wall, the first internal circuit layer, the conductive connection layer, the second internal circuit layer, the second ring-shaped retaining wall and the second external circuit layer, and the grounding path surrounds the signal path . The circuit board structure as claimed in item 2, wherein the first external circuit layer includes a first signal circuit and a first ground circuit, and the second external circuit layer includes a second signal circuit and a second ground circuit , the first signal line, the conductive via hole and the second signal line define the signal path, the first ground line, the first annular retaining wall, the first inner line layer, the conductive connection layer, the The second inner circuit layer, the second ring-shaped retaining wall and the second ground circuit define the ground path. The circuit board structure according to claim 1, wherein the conductive via includes a through hole, a conductive material layer and a hole filling material, and the through hole penetrates the third dielectric layer, the second dielectric layer and the first dielectric layer Four dielectric layers, and the conductive material layer covers the inner wall of the through hole and electrically connects the first outer circuit layer and the second outer circuit layer, the hole filling material fills the through hole, and the first outer circuit layer The circuit layer and the second outer circuit layer respectively cover an upper surface and a lower surface of the hole-filling material opposite to each other. A circuit board structure comprising: A first substrate, including a first dielectric layer, a first outer circuit layer, a first conductive via and a first inner circuit layer, wherein the first outer circuit layer and the first inner circuit layer are respectively located On opposite sides of the first dielectric layer, the first conductive via penetrates through the first dielectric layer and electrically connects the first outer circuit layer and the first inner circuit layer; A second substrate, including a second dielectric layer, a second outer circuit layer, a second conductive via and a second inner circuit layer, wherein the second outer circuit layer and the second inner circuit layer are respectively located On opposite sides of the second dielectric layer, the second conductive via penetrates through the second dielectric layer and electrically connects the second outer circuit layer and the second inner circuit layer; a third dielectric layer covering the first internal circuit layer; a fourth dielectric layer covering the second internal circuit layer; A first annular retaining wall, disposed in the third dielectric layer and electrically connected to the first internal circuit layer, wherein the orthographic projection of the first annular retaining wall on the first base surrounds the first conductive through holes; and A second annular retaining wall is disposed in the fourth dielectric layer and electrically connected to the second internal circuit layer, wherein the orthographic projection of the second annular retaining wall on the second base surrounds the second conductive Through holes, the third dielectric layer is connected to the fourth dielectric layer, and part of the first ring-shaped retaining wall is connected to part of the second ring-shaped retaining wall, so that the first substrate is abutted on the second substrate. The circuit board structure as described in claim item 5 further includes: A first joint portion and a second joint portion are arranged on the first internal circuit layer, and the first annular retaining wall surrounds the first joint portion and the second joint portion, wherein the first joint portion is Should the first conductive via be provided; and A third joint portion and a fourth joint portion are disposed on the second internal circuit layer, and the second annular retaining wall surrounds the third joint portion and the fourth joint portion, wherein the third joint portion is The second conductive via should be set; Wherein the first internal circuit layer includes a first signal circuit and a first ground circuit, the first ring-shaped retaining wall is arranged on the first ground circuit, and the first joint part and the second joint part are arranged on on the first signal line, and the second inner line layer includes a second signal line and a second ground line, the second ring-shaped retaining wall is arranged on the second ground line, and the third junction part and The fourth joint part is configured on the second signal line. The circuit board structure as claimed in item 6, wherein when the first base is docked to the second base, the first joint part is jointed to the third joint part, and part of the first annular retaining wall is jointed to part of the The second annular retaining wall, the first conductive via overlaps the second conductive via, the first junction and the third junction, and the first grounding line, the first annular retaining wall, the second The two ring-shaped retaining walls and the second ground circuit define a ground path, and the ground path surrounds the first joint portion and the third joint portion. The circuit board structure according to claim 6, wherein when the first base is docked to the second base, the first joint part is jointed to the fourth joint part, and part of the first ring-shaped retaining wall is jointed to part of the In the second annular retaining wall, the first conductive via hole does not overlap the second conductive via hole, and the first conductive via hole overlaps the first joint portion and the fourth joint portion. The circuit board structure according to claim 6, wherein when the first base is docked to the second base, the second joint part is jointed to the third joint part, and part of the first ring-shaped retaining wall is jointed to part of the In the second ring-shaped retaining wall, the first conductive via does not overlap the second conductive via, and the second conductive via overlaps the third joint portion and the second joint portion. The circuit board structure as claimed in item 6, wherein when the first base is docked to the second base, the second joint part is jointed to the fourth joint part, and part of the first annular retaining wall is jointed to part of the In the second ring-shaped retaining wall, the first conductive via hole does not overlap the second conductive via hole, the second joint portion, and the fourth joint portion. Circuit board structure as described in claim item 5, wherein The first conductive via hole includes a first through hole, a first conductive material layer and a first hole filling material, the first through hole penetrates the first dielectric layer, and the first conductive material layer covers the first conductive material layer The inner wall of a through hole is electrically connected to the first outer circuit layer and the first inner circuit layer, the first hole filling material fills the first through hole, and the first inner circuit layer and the first outer circuit layer The wiring layer respectively covers a first upper surface and a first lower surface of the first hole-filling material opposite to each other; and The second conductive via hole includes a second through hole, a second conductive material layer and a second hole filling material, the second through hole penetrates the second dielectric layer, and the second conductive material layer covers the first The inner walls of the two through holes are electrically connected to the second outer circuit layer and the second inner circuit layer, the second hole filling material fills the second through hole, and the second inner circuit layer and the second outer circuit layer The circuit layer respectively covers a second upper surface and a second lower surface of the second hole-filling material opposite to each other.

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