CN116133230A - Circuit board structure - Google Patents
Circuit board structure Download PDFInfo
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- CN116133230A CN116133230A CN202210751138.XA CN202210751138A CN116133230A CN 116133230 A CN116133230 A CN 116133230A CN 202210751138 A CN202210751138 A CN 202210751138A CN 116133230 A CN116133230 A CN 116133230A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
- H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Diaphragms For Electromechanical Transducers (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a circuit board structure, which comprises a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall and a second annular retaining wall. The conductive via is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall surrounds the conductive through hole and is electrically connected with the first external circuit layer and the first internal circuit layer. The second annular retaining wall surrounds the conductive through hole and is electrically connected with the second external circuit layer and the second internal circuit layer. The first grounding circuit, the first annular retaining wall and the first inner circuit layer define a first grounding path surrounding the first signal circuit. The second grounding circuit, the second annular retaining wall and the second inner circuit layer define a second grounding path surrounding the second signal circuit. The circuit board structure can effectively prevent energy loss and reduce noise interference, and has better signal integrity.
Description
Technical Field
The present disclosure relates to circuit board structures, and particularly to a circuit board structure.
Background
In the conventional circuit board, one or more insulating layers are required between the inner conductor layer and the outer conductor layer for blocking, wherein the insulating layers are formed by laminating and adding layers. Thus, there is an impedance mismatch across the coaxial via and an electromagnetic interference (electromagnetic interference, EMI) shielding notch can occur, thereby affecting high frequency signal integrity.
Disclosure of Invention
The invention is directed to a circuit board structure that can effectively prevent energy loss and reduce noise interference, and that can have better signal integrity.
According to an embodiment of the invention, the circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive via, a first annular retaining wall, and a second annular retaining wall. The substrate is provided with an opening and comprises a first dielectric layer, a second dielectric layer, a first inner circuit layer, a second inner circuit layer and a conductive connection layer. The opening penetrates through the first dielectric layer, and the first dielectric layer is provided with a first surface and a second surface which are opposite to each other. The first inner circuit layer is configured on the first surface, and the second inner circuit layer is configured on the second surface. The conductive connection layer covers the inner wall of the opening and connects the first inner circuit layer and the second inner circuit layer. The second dielectric layer fills the opening, and has a third surface and a fourth surface opposite to each other. The third dielectric layer covers the first inner circuit layer and the third surface. The fourth dielectric layer covers the second inner circuit layer and the fourth surface. The first external circuit layer is arranged on the third dielectric layer and comprises a first signal circuit and a first grounding circuit. The second external circuit layer is disposed on the fourth dielectric layer and includes a second signal circuit and a second ground circuit. The conductive via penetrates through the third dielectric layer, the second dielectric layer and the fourth dielectric layer and is electrically connected with the first external circuit layer and the second external circuit layer. The first annular retaining wall is arranged in the third dielectric layer, surrounds the conductive through hole and is electrically connected with the first external circuit layer and the first internal circuit layer. The first grounding circuit, the first annular retaining wall and the first inner circuit layer define a first grounding path, and the first grounding path surrounds the first signal circuit. The second annular retaining wall is arranged in the fourth dielectric layer, surrounds the conductive through hole and is electrically connected with the second external circuit layer and the second internal circuit layer. The second grounding circuit, the second annular retaining wall and the second inner circuit layer define a second grounding path, and the second grounding path surrounds the second signal circuit.
In the circuit board structure according to the embodiment of the invention, the first signal line, the conductive via and the second signal line define a signal path. The first grounding circuit, the first annular retaining wall, the first inner circuit layer, the conductive connecting layer, the second inner circuit layer, the second annular retaining wall and the second grounding circuit define a third grounding path, and the third grounding path surrounds the signal path.
In the circuit board structure according to the embodiment of the invention, the conductive via includes a through hole, a conductive material layer, and a hole filling material. The through hole penetrates through the third dielectric layer, the second dielectric layer and the fourth dielectric layer. The conductive material layer covers the inner wall of the through hole and is electrically connected with the first external circuit layer and the second external circuit layer. The hole filling material fills the through hole, and the first external circuit layer and the second external circuit layer respectively cover the upper surface and the lower surface of the hole filling material opposite to each other.
In the circuit board structure according to the embodiment of the invention, the first grounding path and the second grounding path are respectively U-shaped paths.
According to an embodiment of the invention, the circuit board structure comprises two circuit board units and a connection structure layer. Each circuit board unit comprises a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall and a second annular retaining wall. The substrate is provided with an opening and comprises a first dielectric layer, a second dielectric layer, a first inner circuit layer, a second inner circuit layer and a conductive connection layer. The opening penetrates through the first dielectric layer, and the first dielectric layer is provided with a first surface and a second surface which are opposite to each other. The first inner circuit layer is configured on the first surface, and the second inner circuit layer is configured on the second surface. The conductive connection layer covers the inner wall of the opening and connects the first inner circuit layer and the second inner circuit layer. The second dielectric layer fills the opening, and has a third surface and a fourth surface opposite to each other. The third dielectric layer covers the first inner circuit layer and the third surface. The fourth dielectric layer covers the second inner circuit layer and the fourth surface. The first external circuit layer is arranged on the third dielectric layer and comprises a first signal circuit and a first grounding circuit. The second external circuit layer is disposed on the fourth dielectric layer and includes a second signal circuit and a second ground circuit. The conductive via penetrates through the third dielectric layer, the second dielectric layer and the fourth dielectric layer and is electrically connected with the first external circuit layer and the second external circuit layer. The first annular retaining wall is arranged in the third dielectric layer, surrounds the conductive through hole and is electrically connected with the first external circuit layer and the first internal circuit layer. The first grounding circuit, the first annular retaining wall and the first inner circuit layer define a first grounding path, and the first grounding path surrounds the first signal circuit. The second annular retaining wall is arranged in the fourth dielectric layer, surrounds the conductive through hole and is electrically connected with the second external circuit layer and the second internal circuit layer. The second grounding circuit, the second annular retaining wall and the second inner circuit layer define a second grounding path, and the second grounding path surrounds the second signal circuit. The connecting structure layer is arranged between the circuit board units and electrically and structurally connected with the first external circuit layer of each circuit board structure so as to enable the circuit board units to be butted together. The first grounding path of each circuit board structure is connected through the connecting structure layer to define a third grounding path.
In the circuit board structure according to an embodiment of the invention, the connection structure layer includes a connection layer, a plurality of first conductive bonding portions, and a plurality of second conductive bonding portions. The second conductive joint part is arranged corresponding to the conductive through hole of each circuit board unit and is connected with the first signal line. The first conductive joint part surrounds the second conductive joint part and is connected with the first grounding circuit.
In the circuit board structure according to the embodiment of the invention, when the circuit board units are butted together, the second signal line, the conductive via, the first signal line, the second conductive joint, the first signal line, the conductive via and the second signal line of the other one of the circuit board units define a signal path. The second grounding circuit, the second annular retaining wall, the second inner circuit layer, the conductive connecting layer, the first inner circuit layer, the first annular retaining wall, the first grounding circuit, the first conductive joint part, the first grounding circuit of the other one of the circuit board units, the first annular retaining wall, the first inner circuit layer, the conductive connecting layer, the second inner circuit layer, the second annular retaining wall and the second grounding circuit define a fourth grounding path, and the fourth grounding path surrounds the signal path.
In the circuit board structure according to the embodiment of the invention, when the circuit board units are butted together, the first inner circuit layer, the first annular retaining wall, the first grounding circuit, the first conductive joint and the first grounding circuit, the first annular retaining wall and the first inner circuit layer of one of the circuit board units define a third grounding path. The third grounding path surrounds the first signal line of each circuit board unit.
In the circuit board structure according to the embodiment of the invention, the conductive via includes a through hole, a conductive material layer, and a hole filling material. The through hole penetrates through the third dielectric layer, the second dielectric layer and the fourth dielectric layer. The conductive material layer covers the inner wall of the through hole and is electrically connected with the first external circuit layer and the second external circuit layer. The hole filling material fills the through hole, and the first external circuit layer and the second external circuit layer respectively cover the upper surface and the lower surface of the hole filling material opposite to each other.
In the circuit board structure according to the embodiment of the invention, the first grounding path and the second grounding path are respectively U-shaped paths.
Based on the above, in the design of the circuit board structure of the present invention, the annular retaining wall surrounds the conductive via, wherein the annular retaining wall is a closed structure of a surface screen (closed boundary), which can reduce electromagnetic interference (EMI) and completely cover the signal of the conductive via. Compared with the prior art that the single row blind holes with gaps are arranged around the conductive through holes, the circuit board structure can effectively prevent energy loss and reduce noise interference, and has better signal integrity.
Drawings
FIG. 1A is a schematic top view of a circuit board structure according to an embodiment of the invention;
FIG. 1B is a schematic cross-sectional view along line I-I of FIG. 1A;
FIG. 1C is a schematic cross-sectional view along line II-II of FIG. 1A;
FIG. 1D is a schematic cross-sectional view along line III-III of FIG. 1A;
FIG. 1E is a partial perspective view of the circuit board structure of FIG. 1A in a second position;
FIG. 2A is a schematic cross-sectional view of a circuit board structure according to another embodiment of the invention docked in a first position;
FIG. 2B is a schematic cross-sectional view of the circuit board structure of FIG. 2A docked in a second position;
fig. 3 is a schematic partial cross-sectional view of an electronic device including the circuit board structure of fig. 2A.
Description of the reference numerals
10, an electronic device;
20, an electronic component;
22, a connecting pad;
30, connecting pieces;
100. 200, a circuit board structure;
110, a substrate;
111 a first dielectric layer;
113 a second dielectric layer;
115 a first internal wiring layer;
117 a second internal wiring layer;
119 a conductive connection layer;
120 a third dielectric layer;
130 a fourth dielectric layer;
a first external wiring layer 140;
142 a first signal line;
144 a first ground line;
150, a second external circuit layer;
a second signal line 152;
154, a second ground line;
160 conductive vias;
162, a through hole;
164 a layer of conductive material;
166, pore-filling material;
167, upper surface;
169 lower surface;
170, a first annular retaining wall;
180, a second annular retaining wall;
210 a connection layer;
220 a first conductive bond;
230 a second conductive bond;
c1, a copper foil layer;
c2, copper plating;
c3, covering layer;
CS, connecting the structural layer;
h, opening;
l1, L21 signal path;
l2, L3, L4, L22, L23, L24: a ground path;
p1, P2, P3.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1A is a schematic top view of a circuit board structure according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view along line I-I of FIG. 1A. FIG. 1C is a schematic cross-sectional view along line II-II of FIG. 1A. Fig. 1D is a schematic cross-sectional view along line III-III of fig. 1A. Fig. 1E is a partial perspective view of the circuit board structure of fig. 1A in a second position. It should be noted that fig. 1B is a schematic cross-sectional view of the circuit board structure at the first position P1, fig. 1C is a schematic cross-sectional view of the circuit board structure at the second position P2, and fig. 1D is a schematic cross-sectional view of the circuit board structure at the third position P3.
Referring to fig. 1A, fig. 1B, fig. 1C, and fig. 1D, in the present embodiment, the circuit board structure 100 includes a substrate 110, a third dielectric layer 120, a fourth dielectric layer 130, a first external circuit layer 140, a second external circuit layer 150, a conductive via 160, a first annular retaining wall 170, and a second annular retaining wall 180.
In detail, in the present embodiment, the substrate 110 has an opening H, and includes a first dielectric layer 111, a second dielectric layer 113, a first internal circuit layer 115, a second internal circuit layer 117, and a conductive connection layer 119. The opening H penetrates through the first dielectric layer 111, and the first dielectric layer 111 has a first surface S1 and a second surface S2 opposite to each other. The first internal circuit layer 115 is disposed on the first surface S1 of the first dielectric layer 111, and the second internal circuit layer 117 is disposed on the second surface S2 of the first dielectric layer 111. The conductive connection layer 119 covers the inner wall of the opening H and connects the first and second internal wiring layers 115 and 117. The second dielectric layer 113 fills the opening H, and the second dielectric layer 113 has a third surface S3 and a fourth surface S4 opposite to each other, wherein the third surface S3 and the fourth surface S4 respectively align the first inner circuit layer 115 and the second inner circuit layer 117. Here, the first dielectric layer 111 may use a general dielectric material, wherein a dielectric constant of the first dielectric layer 111 may be lower than 4.0, and a dielectric loss (Df) of the first dielectric layer 111 may be lower than 0.01, thereby providing proper impedance matching. The dielectric constant of the second dielectric layer 113 may be lower than 5.0, and the dielectric loss (Df) of the second dielectric layer 113 may be greater than 0 and less than 0.025 to provide proper insulation and impedance matching, as well as lower dielectric loss.
Furthermore, the third dielectric layer 120 of the present embodiment covers the first inner circuit layer 115 and the third surface S3 of the second dielectric layer 113. The fourth dielectric layer 130 covers the second inner circuit layer 117 and the fourth surface S4 of the second dielectric layer 113. The first external circuit layer 140 is disposed on the third dielectric layer 120, and the second external circuit layer 150 is disposed on the fourth dielectric layer 130. The conductive via 160 penetrates the third dielectric layer 120, the second dielectric layer 113 and the fourth dielectric layer 130, and is electrically connected to the first external circuit layer 140 and the second external circuit layer 150. The conductive via 160 includes a via 162, a conductive material layer 164, and a fill material 166. The through hole 162 penetrates the third dielectric layer 120, the second dielectric layer 113 and the fourth dielectric layer 130. The conductive material layer 164 covers the inner wall of the through hole 162 and electrically connects the first external circuit layer 140 and the second external circuit layer 150. The via-filling material 166 fills the through-hole 162, and the first and second external wiring layers 140 and 150 cover the upper and lower surfaces 167 and 169, respectively, of the via-filling material 166 opposite to each other. Here, the first external circuit layer 140 and the second external circuit layer 150 are multi-layered structure layers, and each of the layers is composed of a copper foil layer C1, a copper plating layer C2, and a cap layer C3, wherein the copper plating layer C2 is located between the copper foil layer C1 and the cap layer C3, and the copper plating layer C2 and the conductive material layer 164 are the same film layer. The cap layer C3 is, for example, a copper layer, but not limited to, covering the upper surface 167 and the lower surface 169 of the filler material 166.
In the present embodiment, the first annular retaining wall 170 is buried in the third dielectric layer 120, surrounds the conductive via 160, and is electrically connected to the first external circuit layer 140 and the first internal circuit layer 115. The second annular retaining wall 180 is embedded in the fourth dielectric layer 130, surrounds the conductive via 160, and is electrically connected to the second external circuit layer 150 and the second internal circuit layer 117. In particular, referring to fig. 1C, 1D and 1E, the first ground line 144, the first annular retaining wall 170 and the first inner line layer 115 define a ground path L3 (i.e. a first ground path), and the ground path L3 surrounds the first signal line 142 in a closed enclosure, so that a good high-frequency high-speed loop can be formed. The second ground line 154, the second annular retaining wall 180 and the second inner circuit layer 117 define a ground path L4 (i.e. a second ground path), and the ground path L4 surrounds the second signal line 152 in a closed manner, so that a good high-frequency high-speed loop can be formed. Here, the ground path L3 and the ground path L4 are each a U-like path.
Referring to fig. 1B again, the first external circuit layer 140, the conductive via 160 and the second external circuit layer 150 define a signal path L1. The first external circuit layer 150, the first annular retaining wall 170, the first internal circuit layer 115, the connecting circuit layer 119, the second internal circuit layer 117, the second annular retaining wall 180 and the second external circuit layer 150 define a ground path L2 (i.e. a third ground path), and the ground path L2 surrounds the signal path L1. Further, the first external circuit layer 140 includes a first signal circuit 142 and a first ground circuit 144. The second external wiring layer 150 includes a second signal wiring 152 and a second ground wiring 154. The first signal line 142, the conductive via 160, and the second signal line 152 define a signal path L1. The first ground line 144, the first annular retaining wall 170, the first inner circuit layer 115, the conductive connection layer 119, the second inner circuit layer 117, the second annular retaining wall 180 and the second ground line 154 define a ground path L2, and the ground path L2 surrounds the signal path L1. Since the signal path L1 is surrounded by the ground path L2 and is enclosed in a closed manner, a good high-frequency high-speed circuit can be formed.
In the process, if the third dielectric layer 120 and the fourth dielectric layer 130 are made of photo-imageable dielectric (photoimageable dielectric, PID) materials, dry-Film Lamination (Dry-Film Lamination) can be performed on opposite sides of the substrate 110, and closed trenches with a width of 100 μm and a diameter of 600 μm can be formed on the third dielectric layer 120 and the fourth dielectric layer 130 respectively by photolithography (photolithography process). Alternatively, if the third dielectric layer 120 and the fourth dielectric layer 130 are prepregs (pre-preg) or an Ajinomoto Build-up Film (ABF), closed trenches having a width of, for example, 100 micrometers and a diameter of, for example, 600 micrometers may be formed on the third dielectric layer 120 and the fourth dielectric layer 130, respectively, by laser ablation. Then, a conductive metal paste (such as a conductive copper paste) is applied in the trench by transient liquid phase sintering (Transient Liquid Phase Sintering, TLPS) and air-dried, so that the conductive metal paste has conductive and heat-conductive effects, is suitable for bonding with any metal material, and is not transformed back into a liquid state due to heating, thereby completing the manufacture of the second annular retaining wall 180 of the first annular retaining wall 170.
It should be noted that, in the present embodiment, the first annular retaining wall 170 and the second annular retaining wall 180 are formed by filling the third dielectric layer 120 and the fourth dielectric layer 130 with conductive paste, so that the first annular retaining wall 170 and the second annular retaining wall 180 are solid retaining wall structures respectively, but not limited thereto, the conductive material of the annular retaining wall may be a metal plating layer or a electroless plating layer. In another embodiment, the first annular retaining wall and the second annular retaining wall can be formed by metal plating, electroless plating, or metal conductive paste in the third dielectric layer and the fourth dielectric layer, so that the first annular retaining wall and the second annular retaining wall can be groove-shaped retaining wall structures respectively, which still belong to the scope of the invention.
In short, the signal path L1 defined by the first signal line 142, the conductive via 160 and the second signal line 152 in this embodiment is surrounded by the ground path L2 defined by the first ground line 144, the first annular retaining wall 170, the first inner line layer 115, the conductive connecting layer 119, the second inner line layer 117, the second annular retaining wall 180 and the second ground line 154. That is, the periphery of the signal path L1 for transmitting the high-frequency and high-speed signals such as 5G is provided with the grounding path L2 with good sealing property, so that a good high-frequency and high-speed loop can be formed, and the circuit board structure 100 of the present embodiment can have better signal integrity. Here, the high frequency means a frequency greater than 1GHz; and the high speed means that the data transmission speed is greater than 100Mbps.
Furthermore, since the first annular retaining wall 170 and the second annular retaining wall 180 are closed structures with a surface screen (closed boundary), the signal of the conductive via 160 can be completely covered. Compared with the prior art, in which a single row of blind holes with gaps are disposed around the conductive via, the circuit board structure 100 of the present embodiment can effectively prevent energy loss and reduce noise interference, and has better signal integrity. In addition, the conductive via 160, the conductive connection layer 119, and the second dielectric layer 113 define a coaxial via (coaxial via), wherein the second dielectric layer 113 is located between the conductive via 160 and the conductive connection layer 119. Compared with the prior art in which the inner conductor layer and the outer conductor layer of the coaxial via hole are blocked by the build-up method of laminating the insulating layer, the manufacturing method of the circuit board structure 100 of the present embodiment can avoid the problem that the integrity of the high frequency signal is affected due to the impedance mismatch.
Fig. 2A is a schematic cross-sectional view illustrating a circuit board structure according to another embodiment of the invention in a first position. Fig. 2B is a schematic cross-sectional view of the circuit board structure of fig. 2A docked in a second position. Referring to fig. 2A and fig. 2B, in the present embodiment, the circuit board structure 200 includes two circuit board units and a connection structure layer CS, wherein each circuit board unit is the circuit board structure 100 in fig. 1B. The connection structure layer CS is disposed between the circuit board structures 100 and electrically and structurally connects the first external circuit layers 140 of each circuit board structure 100, so that the two circuit board structures 100 are butted together. Here, the first position P1 and the second position P2 of the upper circuit board structure 100 are respectively abutted to the first position P1 and the second position P2 of the lower circuit board structure 100. Specifically, the ground path L3 (i.e., the first ground path) of each circuit board structure 100 (please refer to fig. 1C) is connected through the connection structure CS to define a ground path L23 (i.e., the third ground path).
In detail, in the present embodiment, the connection structure layer CS includes a connection layer 210, a plurality of first conductive bonding portions 220, and a second conductive bonding portion 230. The second conductive bonding portion 230 is disposed corresponding to the conductive via 160 of each circuit board structure 100 and is connected to the first signal line 142. The first conductive bond 220 surrounds the second conductive bond 230 and connects the first ground line 144.
As shown in fig. 2A, when the circuit board structures 100 are mated together, the second signal line 152, the conductive via 160, the first signal line 142, the second conductive joint 230 of the upper circuit board structure 100, the first signal line 142, the conductive via 160, and the second signal line 152 of the lower circuit board structure 100 define a signal path L21. The second ground line 154, the second annular retaining wall 180, the second inner line layer 117, the conductive connection layer 119, the first inner line layer 115, the first annular retaining wall 170, the first ground line 144, the first conductive joint 220, the first ground line 144 of the underlying circuit board structure 100, the first annular retaining wall 170, the first inner line layer 115, the conductive connection layer 119, the second inner line layer 117, the second annular retaining wall 180, and the second ground line 154 define a ground path L22 (i.e., a fourth ground path), and the ground path L22 surrounds the signal path L21. Since the signal path L21 is surrounded by the ground path L22 and is enclosed in a closed manner, a good high-frequency high-speed circuit can be formed.
Furthermore, as shown in fig. 2B, the second ground line 154, the second annular retaining wall 180 and the second inner circuit layer 117 of the upper circuit board structure 100 define a ground path L24 (i.e. a second ground path), and the ground path L24 surrounds the second signal line 152 in a closed manner, so that a good high-frequency and high-speed loop can be formed. Here, the ground path L24 is a U-like path. Furthermore, the first inner circuit layer 115, the first annular retaining wall 170, the first grounding trace 144, the first conductive connection portion 220, the first grounding trace 144, the first annular retaining wall 170, and the first inner circuit layer 115 of the other circuit board structure 100 define a third grounding path L23, and the third grounding path L23 surrounds the first signal trace 142 of each circuit board structure 100 in a closed enclosure, so that a good high-frequency and high-speed loop can be formed. In addition, the second ground line 154, the second annular retaining wall 180 and the second inner circuit layer 117 of the lower circuit board structure 100 define a ground path L24 (i.e. a second ground path), and the ground path L24 surrounds the second signal line 152 in a closed manner, so that a good high-frequency and high-speed loop can be formed. Here, the ground path L24 is a U-like path.
It should be noted that the above embodiment refers to the manner of docking the first external circuit layers of the two circuit board structures located at the same position. However, in other docking embodiments not shown, it is also possible that the first external circuit layer of one circuit board structure is docked to the second external circuit layer of another circuit board structure; or, butt-jointing the second external circuit layers of the two circuit board structures together; or, two circuit board structures located at different positions are abutted together through the connecting structure layer, which belongs to the scope of the invention.
Fig. 3 is a schematic partial cross-sectional view of an electronic device including the circuit board structure of fig. 2A. Referring to fig. 3, in the present embodiment, the electronic device 10 includes the circuit board structure 100 and the electronic component 20 as described above, for example, in fig. 2A, wherein the electronic component 20 is electrically connected to the circuit board structure 200, and the electronic component 20 includes a plurality of pads 22. In addition, the electronic device 10 of the present embodiment further includes a plurality of connectors 30 disposed between the second external circuit layer 150 of the circuit board structure 200 and the pads 22 of the electronic component 20, wherein the electronic component 20 is electrically connected to the circuit board structure 200 through the connectors 30. Here, the connecting member 30 is, for example, a solder ball, but not limited thereto. In application, an antenna structure can be disposed on the other side of the circuit board structure 200 opposite to the electronic component 20, so as to solve the problem of signal interference in the same plane, reduce signal energy loss and noise interference, and further improve signal transmission reliability.
In summary, in the design of the circuit board structure of the present invention, the annular retaining wall surrounds the conductive via, wherein the annular retaining wall is a closed structure of a panel (closed boundary), which can reduce electromagnetic interference (EMI) and completely cover the signal of the conductive via. Compared with the prior art that the single row blind holes with gaps are arranged around the conductive through holes, the circuit board structure can effectively prevent energy loss and reduce noise interference, and has better signal integrity.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A circuit board structure, comprising:
a substrate having an opening and including a first dielectric layer, a second dielectric layer, a first inner circuit layer, a second inner circuit layer and a conductive connection layer, wherein the opening penetrates through the first dielectric layer, the first dielectric layer has a first surface and a second surface opposite to each other, the first inner circuit layer is configured on the first surface, the second inner circuit layer is configured on the second surface, the conductive connection layer covers an inner wall of the opening and connects the first inner circuit layer and the second inner circuit layer, the second dielectric layer fills the opening, and the second dielectric layer has a third surface and a fourth surface opposite to each other;
a third dielectric layer covering the first inner circuit layer and the third surface;
a fourth dielectric layer covering the second internal circuit layer and the fourth surface;
the first external circuit layer is configured on the third dielectric layer and comprises a first signal circuit and a first grounding circuit;
a second external circuit layer disposed on the fourth dielectric layer and including a second signal circuit and a second ground circuit;
a conductive via penetrating the third dielectric layer, the second dielectric layer, and the fourth dielectric layer and electrically connecting the first external circuit layer and the second external circuit layer;
the first annular retaining wall is arranged in the third dielectric layer, surrounds the conductive through hole and is electrically connected with the first external circuit layer and the first internal circuit layer, wherein the first grounding circuit, the first annular retaining wall and the first internal circuit layer define a first grounding path, and the first grounding path surrounds the first signal circuit; and
the second annular retaining wall is arranged in the fourth dielectric layer, surrounds the conductive through hole and is electrically connected with the second external circuit layer and the second internal circuit layer, wherein the second grounding circuit, the second annular retaining wall and the second internal circuit layer define a second grounding path, and the second grounding path surrounds the second signal circuit.
2. The circuit board structure of claim 1, wherein the first signal trace, the conductive via, and the second signal trace define a signal path, the first ground trace, the first annular wall, the first inner trace layer, the conductive connection layer, the second inner trace layer, the second annular wall, and the second ground trace define a third ground path, and the third ground path surrounds the signal path.
3. The circuit board structure of claim 1, wherein the conductive via includes a via, a conductive material layer, and a fill material, the via penetrates through the third dielectric layer, the second dielectric layer, and the fourth dielectric layer, and the conductive material layer covers an inner wall of the via and electrically connects the first external wiring layer and the second external wiring layer, the fill material fills the via, and the first external wiring layer and the second external wiring layer cover an upper surface and a lower surface of the fill material, respectively, opposite to each other.
4. The circuit board structure of claim 1, wherein the first and second ground paths are each U-like paths.
5. A circuit board structure, comprising:
two circuit board units, each of the two circuit board units comprising:
a substrate having an opening and including a first dielectric layer, a second dielectric layer, a first inner circuit layer, a second inner circuit layer and a conductive connection layer, wherein the opening penetrates through the first dielectric layer, the first dielectric layer has a first surface and a second surface opposite to each other, the first inner circuit layer is configured on the first surface, the second inner circuit layer is configured on the second surface, the conductive connection layer covers an inner wall of the opening and connects the first inner circuit layer and the second inner circuit layer, the second dielectric layer fills the opening, and the second dielectric layer has a third surface and a fourth surface opposite to each other;
a third dielectric layer covering the first inner circuit layer and the third surface;
a fourth dielectric layer covering the second internal circuit layer and the fourth surface;
the first external circuit layer is configured on the third dielectric layer and comprises a first signal circuit and a first grounding circuit;
a second external circuit layer disposed on the fourth dielectric layer and including a second signal circuit and a second ground circuit;
a conductive via penetrating the third dielectric layer, the second dielectric layer, and the fourth dielectric layer and electrically connecting the first external circuit layer and the second external circuit layer;
the first annular retaining wall is arranged in the third dielectric layer, surrounds the conductive through hole and is electrically connected with the first external circuit layer and the first internal circuit layer, wherein the first grounding circuit, the first annular retaining wall and the first internal circuit layer define a first grounding path, and the first grounding path surrounds the first signal circuit; and
the second annular retaining wall is arranged in the fourth dielectric layer, surrounds the conductive through hole and is electrically connected with the second external circuit layer and the second internal circuit layer, wherein the second grounding circuit, the second annular retaining wall and the second internal circuit layer define a second grounding path, and the second grounding path surrounds the second signal circuit; and
the connecting structure layer is configured between the two circuit board units and electrically and structurally connects the first external circuit layer of each of the two circuit board units so as to enable the two circuit board units to be butted together, wherein the first grounding path of each of the two circuit board units is connected through the connecting structure layer to define a third grounding path.
6. The circuit board structure of claim 5, wherein the connection structure layer comprises a connection layer, a plurality of first conductive joints and a second conductive joint, the second conductive joint being disposed corresponding to the conductive via of each of the two circuit board units and connecting the first signal trace, and the plurality of first conductive joints surrounding the second conductive joint and connecting the first ground trace.
7. The circuit board structure of claim 6, wherein when the two circuit board units are mated together, the second signal line, the conductive via, the first signal line, the second conductive bond, the first signal line, the conductive via, and the second signal line of the other of the two circuit board units define a signal path, and the second ground line, the second annular wall, the second inner line layer, the conductive connection layer, the first inner line layer, the first annular wall, the first ground line, the first plurality of first conductive bonds, the first ground line of the other of the two circuit board units, the first annular wall, the first inner line layer, the conductive connection layer, the second inner line layer, the second annular wall, and the second ground line define a fourth ground path, and the fourth ground path surrounds the fourth ground path.
8. The circuit board structure of claim 6, wherein when the two circuit board units are docked together, the first inner circuit layer, the first annular retaining wall, the first ground trace, the first plurality of first conductive joints, the first ground trace of the other of the two circuit board units, the first annular retaining wall, the first inner circuit layer define the third ground path, and the third ground path surrounds the first signal trace of each of the two circuit board units.
9. The circuit board structure of claim 5, wherein the conductive via includes a via, a conductive material layer and a fill material, the via penetrates through the third dielectric layer, the second dielectric layer and the fourth dielectric layer, the conductive material layer covers an inner wall of the via and electrically connects the first external circuit layer and the second external circuit layer, the fill material fills the via, and the first external circuit layer and the second external circuit layer cover an upper surface and a lower surface of the fill material, respectively, opposite to each other.
10. The circuit board structure of claim 5, wherein the first and second ground paths are each U-like paths.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163279661P | 2021-11-15 | 2021-11-15 | |
| US63/279,661 | 2021-11-15 |
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| Publication Number | Publication Date |
|---|---|
| CN116133230A true CN116133230A (en) | 2023-05-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210617226.0A Pending CN116133229A (en) | 2021-11-15 | 2022-06-01 | Circuit board structure |
| CN202210751138.XA Pending CN116133230A (en) | 2021-11-15 | 2022-06-29 | Circuit board structure |
| CN202210751679.2A Pending CN116133231A (en) | 2021-11-15 | 2022-06-29 | Circuit board structure |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210617226.0A Pending CN116133229A (en) | 2021-11-15 | 2022-06-01 | Circuit board structure |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210751679.2A Pending CN116133231A (en) | 2021-11-15 | 2022-06-29 | Circuit board structure |
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| CN (3) | CN116133229A (en) |
| TW (3) | TWI804335B (en) |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW507476B (en) * | 1999-11-09 | 2002-10-21 | Gul Technologies Singapore Ltd | Printed circuit boards with in-board shielded circuitry and method of producing the same |
| KR100875625B1 (en) * | 2005-11-14 | 2008-12-24 | 티디케이가부시기가이샤 | Composite wiring board and its manufacturing method |
| TWM432222U (en) * | 2011-11-18 | 2012-06-21 | Career Technology Mfg Co Ltd | Multilayer flexible circuit board |
| TWI469698B (en) * | 2012-08-08 | 2015-01-11 | Unimicron Technology Corp | Circuit structure and manufacturing method thereof |
| CN103633060B (en) * | 2012-08-24 | 2016-08-17 | 钰桥半导体股份有限公司 | There is the wiring board of embedded element and electromagnetic barrier |
| TW201507555A (en) * | 2013-08-09 | 2015-02-16 | Bridge Semiconductor Corp | Wiring board with hybrid core and dual build-up circuitries |
| US9913385B2 (en) * | 2015-07-28 | 2018-03-06 | Bridge Semiconductor Corporation | Methods of making stackable wiring board having electronic component in dielectric recess |
| US9837347B2 (en) * | 2015-08-14 | 2017-12-05 | Dyi-chung Hu | Coaxial copper pillar |
| US10349520B2 (en) * | 2017-06-28 | 2019-07-09 | Catlam, Llc | Multi-layer circuit board using interposer layer and conductive paste |
| JP6810001B2 (en) * | 2017-08-24 | 2021-01-06 | 株式会社Ｓｏｋｅｎ | High frequency transmission line |
| JP6845118B2 (en) * | 2017-10-25 | 2021-03-17 | 株式会社Ｓｏｋｅｎ | High frequency transmission line |
| TWI730395B (en) * | 2019-09-04 | 2021-06-11 | 同泰電子科技股份有限公司 | Electromagnetic interference shielding structure, flexible circuit board having electromagnetic interference shielding structure and manufacturing method thereof |
| CN212628559U (en) * | 2020-07-08 | 2021-02-26 | 成都市一博科技有限公司 | PCB via hole structure meeting ultrahigh frequency radio frequency signal requirement |
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- 2022-06-01 TW TW111120375A patent/TWI804335B/en active
- 2022-06-01 CN CN202210617226.0A patent/CN116133229A/en active Pending
- 2022-06-29 CN CN202210751138.XA patent/CN116133230A/en active Pending
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| TW202322665A (en) | 2023-06-01 |
| TW202322668A (en) | 2023-06-01 |
| TWI804335B (en) | 2023-06-01 |
| TWI808819B (en) | 2023-07-11 |
| CN116133229A (en) | 2023-05-16 |
| TW202322684A (en) | 2023-06-01 |
| TWI815528B (en) | 2023-09-11 |
| CN116133231A (en) | 2023-05-16 |
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