TW202318504A - 電漿處理方法 - Google Patents

電漿處理方法 Download PDF

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TW202318504A
TW202318504A TW111128294A TW111128294A TW202318504A TW 202318504 A TW202318504 A TW 202318504A TW 111128294 A TW111128294 A TW 111128294A TW 111128294 A TW111128294 A TW 111128294A TW 202318504 A TW202318504 A TW 202318504A
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中谷侑亮
園田靖
田中基裕
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日商日立全球先端科技股份有限公司
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Abstract

向側方且相對於SiGe選擇性地蝕刻HfO 2。一種電漿處理方法，係為了製造GAA等的次世代三維構造元件而使用可進行自由基蝕刻的真空處理裝置，向側方蝕刻HfO 2，該電漿處理方法，其特徵係，將SiCl 4氣體添加至BCl 3氣體，並設成為「此時之SiCl 4氣體的流量比例比BCl 3氣體的流量比例低，且堆積於SiGe上之SiCl x沈積比HfO 2多」的流量比例，藉此，相對於SiGe選擇性地蝕刻HfO 2。

Description

電漿處理方法
本發明，係關於電漿處理方法。
在半導體元件之製造工程中，係被要求應對於半導體裝置中所含有的組件之微細化或積體化。例如，在積體電路或奈米機電系統中，構造物的奈米尺度化進一步被推進。
通常，在半導體元件之製造工程中，為了形成微細圖案而使用微影技術。該技術，係將元件構造的圖案應用於光阻層之上，選擇性地蝕刻藉由光阻層之圖案而露出的基板。在其後的處理工程中，只要使其他材料堆積於蝕刻區域內，則可形成集成電路。
特別是近年來，對於半導體元件，來自巿場之省電力･高速化的要求提高，元件構造之複雜化･高積體化的傾向顯著。例如在邏輯元件中，係檢討以經層積的奈米線構成通道之GAA(Gate All Around)的應用，在GAA之蝕刻工程中，係除了由以往的異向性蝕刻所進行的垂直加工以外，還需要為了形成奈米線而由等向性蝕刻向側方進行加工。
在此，異向性蝕刻，係指藉由離子促進自由基的反應之利用離子輔助反應的蝕刻，等向性蝕刻，係指以僅由自由基所進行的表面反應作為主體之蝕刻。在GAA等的次世代三維元件之製造中，係有多數個「要求由等向性蝕刻向側方進行蝕刻」的工程，例如需要相對於矽鍺SiGe高選擇性地向側方蝕刻閘極絕緣膜所使用的介電係數高之氧化鉿HfO 2的技術。
對於像這樣的要求，在專利文獻1中，係提出如下述般技術：在遠程電漿產生裝置中，使氬等的非反應性氣體、氧等的氧原子供給性氣體及氮氧化物等的氧化性氣體之至少一種活性化而成為包含有活性種的氣體，並將該氣體與三氯化硼BCl 3等的鹵素系氣體一起導入至腔室，藉此，蝕刻HfO 2。
又，在專利文獻2中，係提出如下述般技術：以從包含有含鹵素氣體之蝕刻氣體混合物所產生的電漿，蝕刻HfO 2。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2006-339523號公報 [專利文獻2]日本特開2009-21584號公報
[本發明所欲解決之課題]
為了向側方蝕刻閘極絕緣膜所使用的氧化鉿HfO 2，係需要遮蔽進行縱方向之蝕刻的離子而僅以自由基進行蝕刻。但是，由於記載於專利文獻2之技術，係並非為僅由遮蔽了離子之自由基所進行的蝕刻，因此，吾人認為離子入射所致之縱方向的蝕刻會進行。
又，在GAA等的次世代三維元件之製造中，係雖被要求相對於矽鍺SiGe高選擇性地蝕刻氧化鉿HfO 2，但專利文獻1、2皆並未提及關於相對於矽鍺SiGe選擇性地蝕刻氧化鉿HfO 2的技術。 [用以解決課題之手段]
為了解決上述課題，係藉由下述方式來達成：一種電漿處理方法，係為了製造GAA等的次世代三維構造元件而使用可進行自由基蝕刻的真空處理裝置，向側方蝕刻氧化鉿HfO 2，該電漿處理方法，其特徵係， 將四氯化矽SiCl 4氣體添加至三氯化硼BCl 3氣體，並設成為「此時之四氯化矽SiCl 4氣體的流量比例比三氯化硼BCl 3氣體的流量比例低，且堆積於矽鍺SiGe上之SiCl x沈積比氧化鉿HfO 2多」的流量比例，藉此，相對於矽鍺SiGe選擇性地蝕刻氧化鉿HfO 2。
又，藉由下述方式來達成：在上述電漿處理方法中，將四氯化矽SiCl 4氣體的流量比例設成為3~20%。 [發明之效果]
根據本發明，可提供一種可向側方且相對於矽鍺SiGe選擇性地蝕刻氧化鉿HfO 2的電漿處理方法。
以下，參閱圖面，說明本發明之實施形態。
[第1實施形態] 圖1，係本發明的第1實施形態之真空處理裝置的概略整體構成剖面圖。圖2，係表示本發明的第1實施形態之遮蔽板的平面圖。
在圖1中，表示本發明的第1實施形態之真空處理裝置的概略整體構成剖面圖。在本實施形態之裝置中，係藉由從高頻電源即磁控管103經由介電質窗111被供給至真空處理室117之2.45GHz的微波與磁場形成機構即螺管線圈108所產生的磁場之電子迴旋共振(Electron Cyclotron Resonance、ECR)，可在真空處理室117內生成電漿。將像這樣的真空處理裝置稱為ECR電漿處理裝置。
又，高頻電源124經由匹配器123與載置於試料台115的試料116連接。真空處理室117之內部，係經由閥121被連接於泵122，可藉由閥121的開合度來調節內部壓力。
又，本真空處理裝置，係在真空處理室117之內部具有圖2所示的石英製之遮蔽板113。在遮蔽板113，係相同之孔徑的貫通孔131被均勻地被配置於外周部。在本實施形態中，所謂「均勻」，係指在描繪直徑之差相等的同心圓(包含半徑為零的情形)時，具有中心點的貫通孔131沿圓周方向而以相等間距被配置於相同圓上。藉由遮蔽板113，將真空處理室117內分割成第1空間118與第2空間119，壓力計125被連接於第2空間119內。
本實施形態中所使用的電漿處理裝置，係在微波之頻率為2.45GHz的情況下，具有可在磁場強度0.0875T之面附近生成電漿這樣的特性。因此，若以使電漿生成區域位於遮蔽板113與介電質窗111之間(第1空間118)的方式調整磁場，則可在遮蔽板113之介電質窗111側生成電漿，由於所產生之離子，係幾乎無法通過遮蔽板113，因此，可僅將自由基照射至試料116。此時，在試料116中，係進行「以僅由自由基所進行的表面反應作為主體」之等向性蝕刻。
對此，若以使電漿生成區域位於遮蔽板113與試料116之間(第2空間119)的方式調整磁場，則可在比遮蔽板113更靠試料116側生成電漿，並可將離子與自由基兩者供給至試料116。此時，在試料116中，係進行「藉由離子促進自由基的反應之利用離子輔助反應」的異向性蝕刻。
另外，電漿生成區域之高度位置相對於遮蔽板113之高度位置的調整或切換(上方或下方)、保持各自的高度位置之高度位置的調整等，係可使用控制裝置120來進行。
在本發明之第1實施形態中，係以使電漿生成區域位於遮蔽板113與介電質窗111之間(第1空間118)的方式調整磁場，並藉由「以僅由自由基所進行的表面反應作為主體」之等向性蝕刻，向側方蝕刻試料116。藉由將三氯化硼BCl 3氣體與四氯化矽SiCl 4氣體之混合氣體導入至真空處理室117內而生成電漿的方式，從生成於第1空間118內之電漿所生成的自由基會通過被配置於遮蔽板113的貫通孔131而到達試料116，藉此，進行蝕刻。此時，以「使試料116為氧化鉿HfO 2時之蝕刻率比試料116為矽鍺SiGe時之蝕刻率高，亦即使HfO 2相對於SiGe膜選擇性地被蝕刻」的方式，調整BCl 3氣體與SiCl 4氣體之流量比例。試料116，係指在GAA(Gate All Around)等的次世代三維元件之製造中所使用的半導體製造用之基板。在GAA等的次世代三維元件之製造中，係有多數個「要求由等向性蝕刻向側方進行蝕刻」的工程。例如，相對於SiGe高選擇性地向側方蝕刻閘極絕緣膜所使用的介電係數高之HfO 2。在試料116中，係向層積有SiGe之方向的垂直方向蝕刻HfO 2。因此，在「相對於作為試料116的半導體基板之水平方向的表面，SiGe之複數層被層積於垂直方向即縱方向」的情況下，係相對於縱方向而向垂直方向即側方(亦即，水平方向)蝕刻HfO 2。
圖3，係表示本發明的第1實施形態之「HfO 2與SiGe的蝕刻率」和「BCl 3氣體與SiCl 4氣體的混合氣體系統中之SiCl 4氣體的流量比例」之相依性的曲線圖。
在SiCl 4氣體之流量比例為0%亦即僅以BCl 3氣體進行蝕刻時，係SiGe其蝕刻率比HfO 2高，且無法相對於SiGe選擇性地蝕刻HfO 2。藉由向其添加SiCl 4氣體的方式，當將SiCl 4氣體之流量比例設成為3%以上時，則HfO 2的蝕刻率比SiGe的蝕刻率高，可相對於SiGe選擇性地蝕刻HfO 2。亦即，使用BCl 3氣體與SiCl 4氣體的混合氣體，蝕刻HfO 2。而且，設成為SiCl 4氣體之流量比BCl 3氣體之流量少的構成為較佳。而且，當增加SiCl 4氣體之流量比例時，則由於SiCl x沈積進行堆積而阻礙蝕刻，因此，HfO 2、SiGe的蝕刻率皆下降。
圖3雖係SiCl 4之流量比例至17%左右為止的曲線圖，但當進一步將蝕刻率之曲線外推至SiCl 4之流量比例高的區域時，則可假定SiCl 4之流量比例至20%左右為止，係HfO 2其蝕刻率比SiGe高，且在SiCl 4之流量比例成為了20%以上時，HfO 2的蝕刻率比為負而蝕刻不會進行。因此，在BCl 3+SiCl 4氣體系統中，將SiCl 4氣體的流量比例設成為3~20%之範圍內的值，藉此，相對於SiGe選擇性地蝕刻HfO 2。SiCl 4氣體之添加，係雖在試料116上生成SiCl x沈積而使蝕刻率下降，但在上述SiCl 4氣體之流量比例為3~20%的區域中，係由於堆積於SiGe上之SiCl x沈積比HfO 2多，因此，可相對於SiGe選擇性地蝕刻HfO 2。亦即，SiCl 4氣體之流量相對於混合氣體之流量的比，係可為「堆積於SiGe上之SiCl x沈積膜的厚度比堆積於HfO 2上之SiCl x沈積膜的厚度厚」之值。另外，此時的真空處理室117內之第2空間119的壓力，係1~8mTorr，載置試料116之試料台115的溫度，係50℃以上。
圖4，係表示本發明的第1實施形態之「HfO 2相對於SiGe的蝕刻率選擇比」和「BCl 3氣體與SiCl 4氣體的混合氣體系統中之SiCl 4氣體的流量比例」之相依性的曲線圖。選擇比，係藉由將HfO 2之蝕刻率除以SiGe之蝕刻率而求出。曲線圖內，係以虛線記載HfO 2相對於SiGe之蝕刻率選擇比為1的線，在該選擇比為1以上時，可相對於SiGe選擇性地蝕刻HfO 2。可知在BCl 3氣體與SiCl 4氣體之混合氣體系統中，在SiCl 4氣體的流量比例為3%以上時，選擇比為1以上，可相對於SiGe選擇性地蝕刻HfO 2。圖4雖係SiCl 4氣體之流量比例至17%左右為止的曲線圖，但如圖3中所推測般，SiCl 4氣體之流量比例至20%左右為止，係選擇比為1以上，可相對於SiGe選擇性地蝕刻HfO 2。
本發明，係可利用於相對於SiGe而選擇性地電漿蝕刻Gate All Around構造之閘極絕緣膜即HfO 2的電漿處理方法及相對於SiGe而選擇性地電漿蝕刻HfO 2的電漿處理方法。
上述實施例，係為了易於理解本發明而詳細進行說明者，並不一定限定於具備所說明的全部構成者。
103:磁控管 108:螺管線圈 111:介電質窗 113:遮蔽板 115:試料台 116:試料 117:真空處理室 118:第1空間 119:第2空間 120:控制裝置 121:閥 122:泵 123:匹配器 124:高頻電源 125:壓力計 131:遮蔽板113之貫通孔
[圖1]圖1，係本發明的第1實施形態之真空處理裝置的概略整體構成剖面圖。 [圖2]圖2，係表示本發明的第1實施形態之遮蔽板的平面圖。 [圖3]圖3，係表示本發明的第1實施形態之「HfO 2與SiGe的蝕刻率」和「BCl 3氣體與SiCl 4氣體的混合氣體系統中之SiCl 4氣體的流量比例」之相依性的曲線圖。 [圖4]圖4，係表示本發明的第1實施形態之「HfO 2相對於SiGe的蝕刻率選擇比」和「BCl 3氣體與SiCl 4氣體的混合氣體系統中之SiCl 4氣體的流量比例」之相依性的曲線圖。
103:磁控管
108:螺管線圈
111:介電質窗
113:遮蔽板
115:試料台
116:試料
117:真空處理室
118:第1空間
119:第2空間
120:控制裝置
121:閥
122:泵
123:匹配器
124:高頻電源
125:壓力計

Claims (6)

  1. 一種電漿處理方法，係相對於SiGe而選擇性地電漿蝕刻Gate All Around構造之閘極絕緣膜即HfO 2，該電漿處理方法，其特徵係， 使用BCl 3氣體與SiCl 4氣體的混合氣體，蝕刻前述HfO 2， 前述SiCl 4氣體之流量，係比前述BCl 3氣體之流量少。
  2. 如請求項1之電漿處理方法，其中， 向層積有前述SiGe之方向的垂直方向蝕刻前述HfO 2。
  3. 如請求項1之電漿處理方法，其中， 前述SiCl 4氣體之流量相對於前述混合氣體之流量的比，係「堆積於前述SiGe上之沈積膜的厚度比堆積於前述HfO 2上之沈積膜的厚度厚」之值。
  4. 如請求項2之電漿處理方法，其中， 前述SiCl 4氣體之流量相對於前述混合氣體之流量的比，係「堆積於前述SiGe上之沈積膜的厚度比堆積於前述HfO 2上之沈積膜的厚度厚」之值。
  5. 如請求項4之電漿處理方法，其中， 前述SiCl 4氣體之流量相對於前述混合氣體之流量的比，係3~20%之範圍內的值。
  6. 一種電漿處理方法，係相對於SiGe而選擇性地電漿蝕刻HfO 2，該電漿處理方法，其特徵係， 使用BCl 3氣體與SiCl 4氣體的混合氣體，蝕刻前述HfO 2， 前述SiCl 4氣體之流量，係比前述BCl 3氣體之流量少。
TW111128294A 2021-10-22 2022-07-28 電漿處理方法 TWI847200B (zh)

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