TW202243180A - 具有重佈圖案的半導體元件及其製備方法 - Google Patents

具有重佈圖案的半導體元件及其製備方法 Download PDF

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TW202243180A
TW202243180A TW110145887A TW110145887A TW202243180A TW 202243180 A TW202243180 A TW 202243180A TW 110145887 A TW110145887 A TW 110145887A TW 110145887 A TW110145887 A TW 110145887A TW 202243180 A TW202243180 A TW 202243180A
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pad
edge
power
redistribution
central
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TW110145887A
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TWI771241B (zh
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楊吳德
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南亞科技股份有限公司
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Abstract

本揭露提供一種半導體元件和該半導體元件的製備方法。該半導體元件包括一第一基底，該第一基底包括一中心區域和遠離該中心區域的一邊緣區域；設置在該第一基底上的一第一電路層；設置在該第一電路層中和該中心區域上方的一中心電源墊；設置在該第一電路層中和該邊緣區域上方，並與該中心電源墊電性耦合的一邊緣電源墊；設置在該第一電路層上方並與該中心電源墊電性耦合的一重佈電源圖案；以及設置在該邊緣電源墊和該重佈電源圖案之間，並將該邊緣電源墊和該重佈電源圖案電連接的一邊緣電源通孔。該第一基底、該中心電源墊、該邊緣電源墊、該重佈電源圖案和該邊緣電源通孔共同構成一第一半導體晶片。

Description

具有重佈圖案的半導體元件及其製備方法
本申請案主張2021年4月20日申請之美國正式申請案第17/235,571號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露關於一種半導體元件及其製備方法。特別是關於一種具有重佈圖案的半導體元件及其製備方法。
半導體元件應用於各種電子應用，如個人電腦、行動電話、數位相機和其他電子設備。半導體元件的尺寸正在不斷縮小，以滿足日益增長的計算能力的需求。然而，在縮小尺寸的製程中出現了各種問題，而且這種問題在不斷增加。因此，在實現提高品質、產量、性能和可靠性以及降低複雜性方面仍然存在挑戰。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應做為本案之任一部分。
本揭露之一實施例提供一種半導體元件，包括一第一基底，一第一電路層，一中心電源墊，一邊緣電源墊，一重佈電源圖案以及一邊緣電源通孔。該第一基底包括一中心區域和遠離該中心區域的一邊緣區域。該第一電路層設置在該第一基底上。該中心電源墊設置在該第一電路層中和該中心區域上方。該邊緣電源墊設置在該第一電路層中和該邊緣區域上方，並與該中心電源墊電性耦合。該重佈電源圖案設置在該第一電路層上方並與該中心電源墊電性耦合。該邊緣電源通孔設置在該邊緣電源墊和該重佈電源圖案之間，並將該邊緣電源墊和該重佈電源圖案電連接。該第一基底、該中心電源墊、該邊緣電源墊、該重佈電源圖案和該邊緣電源通孔共同構成一第一半導體晶片。
在一些實施例中，該重佈電源圖案包括一重佈中心電源墊，一重佈邊緣電源墊以及一重佈連接線。該重佈中心電源墊設置在該第一電路層上方，在形貌上(topographically)與該中心電源墊對齊，並與該中心電源墊電性耦合。該重佈邊緣電源墊設置在該第一電路層上方，在形貌上與該邊緣電源墊對齊，並通過該邊緣電源通孔與該邊緣電源墊電性耦合。該重佈連接線，連接該重佈中心電源墊和該重佈邊緣電源墊。
在一些實施例中，該半導體包括一輔助電源墊和一輔助通孔。該輔助電源墊經設置在該第一電路層中，設置在該中心電源墊和該邊緣電源墊之間，並與該中心電源墊電性耦合。該輔助通孔將該重佈連接線和該輔助電源墊電連接。
在一些實施例中，該半導體元件包括設置在該第一電路層上的一下層鈍化層。該邊緣電源通孔和該輔助通孔經設置在該下層鈍化層中。
在一些實施例中，該半導體元件包括設置在該下層鈍化層上的一上層鈍化層。該重佈電源圖案經設置在上層鈍化層中。
在一些實施例中，該半導體元件包括設置在該第一基底下方的一封裝基底。
在一些實施例中，該半導體元件包括設置在該封裝基底和該第一基底之間並連接該封裝基底和該第一基底的一第一附著層。
在一些實施例中，該半導體元件包括一導線，將該重佈邊緣電源墊與該封裝基底中的一導電線電連接。
在一些實施例中，該重佈邊緣電源墊與一外部電源電性耦合。
在一些實施例中，該半導體元件包括一中心資料墊和一重佈資料圖案。該中心資料墊經設置在該第一電路層中和該中心區域上方。該重佈資料圖案包括一重佈中心資料墊，一重佈邊緣資料墊以及一重佈資料線。該重佈中心資料墊設置在下層鈍化層上，在形貌上與該中心資料墊對齊，並通過一中心資料通孔與該中心資料墊電性耦合。該重佈邊緣資料墊，設置在該下層鈍化層上和該邊緣區域上方。該重佈資料線將該重佈中心資料墊和該重佈邊緣資料墊連接。
在一些實施例中，該重佈連接線的寬度大於該重佈資料線的寬度。
在一些實施例中，該半導體元件包括設置在該第一電路層中並與該邊緣電源墊在形貌上對齊的一緩衝層。
在一些實施例中，該半導體元件包括設置在該第一半導體晶片旁邊的一第二半導體晶片。該第二半導體晶片通過該第一附著層附著在該封裝基底上。
在一些實施例中，該半導體元件包括堆疊在該第一半導體晶片上的一第二半導體晶片，其間具有一第二附著層。
在一些實施例中，該第二半導體晶片的佈局(layout)和該第一半導體晶片的佈局實質上相同。
本揭露之另一實施例提供一種半導體元件的製備方法。該製備方法包括：提供一第一基底，包括一中心區域和遠離該中心區域的一邊緣區域，在該第一基底上形成一第一電路層，在該第一電路層中和該中心區域上方形成一中心電源墊，在該第一電路層中和該邊緣區域上方形成一邊緣電源墊，並與該中心電源墊電性耦合，在該邊緣電源墊上形成一邊緣電源通孔，以及在該邊緣電源通孔上形成一重佈電源圖案，並與該中心電源墊電性耦合。該第一基底、該中心電源墊、該邊緣電源墊、該重佈電源圖案和該邊緣電源通孔共同構成一第一半導體晶片。
在一些實施例中，該重佈電源圖案包括：在該第一電路層上方的一重佈中心電源墊，在形貌上與該中心電源墊對齊，並與該中心電源墊電性耦合；在該第一電路層上方的一重佈邊緣電源墊，在形貌上與該邊緣電源墊對齊，並通過該邊緣電源通孔與該邊緣電源墊電性耦合，以及連接該重佈中心電源墊和該重佈邊緣電源墊的一重佈連接線。
在一些實施例中，該製備方法包括通過一第一附著層將該第一半導體晶片附著到一封裝基底。
在一些實施例中，該製備方法包括形成一導線，將該重佈邊緣電源墊和該封裝基底中的一導電線電性耦合。
在一些實施例中，該製備方法包括在該封裝基底下方形成一導體，並在該封裝基底中電連接該導電線。
由於本揭露的半導體元件的設計，功率傳輸的不足可以藉由該邊緣電源通孔和該輔助通孔得到緩解。因此，該半導體裝置的性能可以得到改善。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可做為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所定義之本揭露的精神和範圍。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包括特定特徵、結構或是特性，然而並非每一實施例必須包括該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
應當理解，以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實施例或實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，元件的尺寸並非僅限於所揭露範圍或值，而是可相依於製程條件及/或裝置的所期望性質。此外，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。為簡潔及清晰起見，可按不同比例任意繪製各種特徵。在附圖中，為簡化起見，可省略一些層/特徵。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述元件可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行直譯。
圖1是以流程圖的形式，例示本揭露一實施例之用於半導體元件1A的製備方法10。圖2是以示意性俯視圖的形式，例示本揭露一實施例之一中間半導體。圖3是沿圖2中A-A'線拍攝的示意性剖面圖。圖4是沿圖2中B-B'線拍攝的示意性剖面圖。圖5是以示意性剖面特寫圖形式，例示本揭露一實施例之一中間半導體元件。
參照圖1至圖5，在步驟S11，可以提供第一基底101a，在第一基底101a上形成第一電路層103a，在第一電路層103a中可以形成複數個中心電源墊301a、複數個邊緣電源墊303a、複數個輔助電源墊305a和複數個中心資料墊307a。
參照圖2至圖4，第一基底101a可以是一塊狀(bulk)半導體基底。該塊狀半導體基底的製作技術可以是例如矽或鍺等示素半導體，或例如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦等化合物半導體，或其他III-V化合物半導體或II-VI化合物半導體。
在一些實施例中，第一基底101a可以包括一絕緣體上半導體(semiconductor-on-insulator，SOI)結構，該SOI結構從下到上包括：一處理基底、一絕緣體層和一最上面的半導體材料層。該處理基底和該最上面的半導體材料層的製作技術可以是上述塊狀半導體基底相同的材料。該絕緣體層可以是結晶或非結晶的介電材料，如氧化物和/或氮化物。該絕緣體層的厚度可以在大約10奈米和大約200奈米的範圍內。
應當理解，術語"大約"修改本揭露的成分、組分或反應物的數量是指可能發生的數值數量的變化，例如，通過用於製造濃縮物或溶液的典型測量和液體處理程序。此外，測量程序中的疏忽錯誤、用於製造組合物或執行方法的成分的製造、來源或純度的差異等都可能產生變化。在一實施例中，術語"大約"是指報告數值的10%的範圍內。在另一實施例中，術語"大約"是指報告數值的5%的範內。在更另一實施例中，術語"大約"是指報告數值的10、9、8、7、6、5、4、3、2或1%的範圍內。
在一些實施例中，第一基底101a可以包括中心區域CR和兩個相對的邊緣區域ER。中心區域CR可以是兩個相對的邊緣區域ER之間的區域。兩個相對的邊緣區域ER可以位於第一基底101a的兩個側面上，並且在俯視圖中下沿著Y維度。換句話說，兩個相對的邊緣區域ER可以靠近第一基底101a的兩個邊緣或靠近切割道(scribe lines)。
應當理解，中心區域CR可以包括第一基底101a的一部分和第一基底101a的該部分之上的空間。將元件描述為配置在中心區域CR上是指該元件設置在第一基底101a的該部分的一頂面。將元件描述為設置在中心區域CR中是指元件設置在第一基底101a的該部分中；然而，元件的一頂面可以與第一基底101a的該部分的該頂面齊平。將元件描述為設置在中心區域CR上方表示元件設置在第一基底101a的該部分的該頂面之上。相應地，邊緣區域ER可以包括第一基底101a的另一部分和第一基底101a的該另一部分之上的空間。
參照圖2至圖4，第一電路層103a可以形成在第一基底101a上。第一電路層103a可包括層間介電層和/或金屬間介電層，其中包含複數個功能區塊(為清晰起見未顯示)和複數個導電特徵(為清晰起見未顯示)。複數個功能區塊可以是電晶體，如互補金屬氧化物半導體電晶體、金屬氧化物半導體場效應電晶體、鰭狀場效應電晶體等，或其組合 的電晶體。複數個功能區塊可以共同合作，提供各種功能，如邏輯、輸入/輸出(I/O)、記憶體、類比電路等。
該複數個導電特徵可以包括複數個導電插塞、複數個導電線、複數個導電通孔和複數個導電墊，或其他適合的導電元件。複數個導電插塞可以在物理和電氣上與複數個功能區塊相連接。複數個導電線可以相互分離，並可以沿Z維度水平地設置在層間電介層和/或金屬間介電層中。在本揭露的描述中，最上面的導電線可以被指定為複數個導電墊。該複數個導電墊的頂面可以與第一電路層103a的該頂面實質上共面。該複數個導電通孔可沿Z維度連接相鄰的導電線。在一些實施例中，該複數個導電通孔可改善第一電路層103a的散熱，並可在第一電路層103a中提供結構的支持。
該層間介電層和/或該金屬間介電層的製作技術可以是例如氧化矽、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、低介電材料等，或其組合的材料。該低介電材料的介電常數可以小於3.0或甚至小於2.5。在一些實施例中，該低介電材料的介電常數可以小於2.0。該層間介電層和/或該金屬間介電層的製作技術可以是一沉積製程，如化學氣相沉積、電漿增強化學氣相沉積等，或類似的製程。該沉積製程後可進行一平面化處理，以去除多餘的材料，並為後續處理步驟提供一個實質上平整的表面。該複數個功能區塊和該複數個導電特徵可以在形成該層間介電層和/或該金屬間介電層時形成。
該複數個導電特徵的製作技術可以是例如鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如，碳化鉭、碳化鈦、碳化鉭鎂)、金屬氮化物(例如，氮化鈦)、過渡金屬鋁化物或其組合。
參照圖2至圖4，複數個中心電源墊301a可以在第一電路層103a中和中心區域CR上方形成。複數個中心電源墊301a可以與第一電路層103a的該頂面實質上共面。在一些實施例中，複數個中心電源墊301a可以排列成兩列，這兩列在俯視圖中與Y維度平行。
參照圖2至圖4，複數個邊緣電源墊303a可以形成在第一電路層103a中和兩個相對的邊緣區域ER上方。複數個邊緣電源墊303a可以與第一電路層103a的該頂面實質上共面。在一些實施例中，複數個邊緣電源墊303a可以排列成兩列，該兩列在俯視圖中與Y維度平行。該兩列中的一列可以排列在兩個相對的邊緣區域ER其中一者上面，該兩列中的另一列可以排列在兩個相對的邊緣區域ER中的另一者上面。
參照圖2至圖4，複數個輔助電源墊305a可以形成在第一電路層103a中，並在中心區域CR和兩個相對的邊緣區域ER之間的兩個區域上方。複數個輔助電源墊305a可與第一電路層103a的該頂面實質上共面。在一些實施例中，複數個輔助電源墊305a可以排列成兩列，這兩列在俯視圖中與Y維度平行。這兩列可以彼此相對，複數個中心電源墊301a插置其間。
參照圖2至圖4，複數個中心資料墊307a可以形成在第一電路層103a中和中心區域CR的上方。複數個中心資料墊307a可以與第一電路層103a的該頂面實質上共面。在一些實施例中，複數個中心資料墊307a可被排列成兩列，該兩列在俯視圖中與Y維度平行。
在一些實施例中，複數個中心電源墊301a、複數個邊緣電源墊303a、複數個輔助電源墊305a和複數個中心資料墊307a可以分別和相應地與該複數個功能區塊電性耦合。
為了簡明、清晰和描述的方便，只描述複數個中心電源墊301a中的一個的情況。
在一些實施例中，可以在第一電路層103a中形成一焊盤開口(未示出)，並且可以形成一導電材料以填充該焊盤開口來形成中心電源盤301a。該焊盤開口的製作技術可以藉由光學微影(photolithography)製程和隨後的蝕刻製程。最上面的導電特徵的一頂面的一部分可以通過該焊盤曝露出來。
在一些實施例中，該蝕刻製程可以是使用氬氣和四氟甲烷做為蝕刻劑的非等向性乾蝕刻製程。蝕刻製程的處理溫度可在大約120℃和大約160℃的範圍內。蝕刻製程的處理壓力在大約0.3托和大約0.4托的範圍內。蝕刻製程的處理持續時間可在大約33秒和大約39秒的範圍內。另外，在一些實施例中，該蝕刻製程可以是使用氦氣和三氟化氮做為蝕刻劑的非等向性乾蝕刻製程。蝕刻製程的處理溫度可以在大約80℃和大約100℃的範圍內。蝕刻製程的壓力在大約1.2 Torr和大約1.3 Torr的範圍內。蝕刻製程的處理持續時間可在大約20秒和大約30秒的範圍內。
在一些實施例中，在形成該焊盤開口之後，可以進行一清潔製程。該清潔製程可以包括應用氫氣和氬氣的混合物做為遠端電漿源，製程溫度在大約250℃到大約350℃的範圍內，製程壓力在大約1托到大約10托的範圍內，並有一偏壓能量被施加到進行該清潔製程的設備上。該偏壓能量可以在大約0瓦到200瓦的範圍內。該清洗製程可以從通過該焊盤開口曝露的最上面導電特徵的該頂面去除源自空氣中氧氣氧化的氧化物，而不會損壞最上面導電特徵。
隨後可以在第一電路層103a和該焊盤開口上進行鈍化製程。該鈍化製程可以包括在大約200℃和大約400℃的範圍內的處理溫度下，用例如二甲氨基三甲基矽烷(dimethylaminotrimethylsilane)、四甲基矽烷(tetramethylsilane)或類似的前驅物浸泡該中間半導體元件。紫外線輻射可被用來促進鈍化製程。該鈍化製程可以通過密封其表面孔隙來鈍化通過該焊盤開口曝露的第一電路層103a的側壁，以減少不良的側壁生長，這可能會在隨後的處理步驟中影響半導體元件1A的電氣特性。因此，半導體元件1A的性能和可靠性可以得到提高。
在一些實施例中，該焊盤開口可以藉由濺鍍、電鍍或無電電鍍(electroless plating)的方式依次填充導電材料。例如，當藉由濺鍍且使用鋁銅材料做為來源來填充該焊盤開口時，濺鍍的製程溫度可以在大約100℃和大約400℃的範圍內。濺鍍的製程壓力可以在大約1mTorr和大約100mTorr的範圍內。濺鍍後，可進行蝕刻製程，以修整填充的導電材料，形成中心電源墊301a。該蝕刻製程可以使用氯氣和氬氣做為蝕刻劑。氯氣的蝕刻劑流量可以在大約10sccm(標準立方釐米/分鐘)和大約30sccm的範圍內。氬氣的蝕刻劑流量可在大約900sccm和大約1100sccm的範圍內。蝕刻製程的處理溫度可在約50℃和約200℃之間。蝕刻製程的處理壓力可在大約50mTorr和大約10Torr的範圍內。蝕刻製程的處理持續時間可以在大約30秒和大約200秒的範圍內。在這個例子中，中心電源墊301a的厚度可在大約400奈米和大約1100奈米的範圍內，中心電源墊301a的製作技術可以是鋁銅合金。鋁中少量的銅可以提高抗電遷移能力，並更減少丘狀(hillocks)的發生，即鋁薄膜層表面上的鋁的小突起(protrusions)。
在另一例子中，該焊盤開口可以藉由使用電鍍液的電鍍製程來填充。該電鍍液可以包括硫酸銅、甲烷磺酸銅(copper methane sulfonate)、葡萄糖酸銅(copper gluconate)、氨基磺酸銅(copper sulfamate)、硝酸銅、磷酸銅或氯化銅。電鍍液的pH值可以在大約2到大約6的範圍內，或者大約3到大約5的範圍內。該電鍍製程的處理溫度可以保持在大約40℃到大約75℃的範圍內，或者大約50℃到大約70℃的範圍內。在這個例子中，中心電源墊301a的製作技術可以是銅。
在一些實施例中，該電鍍液可包括促進劑、抑制劑或平整劑。該促進劑可包括極性硫(polar sulfu)、氧或氮官能團(nitrogen functional group)，有助於提高沉積率並可促進密集成核(dense nucleation.)。該促進劑可以是低濃度水平的存在，例如，在大約0ppm和大約200ppm的範圍內。該抑制劑是降低電鍍率的添加劑，通常以較高的濃度存在於電鍍液中，例如，大約5ppm和大約1000ppm的範圍內。抑制劑可以是具有高分子量的聚合物表面活性劑，如聚乙二醇(polyethylene glycol)。
抑制劑可以藉由吸附在表面並形成對銅離子的障礙層來減緩沉積速度。由於它們的大尺寸和低擴散率，抑制劑不太可能到達焊盤開口的下部。因此，大部分的抑制作用可能發生在焊盤開口的上部，有助於減少填充材料(如銅)的過度負擔，避免焊盤開口"關閉"。
平整劑可用於改善填充性能，降低表面粗糙度，並防止銅在該焊盤開口的上部沉積。平整劑可以以較小的濃度存在，例如，在大約1ppm和大約100ppm的範圍內。平整劑可以是，例如，3-巰基-1-丙磺酸(3-mercapto-1-propanesulfonate)，(3-磺丙基)二硫化物((3-sulfopropyl) disulfide)，或3,3-硫代雙(1-丙磺酸酯)(3,3-thiobis(1-propanesulfonate))。
在一些實施例中，中心電源墊301a可以包括一底部部分和一頂部部分。該底部部分可以形成在該焊盤開口的下部。該頂部部分可以形成在該頂部部分上，並完全填充在該焊盤開口處。該底部部份可以包括鎳。該頂端部分可以包括鈀、鈷或其組合。
在一些實施例中，設置中心電源墊301a的第一電路層103a的製作技術可以是聚合材料，例如聚苯並噁唑(polybenzoxazole)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene)、味之素堆積膜(ajinomoto buildup film)、阻焊膜(solder resist film)或類似材料。該聚合物材料(例如，聚醯亞胺)可能具有許多有吸引力的特性，例如能夠填充高長寬比的開口，相對較低的介電常數(大約3.2)，簡單的沉積製程，減少底層的尖銳特徵或步驟，以及固化後的高溫耐受性。此外，一些光敏聚合材料(如光敏聚醯亞胺)可具有上述所有特性，並可像光阻劑遮罩一樣進行圖案化，在圖案化和蝕刻後，可留在光敏聚合材料沉積的表面上，做為鈍化層的一部分。
複數個邊緣電源墊303a、複數個輔助電源墊305a、複數個輔助電源墊305a和複數個中心資料墊307a可與中心電源墊301a同時形成，此處不再重複描述。
在一些實施例中，複數個中心電源墊301a可做為連接部件，將半導體元件1A與外部元件電性連接。
參照圖5，在一些實施例中，在第一電路層103a和中心電源墊301a之間可以形成種子層SL。種子層SL可以具有U形的剖面輪廓。種子層SL可以包括，例如，銅。
圖6以示意性俯視圖形式，例示本揭露一實施例之一中間半導體元件。圖7和圖8分別是沿圖6中A-A'和B-B'線拍攝的剖面示意圖。
參照圖1和圖6至圖8，在步驟S13，複數個中心電源通孔401a可在複數個中心電源墊301a上形成，複數個邊緣電源通孔403a可在複數個邊緣電源墊303a上形成，複數個輔助通孔405a可在複數個輔助電源墊305a上形成，複數個中心資料通孔407a可在複數個中心資料墊307a上形成。
參照圖6至圖8，可在第一電路層103a上形成下層鈍化層105a。在一些實施例中，下層鈍化層105a可包括聚苯並噁唑、聚醯亞胺、苯並環丁烯、味之素積層膜、阻焊膜等，或其組合。製作技術是聚合物材料的下層鈍化層105a可能具有許多有吸引力的特性，例如能夠填充高長寬比的開口，相對較低的介電常數(約3.2)，簡單的沉積製程，減少底層的尖銳特徵或步驟，以及固化後的高溫耐受性。在其他一些實施例中，下層鈍化層105a可以是介電層。該介電層可以包括氮化物(如氮化矽)，氧化物(如氧化矽)，氧氮化物(oxynitride，如氮氧化矽(silicon oxynitride)，氧化氮化矽(silicon nitride oxide))，磷矽酸鹽玻璃(phosphosilicate glass)，硼矽酸鹽玻璃(borosilicate glass)，摻硼磷矽酸鹽玻璃(boron-doped phosphosilicate glass)，或類似物，或其組合。在一些實施例中，下層鈍化層105a可以被指定為第一電路層103a的層間介電層和/或金屬間介電層的一部分。
應當理解，在本揭露的描述中，氮氧化矽是指含有矽、氮和氧的物質，其中氧的比例大於氮的比例。氧化氮化矽是指一種含有矽、氧和氮的物質，其中氮的比例大於氧的比例。
在一些實施例中，下層鈍化層105a的製作技術可以是例如旋塗、層壓(lamination)、或沉積等。該沉積可以包括化學氣相沉積，如電漿增強化學氣相沉積。該電漿增強化學氣相沉積的處理溫度可在大約350℃和大約450℃的範圍內。電漿增強化學氣相沉積的處理壓力可在大約2.0托和大約2.8托的範圍內。電漿增強化學氣相沉積的處理持續時間可在大約8秒和大約12秒的範圍內。
在一些實施例中，可沿下層鈍化層105a形成複數個通孔(為清晰起見未顯示)，以曝露複數個中心電源墊301a、複數個邊緣電源墊303a、複數個輔助電源墊305a和複數個中心資料墊307a。在一些實施例中，該複數個通孔的側壁可以是實質上垂直的。在一些實施例中，該複數個通孔的側壁可以是錐形的。應當理解，在本揭露的描述中，如果存在一個垂直平面，而一表面與該平面的偏差不超過該表面的均方根粗糙度的三倍，則該表面是 "實質上垂直"的。
可以形成一種導電材料來填充該複數個通孔。例如，導電材料可以是鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(如碳化鉭、碳化鈦、碳化鉭鎂)、金屬氮化物(如氮化鈦)、過渡金屬鋁化物，或其組合。可以進行平面化處理，如化學機械拋光，以去除多餘的材料，為後續製程步驟提供一個實質上平整的表面，並同時形成複數個中心電源通孔401a、複數個邊緣電源通孔403a、複數個輔助通孔405a和複數個中心資料通孔407a。
複數個中心電源通孔401a可與複數個中心電源墊301a電性耦合。複數個邊緣電源通孔403a可與複數個邊緣電源墊303a電性耦合。複數個輔助通孔405a可與複數個輔助電源墊305a電性耦合。複數個中心資料通孔407a可與複數個中心資料墊307a電性耦合。
在一些實施例中，在上述通孔和焊盤之間可以形成複數個阻隔層(為清晰起見未顯示)。例如，在中心電源墊301a和中心電源通孔401a之間可以形成阻隔層。該阻隔層可以包括氟化鋁。由於氟化鋁的飽和結合特性，它是穩定的且可以防止底層焊盤被各種半導體製程腐蝕，特別是包括氟離子的製程。阻隔層的製作技術可以是濺鍍製程。該濺鍍製程的來源可以包括鋁和六氟化硫或氟。六氟化硫或氟可在電漿中分解，並提供氟化的來源(如氟離子和氟化物自由基)，與沉積的薄膜發生反應。
在一些實施例中，該阻隔層可更包括氧化鋅，以增加該阻隔層的電性能。在一些實施例中，氧化鋅的含量可以大於氟化鋁的含量。在一些實施例中，濺鍍製程的濺鍍源可以包括氧化鋅和氟化鋁。氧化鋅的濺鍍電源和氟化鋁的濺鍍電源的比例可以是大約100W：75W。
圖9以示意性俯視圖形式，例示本揭露一實施例之一中間半導體元件。圖10和圖11分別是沿圖9中A-A'和B-B'線拍攝的剖面示意圖。圖12是例示本揭露一實施例之一中間半導體元件的俯視特寫示意圖。
參照圖1和圖9至圖12，在步驟S15，可形成複數個重佈電源圖案510a，以電性耦合到複數個中心電源通孔401a、複數個邊緣電源通孔403a和複數個輔助通孔405a，並且可形成複數個重佈資料圖案520a，以電性耦合到複數個中心資料通孔407a。
為了簡明、清晰和描述方便，只描述了一個重佈電源圖案510a和一個重佈資料圖案520a。
參照圖9至圖11，重佈電源圖案510a可包括重佈中心電源墊511a、重佈邊緣電源墊513a和重佈連接線515a。重佈中心電源墊511a可以形成在下層鈍化層105a上，在形貌上與中心電源通孔401a對齊並接觸。重佈中心電源墊511a可以通過中心電源通孔401a與中心電源墊301a電性耦合。在一些實施例中，重佈中心電源墊511a可以形成延伸至下層鈍化層105a，並且可以直接接觸中心電源墊301a，而中心電源通孔401a被省略。
重佈邊緣電源墊513a可以形成在下層鈍化層105a上，在形貌上與邊緣電源通孔403a對齊並接觸。重佈邊緣電源墊513a可以通過邊緣電源通孔403a與邊緣電源墊303a電性耦合。在一些實施例中，重佈邊緣電源墊513a可形成延伸至下層鈍化層105a，並可直接接觸邊緣電源墊303a，而邊緣電源通孔403a被省略。重佈邊緣電源墊513a可用於佈線(wiring)或凸塊(bumping)，以將半導體元件1A電性耦合到外部元件。
重佈連接線515a可以形成在下層鈍化層105a上並與輔助通孔405a接觸。重佈連接線515a可通過輔助通孔405a與輔助電源墊305a電性耦合。重佈連接線515a可以連接重佈中心電源墊511a和重佈邊緣電源墊513a。在一些實施例中，重佈連接線515a可以是線狀的，並且可以將重佈中心電源墊511a從中心區域CR重新路由(re-route)到邊緣區域ER以電性耦合到重佈邊緣電源墊513a。在一些實施例中，重佈連接線515a可以連接中心區域CR上方的兩個相鄰的重佈中心電源墊511a。
參照圖9至圖11，重佈資料圖案520a可包括重佈中心資料墊521a、重佈邊緣資料墊523a和重佈資料線525a。重佈中心資料墊521a可以形成在下層鈍化層105a上，在形貌上與中心資料通孔407a對齊並接觸。重佈中心資料墊521a可通過中心資料通孔407a與中心資料墊307a電性耦合。在一些實施例中，重佈中心資料墊521a可形成延伸至下層鈍化層105a，並可直接接觸中心資料墊307a，而中心資料通孔407a被省略。
重佈邊緣資料墊523a可以形成在下層鈍化層105a上和邊緣區域ER上方。重佈邊緣資料墊523a可用於佈線或凸塊，以將半導體元件1A電性耦合到外部元件。應當理解的是，沒有通孔直接接觸重佈邊緣資料墊523a。
重佈資料線525a可以形成在下層鈍化層105a上。重佈資料線525a可以連接重佈中心資料墊521a和重佈邊緣資料墊523a。在一些實施例中，重佈資料線525a可以是線狀的，並且可以將重佈中心資料墊521a從中心區域CR重新路由到邊緣區域ER以電性耦合到重佈邊緣資料墊523a。應當理解的是，沒有通孔直接接觸重佈資料線525a。
參照圖9至圖11，重佈電源圖案510a可被做為電源線。例如，在俯視圖下，位於第一基底101a的左上角的重佈電源圖案510a可以電性耦合到外部電源，而位於第一基底101a的右上角的重佈電源圖案510a可以接地。對於另一個例子，位於第一基底101a的底部的重佈電源圖案510a可以電性耦合到外部電源，並且位於第一基底101a的中間的重佈電源圖案510a可以接地。在一些實施例中，重佈資料圖案520a可被做為資料線。在一些實施例中，重佈連接線515a的寬度W1可以大於重佈資料線525a的寬度W2。重佈電源圖案510a和重佈資料圖案520a可以重新路由中心電源墊301a和中心資料墊307a，以獲得更多的空間用於佈線或凸塊，並防止中心電源墊301a和中心資料墊307a受到佈線或凸塊的應力的影響。
參照圖9至圖11，可在下層鈍化層105a上形成上層鈍化層107a。重佈電源圖案510a和重佈資料圖案520a可以形成在上層鈍化層107a中。上層鈍化層107a可以包括聚苯並噁唑、聚醯亞胺、苯並環丁烯、味之素堆積膜、阻焊膜等，或其組合。製作技術是聚合物材料的上層鈍化層107a可能具有許多有吸引力的特性，例如能夠填充高長寬比的開口，相對較低的介電常數(約3.2)，簡單的沉積製程，減少底層的尖銳特徵或步驟，以及固化後的高溫耐受性。在其他一些實施例中，上層鈍化層107a可以是介電層。該介電層可以包括氮化物(如氮化矽)，氧化物(如氧化矽)，氧氮化物(如氧氮化矽，氧化氮化矽)，磷矽酸鹽玻璃，硼矽酸鹽玻璃，摻硼磷矽酸鹽玻璃，或類似物，或其組合。
在一些實施例中，重佈電源圖案510a和重佈資料圖案520a的形成可以包括使用任何適合的方法(例如，旋塗技術、濺鍍等)來形成一個或複數個絕緣層(即上層鈍化層107a)，並在該絕緣層中形成導電特徵。該導電特徵的形成可以包括對絕緣層進行圖案化(例如，使用光學微影和/或蝕刻製程)，並在圖案化的絕緣層中形成導電特徵(例如，通過沉積種子層，使用遮罩層來定義導電特徵的形狀，並使用無電/電化學電鍍製程）。
在一些實施例中，可在下層鈍化層105a上形成導電毯層(為清晰起見未顯示)。光阻劑層(為清晰起見未示出)可被沉積在該導電毯層上，並隨後被圖案化以曝露出要形成重佈電源圖案510a和重佈資料圖案520a的區域。導電材料可以形成在該區域中，以形成重佈電源圖案510a和重佈資料圖案520a。在一些實施例中，重佈電源圖案510a和重佈資料圖案520a的製作技術可例如是鎢、鈦、錫、鎳、銅、金、鋁、鉑、鈷或其組合。
參照圖9至圖11，第一基底101a、第一電路層103a、下層鈍化層105a、上層鈍化層107a、複數個中心電源墊301a、複數個邊緣電源墊303a、複數個輔助電源墊305a、複數個中心資料墊307a、複數個中心電源通孔401a、複數個邊緣電源通孔403a、複數個輔助通孔405a、複數個中心資料通孔407a、複數個重佈電源圖案510a和複數個重佈資料圖案520a共同構成第一半導體晶片100a。
參照圖12，在一些實施例中，上層鈍化層107a可以是多層結構。例如，上層鈍化層107a可以包括底層107a-1和頂層107a-3。底層107a-1可以形成在下層鈍化層105a上，並且製作技術可以是氮化物(如氮化矽)、氧化物(如氧化矽)、氧氮化物(如氧氮化矽、氧化氮化矽)、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻硼磷矽酸鹽玻璃，或類似物，或其組合。頂層107a-3可以形成在底層107a-1上，並且製作技術可以是聚苯並噁唑、聚醯亞胺、苯並環丁烯、味之素堆積膜、阻焊膜、類似物或其組合。重佈電源圖案510a和重佈資料圖案520a可沿底層107a-1和頂層107a-3形成。
通常，當邊緣電源通孔403a和輔助通孔405a不存在時，通過重佈邊緣電源通孔513a、重佈連接線515a和重佈中心電源通孔511a對中心電源墊301的電源輸送可能瞬間不夠。電源輸送的不足是由寄生電感、寄生電容以及由重佈電源圖案510a的額外輸送路徑引起的額外電阻造成的。
相反地，在本揭露中，邊緣電源通孔403a和輔助通孔405a的存在可提供替代路徑，以將電源輸送到與中心電源墊301a電性耦合的導電特徵(例如，邊緣電源墊303a和輔助電源墊305a)。因此，電源輸送不足的影響可以得到緩解。因此，半導體元件1A的性能可以得到改善。
圖13以示意性剖面圖，例示本揭露一些實施例之該半導體元件1A的部分製備流程。
參照圖1和13，在步驟S17，可通過第一附著層803將封裝基底807附著到第一基底101a上，可在封裝基底807下方形成複數個導體813，複數個導線809可將複數個重佈電源圖案510a和複數個重佈資料圖案520a(未示出)電性耦合到封裝基底807中的相應導電線811，並且可在封裝基底807上方形成封裝層815。
參照圖13，第一附著層803可以是晶片附著膜、銀膠或類似物。在一些實施例中，第一附著層803可更包括金、銀、氧化鋁或氮化硼顆粒。在一些實施例中，將第一半導體晶片100a附著到封裝基底807上可以包括以下製程：在第一基底101a下面可以形成一黏合材料層。該黏合材料層可以包括可流動的材料。帶有該黏合材料層的第一半導體晶片100a可以被黏合到封裝基底807上。此後，可隨後執行固化製程來使黏合材料層可被交聯(cross-linked)和固化以形成第一附著層803。
參照圖13，複數個導體813可以包括具有低電阻率的導電材料，例如錫、鉛、銀、銅、鎳、鉍或其合金。複數個導線809可以被製作以將重佈邊緣電源墊513a和重佈邊緣資料墊523a分別與封裝基底807中的相應導電線811電性耦合。複數個導線809的製作技術可是例如金。複數個導線809的製作技術可以是藉由使用超音波接合(bonding)、熱聲結合或熱壓結合的球形接合製程(ball–wedge process)或楔形接合製程(wedge–wedge process)。
參照圖13，封裝層815可以在封裝基底807上形成，以覆蓋第一半導體晶片100a和複數個導線809。封裝層815的製作技術可以是一成型化合物，如聚苯並噁唑、聚醯亞胺、苯並環丁烯、環氧樹脂層壓物(epoxy laminate)或二氟化銨(ammonium bifluoride)。封裝層815的製作技術可以是通過壓縮成型、轉移成型、液體封裝劑成型等方式。例如，可將該成型化合物以液體形式分布。隨後，執行固化製程以固化該成型化合物。該成型化合物的形成可以溢出第一半導體晶片100a，使該成型化合物覆蓋第一半導體晶片100a。可採用例如機械研磨、化學機械拋光或其他回蝕技術的平面化製程，以去除該成型化合物的多餘部分，並提供一實質上平整的表面。
圖14至16以示意性剖面圖形式，分別例示本揭露一些實施例之一半導體元件1B、1C和1D。
參照圖14，半導體元件1B可以具有與圖13中所示相似的結構。圖14中與圖13中相同或相似的元件已被標記為類似的參考符號，重複的描述已被省略。
半導體元件1B可以包括複數個緩衝層801。為了簡明、清晰和方便描述，只描述一個緩衝層801。
緩衝層801可以經設置在第一電路層103a中，並在形貌上與重佈邊緣電源墊513a對齊。緩衝層801的垂直水平可以低於邊緣電源墊303a的垂直水平。在一些實施例中，緩衝層801和邊緣電源墊303a可以不互相接觸。緩衝層801可用於吸收和重新分布集中在底層的應力，這些應力是由熱膨脹不匹配產生的剪切應力和由於佈線製程或碰撞製程產生的法向應力造成的。緩衝層801的製作技術可例如是熱膨脹係數小於約20ppm/°C和楊氏模量小於約15GPa的材料。具體來說，緩衝層801的製作技術是包括聚醯亞胺或環氧樹脂材料的材料。緩衝層801的厚度可在大約500奈米和大約10000奈米的範圍內。優選地，緩衝層801的厚度可在大約1000奈米和大約5000奈米的範圍內。緩衝層801可做為緩衝物以減少凸塊製程或佈線製程的應力；因此，上層鈍化層107a、下層鈍化層105a或第一電路層103a的上部的分層(delamination)可被減少。
參照圖15，半導體元件1C可以具有與圖13中所示類似的結構。圖15中與圖13中相同或相似的元件已被標記為類似的參考符號，重複的描述已被省略。
半導體元件1C可以包括第二半導體晶片100b。第二半導體晶片100b可以經設置在第一半導體晶片100a的旁邊。第二半導體晶片100b可以通過第一附著層803附著在封裝基底807上。複數個導線809可將第二半導體晶片100b與封裝基底807中的相應導電線811電性耦合。封裝層815可覆蓋第一半導體晶片100a和第二半導體晶片100b。
在一些實施例中，第二半導體晶片100b可具有與第一半導體晶片100a的佈局不同的佈局。在一些實施例中，第二半導體晶片100b可以具有與第一半導體晶片100a的佈局相同的佈局。在一些實施例中，第一半導體晶片100a和第二半導體晶片100b可以提供相同的功能，但不限於此。
在一些實施例中，第二半導體晶片100b可以包括第二基底101b、第二電路層103b、下層鈍化層105b、上層鈍化層107b、複數個中心電源墊301b、複數個邊緣電源墊303b、複數個輔助電源墊305b。複數個中心資料墊307b，複數個中心電源通孔401b，複數個邊緣電源通孔403b，複數個輔助通孔405b，以及分別包括重佈中心電源墊511b、重佈邊緣電源墊513b和重佈連接線515b的重佈電源圖案510b。第二半導體晶片100b的上述特徵可以具有與第一半導體晶片100a的相應特徵類似的結構，在此不重複描述。
參照圖16，半導體元件1D可以具有與圖13中所示類似的結構。圖16中與圖13中相同或相似的元件已被標記為類似的參考符號，重複的描述已被省略。
半導體元件1D可包括第二半導體晶片100b。第二半導體晶片100b可以經設置在第一半導體晶片100a的上方。第二半導體晶片100b可以通過第二附著層805附著在第一半導體晶片100a上。第二附著層805可以是晶片附著膜、銀膠或類似物。在一些實施例中，第二附著層805可以更包括金、銀、氧化鋁或氮化硼顆粒。在一些實施例中，將第二半導體晶片100b附著到第一半導體晶片100a可以包括以下製程：在第二半導體晶片100b下面可以形成一黏合材料層。該黏合材料層可以包括可流動的材料。帶有黏合材料層的第二半導體晶片100b可以被黏合到第一半導體晶片100a上。此後，可隨後執行固化製程來使黏合材料層可被交聯和固化以形成第二附著層805。
複數個導線809可將第二半導體晶片100b與封裝基底807中的相應導電線811電性耦合。封裝層815可覆蓋第一半導體晶片100a和第二半導體晶片100b。第二半導體晶片100b可具有與圖15所示類似的結構，其描述在此不再重複。
在一些實施例中，第一半導體晶片100a的第一基底101a和/或第二半導體晶片100b的第二基底101b可以被減薄。這種減薄允許改善熱耗散，並提供較低的封裝輪廓。
本揭露一實施例提供一種半導體元件，包括：一第一基底，包括一中心區域和遠離該中心區域的一邊緣區域；一第一電路層，設置在該第一基底上；一中心電源墊，設置在該第一電路層中和該中心區域上方；一邊緣電源墊，設置在該第一電路層中、該邊緣區域上，並與該中心電源墊電性耦合；一重佈電源圖案，設置在該第一電路層上，並與該中心電源墊電性耦合，以及一邊緣電源通孔，設置在該邊緣電源墊和該重佈電源圖案之間，並將該邊緣電源墊和該重佈電源圖案電性耦合。該第一基底、該中心電源墊、該邊緣電源墊、該重佈電源圖案和該邊緣電源通孔共同構成一第一半導體晶片。
本揭露另一實施例提供一種半導體元件的製備方法，包括：提供包括一中心區域和遠離該中心區域的一邊緣區域的一第一基底，在該第一基底上形成該第一電路層，在該第一電路層中和該中心區域上方形成一中心電源墊，在該第一電路層中、該邊緣區域上方形成一邊緣電源墊並與該中心電源墊電性耦合，在該邊緣電源墊上形成一邊緣電源通孔，以及在該邊緣電源通孔上形成一重佈電源圖案並與該中心電源墊電性耦合。該第一基底、該中心電源墊、該邊緣電源墊、該重佈電源圖案和該邊緣電源通孔共同構成一第一半導體晶片。
由於本揭露的半導體元件的設計，電源輸送的不足可以通過邊緣電源通孔403a和次要通孔405a來緩解。因此，半導體元件1A的性能可以得到改善。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包括於本申請案之申請專利範圍內。
1A:半導體元件 1B:半導體元件 1C:半導體元件 1D:半導體元件 10:製備方法 100a:第一半導體晶片 100b:第二半導體晶片 101a:第一基底 101b:第二基底 103a:第一電路層 103b:第二電路層 105a:下層鈍化層 105b:下層鈍化層 107a:上層鈍化層 107a-1:底層 107a-3:頂層 107b:上層鈍化層 301a:中心電源墊 301b:中心電源墊 303a:邊緣電源墊 303b:邊緣電源墊 305a:輔助電源墊 305b:輔助電源墊 307a:中心資料墊 307b:中心資料墊 401a:中心電源通孔 401b:中心電源通孔 403a:邊緣電源通孔 403b:邊緣電源通孔 405a:輔助通孔 405b:輔助通孔 407a:中心資料通孔 510a:重佈電源圖案 510b:重佈電源圖案 511a:重佈中心電源墊 511b:重佈中心電源墊 513a:重佈邊緣電源墊 513b:重佈邊緣電源墊 515a:重佈連接線 515b:重佈連接線 520a:重佈資料圖案 521a:重佈中心資料墊 523a:重佈邊緣資料墊 525a:重佈資料線 801:緩衝層 803:第一附著層 805:第二附著層 807:封裝基底 809:導線 811:導電線 813:導體 815:封裝層 CR:中心區域 ER:邊緣區域 S11:步驟 S11:步驟 S13:步驟 S17:步驟 SL:種子層 W1:寬度 W2:寬度 X:維度 Y:維度 Z:維度
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。
圖1例示本揭露一實施例之一種半導體元件的製備方法的流程圖。 圖2例示本揭露一實施例之一中間半導體的俯視示意圖。 圖3例示本揭露一些實施例沿圖2中A-A'線拍攝的剖面示意圖。 圖4例示本揭露一些實施例沿圖2中B-B'線拍攝的剖面示意圖。 圖5例示本揭露一些實施例之一中間半導體元件的剖面特寫示意圖。 圖6例示本揭露一些實施例之一中間半導體元件的俯視示意圖。 圖7例示本揭露一些實施例沿圖6中A-A'線拍攝的剖面示意圖。 圖8例示本揭露一些實施例沿圖6中B-B'線拍攝的剖面示意圖。 圖9例示本揭露一些實施例之一中間半導體元件的俯視示意圖。 圖10例示本揭露一些實施例沿圖9中A-A'線拍攝的剖面示意圖。 圖11例示本揭露一些實施例沿圖9中B-B'線拍攝的剖面示意圖。 圖12例示本揭露一些實施例之一中間半導體元件的俯視特寫示意圖。 圖13例示本揭露一些實施例之該半導體元件的部分製備流程中的剖面示意圖。 圖14例示本揭露一些實施例之一半導體元件的剖面示意圖。 圖15例示本揭露一些實施例之一半導體元件的剖面示意圖。 圖16例示本揭露一些實施例之一半導體元件的剖面示意圖。
101a:第一基底
103a:第一電路層
105a:下層鈍化層
107a:上層鈍化層
301a:中心電源墊
303a:邊緣電源墊
305a:輔助電源墊
401a:中心電源通孔
403a:邊緣電源通孔
405a:輔助通孔
407a:中心資料通孔
510a:重佈電源圖案
511a:重佈中心電源墊
513a:重佈邊緣電源墊
515a:重佈連接線
520a:重佈資料圖案
521a:重佈中心資料墊
523a:重佈邊緣資料墊
525a:重佈資料線
CR:中心區域
ER:邊緣區域
W1:寬度
W2:寬度
X:維度
Y:維度

Claims (20)

  1. 一種半導體元件，包括： 一第一基底，包括一中心區域和遠離該中心區域的一邊緣區域； 一第一電路層，設置在該第一基底上； 一中心電源墊，設置在該第一電路層中和該中心區域上方； 一邊緣電源墊，設置在該第一電路層中和該邊緣區域上方，並與該中心電源墊電性耦合； 一重佈電源圖案，設置在該第一電路層上方並與該中心電源墊電性耦合；以及 一邊緣電源通孔，設置在該邊緣電源墊和該重佈電源圖案之間，並將該邊緣電源墊和該重佈電源圖案電連接； 其中該第一基底、該中心電源墊、該邊緣電源墊、該重佈電源圖案和該邊緣電源通孔共同構成一第一半導體晶片。
  2. 如請求項1所述的半導體元件，其中該重佈電源圖案包括： 一重佈中心電源墊，設置在該第一電路層上方，在形貌上(topographically)與該中心電源墊對齊，並與該中心電源墊電性耦合； 一重佈邊緣電源墊，設置在該第一電路層上方，在形貌上與該邊緣電源墊對齊，並通過該邊緣電源通孔與該邊緣電源墊電性耦合；以及 一重佈連接線，連接該重佈中心電源墊和該重佈邊緣電源墊。
  3. 如請求項2所述的半導體元件，更包括一輔助電源墊和一輔助通孔； 其中該輔助電源墊經設置在該第一電路層中，設置在該中心電源墊和該邊緣電源墊之間，並與該中心電源墊電性耦合； 其中該輔助通孔將該重佈連接線和該輔助電源墊電連接。
  4. 如請求項3所述的半導體元件，更包括設置在該第一電路層上的一下層鈍化層； 其中該邊緣電源通孔和該輔助通孔經設置在該下層鈍化層中。
  5. 如請求項4所述的半導體元件，更包括設置在該下層鈍化層上的一上層鈍化層； 其中該重佈電源圖案經設置在該上層鈍化層中。
  6. 如請求項5所述的半導體元件，更包括設置在該第一基底下方的一封裝基底。
  7. 如請求項6所述的半導體元件，更包括設置在該封裝基底和該第一基底之間並連接該封裝基底和該第一基底的一第一附著層。
  8. 如請求項7所述的半導體元件，更包括一導線，將該重佈邊緣電源墊與該封裝基底中的一導電線電連接。
  9. 如請求項7所述的半導體元件，其中該重佈邊緣電源墊與一外部電源電性耦合。
  10. 如請求項7所述的半導體元件，更包括一中心資料墊和一重佈資料圖案； 其中該中心資料墊經設置在該第一電路層中和該中心區域上方； 其中該重佈資料圖案包括： 一重佈中心資料墊，設置在下層鈍化層上，在形貌上與該中心資料墊對齊，並通過一中心資料通孔與該中心資料墊電性耦合； 一重佈邊緣資料墊，設置在該下層鈍化層上和該邊緣區域上方；以及 一重佈資料線，將該重佈中心資料墊和該重佈邊緣資料墊連接。
  11. 如請求項10所述的半導體元件，其中該重佈連接線的寬度大於該重佈資料線的寬度。
  12. 如請求項7所述的半導體元件，更包括設置在該第一電路層中並與該邊緣電源墊在形貌上對齊的一緩衝層。
  13. 如請求項7所述的半導體元件，更包括設置在該第一半導體晶片旁邊的一第二半導體晶片； 其中該第二半導體晶片通過該第一附著層附著在該封裝基底上。
  14. 如請求項7所述的半導體元件，更包括堆疊在該第一半導體晶片上的一第二半導體晶片，其間具有一第二附著層。
  15. 如請求項14所述的半導體元件，其中該第二半導體晶片的佈局(layout)和該第一半導體晶片的佈局實質上相同。
  16. 一種半導體元件的製備方法，包括: 提供一第一基底，包括一中心區域和遠離該中心區域的一邊緣區域； 在該第一基底上形成一第一電路層； 在該第一電路層中和該中心區域上方形成一中心電源墊； 在該第一電路層中和該邊緣區域上方形成一邊緣電源墊，並與該中心電源墊電性耦合； 在該邊緣電源墊上形成一邊緣電源通孔；以及 在該邊緣電源通孔上形成一重佈電源圖案，並與該中心電源墊電性耦合； 其中該第一基底、該中心電源墊、該邊緣電源墊、該重佈電源圖案和該邊緣電源通孔共同構成一第一半導體晶片。
  17. 如請求項16所述的製備方法，其中該重佈電源圖案包括： 在該第一電路層上方的一重佈中心電源墊，在形貌上與該中心電源墊對齊，並與該中心電源墊電性耦合； 在該第一電路層上方的一重佈邊緣電源墊，在形貌上與該邊緣電源墊對齊，並通過該邊緣電源通孔與該邊緣電源墊電性耦合；以及 連接該重佈中心電源墊和該重佈邊緣電源墊的一重佈連接線。
  18. 如請求項17所述的製備方法，更包括通過一第一附著層將該第一半導體晶片附著到一封裝基底。
  19. 如請求項18所述的製備方法，更包括形成一導線，將該重佈邊緣電源墊和該封裝基底中的一導電線電性耦合。
  20. 如請求項19所述的製備方法，更包括在該封裝基底下方形成一導體，並在該封裝基底中電連接該導電線。
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