TW202236571A - 半導體元件與其製作方法 - Google Patents
半導體元件與其製作方法 Download PDFInfo
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- TW202236571A TW202236571A TW110122824A TW110122824A TW202236571A TW 202236571 A TW202236571 A TW 202236571A TW 110122824 A TW110122824 A TW 110122824A TW 110122824 A TW110122824 A TW 110122824A TW 202236571 A TW202236571 A TW 202236571A
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Abstract
一種半導體元件包含:導電特徵、設置於導電特徵上方的介電層、以及延伸穿透介電層的接觸特徵。接觸特徵具有上部與下部。上部係以間隔層從介電層分離。下部係電性地耦接至導電特徵並且與介電層接觸。
Description
半導體工業在追求更高的元件密度且更低的成本之方面上已取得了顯著的進步。在半導體元件發展的過程中,功能密度(例如:晶片單位面積之相互連接的導電特徵數量)通常增加了,而幾何尺寸卻減小了。這種尺寸微縮的過程通常係藉由提高生產效率且降低相關成本來提供效益。然而,增加的功能密度增加了半導體元件的複雜性,例如:藉由減小相鄰導電特徵之間的距離。當相鄰導電特徵之間的距離減小時,可能難以形成用於每一導電特徵的接觸特徵。例如:接觸特徵之間的距離通常根據相鄰導電特徵之間的距離減小而減小,此可能顯著地增加接觸特徵短路的可能性。
因此,有必要改善接觸特徵且改善其形成的方法。
以下揭露提供許多不同實施例或例示,以實施申請標的之不同特徵。以下敘述之成份和排列方式的特定例示是為了簡化本揭露。這些當然僅是做為例示,其目的不在構成限制。舉例而言,第一特徵形成在第二特徵之上或上方的製程描述包含第一特徵和第二特徵有直接接觸的實施例,也包含有其他特徵形成在第一特徵和第二特徵之間,以致第一特徵和第二特徵沒有直接接觸的實施例。而本文使用的是,第一特徵形成在第二特徵之上或上方代表第一特徵和第二特徵為直接接觸。除此之外,本揭露在各種例示中重覆參照數值及/或字母。此重覆的目的是為了使說明簡化且清晰易懂,並不表示各種討論的實施例及/或配置之間有關係。
再者,空間相對性用語,例如「下方(beneath)」、「在…之下(below)」、「低於(lower)」、「在…之上(above)」、「高於(upper)」等,是為了易於描述圖式中所繪示的元素或特徵和其他元素或特徵的關係。空間相對性用語除了圖式中所描繪的方向外,還包含裝置在使用或操作時的不同方向。裝置可以其他方式定向(旋轉90度或在其他方向),而本文所用的空間相對性描述也可以據此解讀。
本揭露提供了包含至少一接觸特徵之半導體元件的各種實施例,此接觸特徵係藉由孔洞所形成。使用此孔洞,可以超過(例如:更小) 圖案化製程(例如:光學微影製程) 的極限的尺寸來特徵化接觸特徵。如此一來,當形成分別用於以相對較小的距離將彼此側向地間隔開之導電特徵的接觸特徵時,仍可成功地形成接觸特徵而沒有任何問題(例如:使導電特徵短路)。例如:可藉由調整用於沉積介電層的條件來於介電層中形成孔洞。可藉由在具有相對較大尺寸的凹陷上,刻意地形成介電層的突出物來形成孔洞,這可能會受到某些圖案化製程的限制。據此,孔洞可以大致上小於凹陷之尺寸的尺寸來特徵化。接觸孔可與孔洞自對準(self-aligned)地形成,其亦可繼承大致上與孔洞的尺寸相似的尺寸。據此,藉由以導電材料填充接觸孔,可形成以超過圖案化製程的極限的尺寸來特徵化的接觸特徵。
圖1是示出根據本揭露之各方面所繪示的用於製造半導體元件200的方法100的流程圖。應注意的是,方法100僅為例示,並且不旨在限製本揭露。據此,應理解的是,可在圖1的方法100之前、期間與之後提供附加的操作,且此處可僅簡要地描述一些其他的操作。在一些實施例中,方法100的操作可與如圖1至圖7 所示的在各種製造階段之半導體元件的剖面視圖相關,其將於後進一步詳細討論。
現請參照圖1,方法100開始於操作102,在操作102中,提供了被第一介電層所覆蓋的導電特徵。方法100進行到操作104,在操作104中,使第一介電層的一部分凹陷。方法100進行到操作106,在操作106中,藉由以第二介電層填充凹陷來形成孔洞。方法100進行到操作108,在操作108中,藉由蝕刻第一介電層與第二介電層穿透孔洞來形成接觸孔。方法100進行到操作110,在操作110中,藉由以導電材料填充接觸孔來形成接觸特徵。
如以上所述,圖2至圖7係根據圖1之方法100的實施例所示的在製造之各種階段的半導體元件200的示意剖面視圖。半導體元件200可被包含在微處理器、儲存單元及/或其他積體電路(integrated circuit;IC)中。應注意的是,圖1的方法無法產生完整的半導體元件200。可使用互補式金屬氧化物半導體(complementary metal-oxide-semiconductor;CMOS)技術製程來製造半導體元件200。據此,應理解的是,可在圖1的方法100之前、期間與之後提供附加的製程,且此處可僅簡要地描述一些其他的操作。此外,為了能更好地理解本揭露,圖1至圖7係被簡化了。例如:儘管圖式繪示了半導體元件200,然而應理解的是,IC可包含許多其他元件,包含電晶體、電阻、電容、電感、保險絲等。
對應至圖1的操作102,圖2係根據一些實施例的在製造的各種階段中之一者的半導體元件200的剖面視圖,其包含具有至少一導電特徵204的基材202,且導電特徵204係被第一介電層206所覆蓋。儘管在圖2的說明性實施例中的半導體元件200僅包含一個導電特徵204,但應理解的是,圖2的說明性實施例與後續多圖式僅出於說明之目的。因此,半導體元件200可包含任何期望數量的導電特徵,同時維持在本揭露之範圍內。例如:在導電特徵204的每一側上,半導體元件200可包含至少一個大致上與導電特徵204相近的導電特徵。
半導體基材202包含半導體材料的基材,例如:矽。或者,基材202可包含其他元素半導體材料,例如:鍺。基材202亦可包含化合物半導體,如碳化矽、砷化鎵、砷化銦與磷化銦。基材202可包含合金半導體,如矽鍺、碳化矽鍺、磷砷化鎵與磷化銦鎵。在一實施例中,基材202包含磊晶層。例如:基材可具有覆蓋在塊狀(bulk)半導體上的磊晶層。此外,基材202可包含絕緣層上半導體(semiconductor-on-insulator;SOI)結構。例如:基材可包含藉由如氧離子植入矽晶隔離(separation by implanted oxygen;SIMOX)之製程,或如晶圓接合與研磨之其他適合的技術所形成的埋藏氧化物(buried oxide;BOX)層。
在基材202包含半導體材料之上述的實施例中,導電特徵204可為電晶體(例如:金屬氧化物半導體場效應電晶體(metal oxide semiconductor field effect transistor;MOSFET))的源極特徵(例如:源極電極)、汲極特徵(例如:汲極電極)或閘極特徵(例如:閘極電極)。或者,導電特徵204可為設置在源極、汲極或閘極電極上的自對準矽化物(salicide)特徵。藉由自對準(self-aligned)的矽化物(silicide)技術來形成自對準矽化物特徵。
在一些其他實施例中,基材202為形成在各種元件特徵(例如:電晶體的源極、汲極或閘電極)上方的介電材料基材。這樣的介電材料基材202可包含氧化矽、具有介電常數(k值)小於約4.0之相對低介電常數的介電材料、或其組合中至少之一者。在一些實施例中,介電材料基材202係由包含低介電常數介電材料、極低介電常數介電材料、多孔低介電常數介電材料、或其組合的材料所形成。術語「低介電常數」(low-k) 旨在將介電材料的介電常數定義為3.0或更小。術語「極低介電常數」(extreme low-k;ELK) 是指介電常數為2.5或更小,且偏好在1.9與2.5之間。術語「多孔低介電常數」是指介電材料的介電常數為2.0或更小,且偏好1.5或更小。本揭露的一些實施例可採用各式各樣的低介電常數材料,例如:旋塗(spin-on)無機介電質、旋塗有機介電質、多孔介電材料、有機聚合物、有機矽玻璃、FSG(SiOF系列材料)、聚倍半矽氧烷(hydrogen silsesquioxane;HSQ)系列材料、甲基倍半矽氧烷(methyl silsesquioxane;MSQ)系列材料、或多孔有機系列材料。
在基材202係由介電材料所形成的這種實施例中,導電特徵204可為形成於基材202內的水平導電結構、垂直導電結構、或其組合。例如:導電特徵204可為互連結構(例如:水平導電結構)、穿孔結構(例如:垂直導電結構)、或其組合。據此,導電特徵204可電性地耦接至電晶體的元件特徵,例如:設置在層、互連層、或金屬化的層下方之電晶體的源極、汲極或閘極特徵。在這樣的實施例中,導電特徵204可由金屬材料(例如:銅(Cu)、鋁(Al)、鎢(W)等)所形成。
第一介電層為形成來覆蓋各種導電特徵(例如:導電特徵204等) 的介電材料。第一介電層206可包含氧化矽、具有介電常數(k值)小於約4.0之相對低介電常數的介電材料、或其組合中至少之一者。在一些實施例中,介電材料基材202係由包含低介電常數介電材料、極低介電常數介電材料、多孔低介電常數介電材料、或其組合的材料所形成。術語「低介電常數」(low-k) 旨在將介電材料的介電常數定義為3.0或更小。術語「極低介電常數」(extreme low-k;ELK) 是指介電常數為2.5或更小,且偏好在1.9與2.5之間。術語「多孔低介電常數」是指介電材料的介電常數為2.0或更小,且偏好1.5或更小。本揭露的一些實施例可採用各式各樣的低介電常數材料,例如:旋塗(spin-on)無機介電質、旋塗有機介電質、多孔介電材料、有機聚合物、有機矽玻璃、FSG(SiOF系列材料)、聚倍半矽氧烷(hydrogen silsesquioxane;HSQ)系列材料、甲基倍半矽氧烷(methyl silsesquioxane;MSQ)系列材料、或多孔有機系列材料。
對應至圖1的操作104,圖3為半導體元件200的剖面視圖,其中第一介電層206的一部分係被凹陷的(下文稱為「凹陷部分207」)。可使用具有遮罩技術的光學微影與一或多個乾式蝕刻操作,例如:電漿蝕刻或反應式離子蝕刻來形成凹陷部分207。替代地或附加地,可使用一或多個濕式蝕刻操作來形成凹陷部分207。凹陷部分207係形成以與導電特徵204垂直對準。
在一些實施例中,在沿著相對於基材202所設置之第一介電層206的第一方向(例如:Y方向)上,凹陷207可部分地延伸穿透第一介電層206。具體而言,可形成第一介電層206且以厚度T
1將其特徵化,以及凹陷部分207可以深度T
2延伸至第一介電層206中,其中深度T
2大致上小於厚度T
1。例如:厚度T
1可在約150奈米(nm)至約180奈米的範圍內,而深度T
2可在約120奈米至約150奈米的範圍內。在一些實施例中,在與第一方向相交的第二方向(例如:X方向)上,凹陷部分207可以寬度(或剖面長度)W
1來特徵化,如圖3所示。這樣的寬度W
1可與某種圖案化製程(例如:光學微影製程)的臨界尺寸相關聯(例如:藉由其來定義) 以形成凹陷部分207。例如:寬度W
1的範圍可從30奈米到80奈米。凹陷部分207可形成為從第一介電層206的頂表面朝向基材202逐漸地變細。凹陷部分207不必形成為具有實質上較小的尺寸(例如:W
1)。如此一來,可以顯著地降低形成凹陷部分207的成本及/或資源(例如:光學微影製程中的光阻層的數量)。根據一些實施例,凹陷部分207可呈現大於1.5的深寬比(T
2/W
1),以促進孔洞的形成。孔洞的細節將於以下討論。
對應至圖1的操作106,圖4是包含形成在第二介電層208中的孔洞210的半導體元件200的剖面圖。孔洞210係與形成第二介電層208同時形成,其將於以下進一步詳細討論。孔洞210係形成為與導電特徵204垂直地對準。在一些實施例中,孔洞210以沿著X方向的寬度(或橫截面長度)W
2來特徵化,其大致上小於凹陷部分207的寬度W
1。例如:寬度W
2可小於或等於寬度W
1的1/3。在另一個示例中,寬度W
2可小於或等於寬度W
1的1/2。如此一來,孔洞210隨後可用以形成接觸特徵,其繼承了孔洞210的寬度W
2並且與導電特徵204自對準。這樣一來,可進一步地減小這種接觸特徵的臨界尺寸,使其超出光學微影製程的極限。
在一個實施例中,使用適合的沉積製程(例如;化學氣相沉積、物理氣相沉積等) 來形成第二介電層208,其中,調整沉積製程以使得凹陷部分207與沉積速率使得沉積製程將不會完全地填充凹陷部分207,而是將在第二介電層208中形成所需要的孔洞210。作為非限制性的例示,當凹陷部分207的深寬比如以上關於圖3所描述的,且之中沉積有氧化矽(第二介電層208的例示性材料)時,沉積製程可起始於藉由導入如矽烷(SiH
4)與氧(O
2)之類的前驅物至第一介電層206。在一個實施例中,以約100(standard cubic centimeter per minute ;sccm)至約10000sccm之間的流速,如約2000sccm來導入矽烷,同時以約500sccm至約10000sccm之間的流速.如約4000sccm來導入氧氣。此外,可在約200℃至約500℃之間的溫度,如約400℃,以及在約0.1T至約10T之間的壓力,如約3T下進行沉積。
藉由使用這些製程參數,可以相對高的沉積速率來沉積第二介電層208,如在約1奈米/秒至約10奈米/秒之間的沉積速率(例如:約3奈米/秒)。以這樣的沉積速率,以及如以上所述之凹陷部分207的尺寸,可在第二介電層208中形成孔洞210。在一些其他實施例中,第二介電層208可包含任何其他適合的介電材料,如氮化矽、碳化矽、氮氧化矽、多晶矽或其組合,且同時仍在本揭露的範圍內。根據本揭露的各種實施例,第一介電層206與第二介電層208可包含相似或不同的介電材料,只要這二種介電材料分別以不同的蝕刻特性(例如:不同的蝕刻速率的某些蝕刻劑) 來特徵化即可。
對應至圖1的操作108,圖5是之中形成有接觸孔212的半導體元件200的剖面視圖。在一些實施例中,可藉由在第二介電層208(圖4)與第一介電層206上進行蝕刻製程213來形成接觸孔212。蝕刻製程213可為非等向性或方向性蝕刻製程,其中蝕刻劑(例如:粒子、離子、或電漿)可沿著特定方向(例如:Y方向)被引導。如上所述,第一介電層206與第二介電層208可分別以不同的蝕刻速率來特徵化。據此,第二介電層208的一部分 (下文中稱為「間隔層」214)可保持厚度W
3,如圖7所示。間隔層214可沿著第一介電層206之內側壁206S的上部延伸。將如下所述,當以導電材料填充接觸孔212(與凹陷部分207)時,間隔層214可保護在第一介電層206中及/或基材202上的一或多個其他導電特徵避免損壞。
此外,根據各種實施例,當蝕刻第二介電層208時,孔洞210可促進蝕刻製程213的蝕刻劑以移除在孔洞210正下方之第二介電層208的的一部分,以及接著在孔洞210正下方之第一介電層206的一部分也從而形成接觸孔212,而此蝕刻製程213被導引為與孔洞210所延伸之方向大致上平行(例如:Y方向)。因此,接觸孔212可與孔洞210「自對準」(self-aligned),其造成接觸孔212繼承了孔洞210的寬度W
2。不同於現有技術的是,現有技術通常需要額外的成本及/或資源來減少凹陷部分207(關於圖3的討論)的臨界尺寸,接觸孔212可形成以具有大致上小於凹陷部分207(圖3)之寬度W
1或超出光學微影製程極限的尺寸。替代地或附加地,蝕刻製程213可以包含一或多個蝕刻製程,其中每一蝕刻製程具有相似或不同的蝕刻條件,因而產生接觸孔212且蝕刻穿透在孔洞210下方之第一介電層206的部分,如圖6所示。如此,至少導電特徵204之上表面的部分可被暴露出來。
對應至圖1的操作110,圖7是包含接觸特徵216的半導體元件200的剖面視圖。可藉由以導電材料來填充接觸孔212(圖5與圖6),接著進行研磨製程(例如:化學機械性拋光(CMP)製程),來形成接觸特徵216。導電材料可包含如銅(Cu)、鋁(Al)、鎢(W)或其組合的金屬材料。
如在一些實施例中所示,接觸特徵216包含上部2l6U與下部2l6L。上部2l6U係藉由間隔層214從第一介電層206的內側壁206S的上部側向地間隔開來(或被其包圍)。如此一來,上部2l6U可呈現出一寬度(或剖面長度)W
4,其可等於:W
1-2W
3。相反地,藉由孔洞210所形成的下部216L係與第一介電層206的內側壁206S的下部接觸。因此,下部216L可繼承孔洞210的寬度W
2,其約為或小於寬度W
1的1/3。在一些實施例中,寬度W
2可約為或小於寬度W
1的1/2。給定接觸特徵216之上部與下部的不同尺寸,接觸特徵216可包含(或以其他方式來定義)在上部216U與下部216L之相交處的中間邊界216I。在一些實施例中,中間邊界216I可與X方向大致上平行。
藉由使用孔洞210來形成接觸孔212(圖5與圖6),所形成之接觸特徵216之下部216L的臨界尺寸 (例如:寬度W
2)可大致上小於寬度W
1,其有時可能會受到光學微影製程的限制。此外,藉由以間隔物層214來延伸第一介電層206的內側壁206S,可形成彼此相對靠近的多個接觸特徵(其中一些可類似於接觸特徵216),間隔物層214可作為附加的保護層(相對於第一介電層206),以電性地隔離相鄰的接觸特徵。
圖8A與圖8B分別繪示例示性半導體元件800的剖面視圖與俯視圖,此例示性半導體元件800包含如本文所揭露之接觸特徵中的至少一者。如圖8A所示,半導體元件800包含形成在基材801上的二個電晶體802與電晶體804。電晶體802包含閘極特徵(或電極)802G、汲極特徵802D與源極特徵802S;以及在基材801的井803中所形成的電晶體804,包含閘極特徵(或電極)804G、汲極特徵804D與源極特徵804S。在基材801為P型摻雜的示例中,井803可為N型摻雜。因此,電晶體802可為N型電晶體,且電晶體804為P型電晶體。儘管在圖8的說明性實施例中,電晶體802和804被繪示為平面電晶體,然而應理解的是,每一電晶體可包含任何其他類型的電晶體(例如:FinFET、奈米線電晶體或奈米片電晶體)中的一種,且仍在本揭露的範圍內。
在一些情況下,所形成之閘極特徵802G與閘極特徵804G可實質上地靠近彼此。因此,為了在如此實質上相近的閘極特徵之間形成一或多個接觸特徵,例如:接觸特徵806與接觸特徵808,使用本揭露的方法可為有幫助的。例如:儘管接觸特徵806的上部806U與接觸特徵808的上部808U的各自尺寸可能會受到光學微影製程的限制,而實際連接至導電特徵(例如:802S與804D)的接觸特徵806的下部806L與接觸特徵808的上部808L仍可以具有超出(例如:小於)極限尺寸來形成。而且,隨著以間隔層807與間隔層809分開地將上部806U與上部808U從低介電常數介電層805來分離,間隔層807與間隔809可在形成接觸特徵806與接觸特徵808時保護閘極特徵802G與閘極特徵804G不受損壞。
圖8B繪示了半導體元件800之相對應的俯視圖。在一些實施例中,圖8B可為半導體元件800的佈局設計。如圖所示,圖8A中所示的每一特徵可根據圖8B的各自圖案來形成。舉例來說,用以形成閘極特徵802G的圖案可延伸跨越用以形成源極/汲極特徵802S/802D的圖案;用以形成閘極特徵802G的圖案可延伸跨越用以形成源極/汲極特徵802S/802D的圖案,其被用以形成井803的圖案所圍繞;以及用以形成接觸特徵806與接觸特徵808的圖案(例如:圖案850)可與源極特徵802S的部分與汲極特徵804D的部分重疊。應注意的是,當從頂部觀察時,每一接觸特徵806與接觸特徵808可被各自的間隔層(例如:間隔層807與間隔層809)所圍繞。
圖9A與圖9B分別繪示了另一例示性半導體元件900的剖面視圖與俯視圖,此半導體元件900包含如本文所揭露之接觸特徵中的至少一者。如圖9A所示,半導體元件900包含電晶體902與電晶體904二個電晶體。電晶體902包含閘極特徵(或電極)902G、汲極特徵902D與源極特徵902S;電晶體904包含閘極特徵(或電極)904G、汲極特徵904D與源極特徵904S。儘管在圖1的說明性實施例中,電晶體902與電晶體904被繪示為平面電晶體,應理解的是,每一電晶體可包含任何其他類型的電晶體(例如:FinFET、奈米線電晶體或奈米片電晶體)中的一種,且仍在本揭露的範圍內。半導體元件900可包含接觸特徵906與接觸特徵908二個接觸特徵,其分別電性地連接至源極特徵/汲極特徵902S/904D與閘極特徵904G。每一接觸特徵906與接觸特徵908可包含上部與下部。如圖所示,接觸特徵906包含以間隔層907從低介電常數層905分離的上部906U,與電性連接至源極特徵/汲極特徵902S/904D的下部906L;以及接觸特徵908包含以間隔層909從低介電常數層905分離的上部908U,與電性連接至閘極特徵904G的下部908L。
圖9B繪示了半導體元件900之相對應的俯視圖。在一些實施例中,圖9B可為半導體元件900的佈局設計。如圖所示,圖9A中所示的每一特徵可根據圖9B的各自圖案來形成。舉例來說,用以形成閘極特徵902G的圖案可延伸跨越用以形成汲極特徵/源極特徵902D/902S/904D/904S的圖案,以及用以形成其他源極/汲極特徵的另一圖案(例如:圖案920);用以形成閘極特徵904G的圖案可延伸跨越用以形成汲極特徵/源極特徵902D/902S/904D/904S的圖案,以及圖案920;以及用以形成接觸特徵906與接觸特徵908的圖案(例如:圖案950)可與源極特徵/汲極特徵902S/904D的部分與閘極特徵904G的部分重疊。應注意的是,當從頂部觀察時,每一接觸特徵906與接觸特徵908可被各自的間隔層(例如:間隔層907與間隔層909)所圍繞。
圖10A與圖10B分別繪示了又一例示性半導體元件1000的透視圖和俯視圖,其包含本文中所揭露的接觸特徵中至少一者。如圖10A所示,半導體元件1000包含形成在基材1001上的電晶體1002與電晶體1004二個電晶體。電晶體1002包含閘極特徵(或電極)1002G、汲極特徵1002D與源極特徵1002S;以及電晶體1004包含閘極特徵(或電極)1004G、汲極特徵1004D與源極特徵1004S。儘管在圖10A的說明性實施例中,電晶體1002與電晶體1004被示為鰭式場效電晶體(FinFET),應理解的是,每一電晶體可包含任何其他類型的非平面電晶體(例如:奈米線電晶體或奈米片電晶體)中的一種,同時仍在本揭露的範圍內。半導體元件1000可包含分別電性地連接至汲極特徵/源極特徵1002D/ 1004S與閘極特徵1004G的接觸特徵1006與接觸特徵1008二個接觸特徵。每一接觸特徵1006與接觸特徵1008可包含上部與下部,如上所示。
圖10B繪示了半導體元件1000之相對應的俯視圖。在一些實施例中,圖10B可為半導體元件1000的佈局設計。如圖所示,圖9A中所示的每一特徵可根據圖9B的各自圖案來形成。舉例來說,圖10A中所示的每一特徵可根據圖10B的各自圖案來形成。舉例來說,用以形成閘極特徵1002G的圖案可延伸跨越用以形成源極特徵/汲極特徵1002S/1002D/1004S/1004D的圖案;用以形成閘極特徵904G的圖案可延伸跨越用以形成源極特徵/汲極特徵1002S/1002D/1004S/1004D的圖案;以及用以形成接觸特徵1006與接觸特徵1008的圖案(例如:圖案1050)可與源極特徵/汲極特徵1002D/1004S的部分與閘極特徵1004G的部分重疊。應注意的是,每一接觸特徵1006與接觸特徵1008可被各自的間隔層所圍繞或排列。
圖11A與圖11B分別繪示了又一例示性半導體元件1100的透視圖和俯視圖,其包含本文中所揭露的接觸特徵中至少一者。如圖11A所示,半導體元件1100包含形成在基材1101上的電晶體1102。電晶體1102包含閘極特徵(或電極)1102G、汲極特徵1102D與源極特徵102S。儘管在圖1的說明性實施例中,電晶體1102被繪示為鰭式場效電晶體(FinFET) ,然而應理解的是,電晶體可包含任何其他類型的非平面電晶體(例如:奈米線電晶體或奈米片電晶體)中的一種,同時仍在本揭露的範圍內。半導體元件1100可包含接觸特徵1104、接觸特徵1106、接觸特徵1108與接觸特徵1110共四個接觸特徵,其中接觸特徵1104與接觸特徵1106電性連接至源極特徵1102S,且接觸特徵1108與接觸特徵1110電性連接至汲極特徵1102D。接觸特徵1104至接觸特徵1110中之每一者可包含上部和下部,如上所示。
圖11B繪示了半導體元件1100之相對應的俯視圖。在一些實施例中,圖11B可為半導體元件1100的佈局設計。如圖所示,圖11A中所示的每一特徵可根據圖11B的各自圖案來形成。舉例來說,用以形成閘極特徵1102G的圖案可延伸跨越用以形成源極特徵/汲極特徵1102S/1102D的圖案;用以形成接觸特徵1104與接觸特徵1106的圖案(例如:圖案1150) 可與源極特徵1102S的部分重疊;以及用以形成接觸特徵1108與接觸特徵1110的圖案(例如:圖案1155) 可與汲極特徵1102D的部分重疊。應注意的是,接觸特徵1004至接觸特徵1010中之每一者可被各自的間隔層所圍繞或排列。
圖12與圖13分別繪示了如本文所揭露之接觸特徵的例示性俯視圖。例如在圖12中,接觸特徵1200包含上部1200U與下部1200L。在一些實施例中,上部1200U與下部1200L可各自形成為基於圓形的形狀並且彼此同心。因此,下部1200L可以小於上部1200U之直徑(或剖面長度) 的直徑(或剖面長度)來特徵化。在圖13的另一範例中,接觸特徵1300包含上部1300U與下部1300L。在一些實施例中,上部1300U與下部1300L係分別地形成為基於正方形或基於矩形的形狀,其沿著特定方向(例如:X方向)延伸。因此,下部1300L可以小於上部1300U之寬度(或剖面長度) W
1的寬度(或剖面長度)W
2(在垂直於X方向的方向上)來特徵化。
上述摘要許多實施例的特徵,因此本領域具有通常知識者可更了解本揭露的態樣。本領域具有通常知識者應理解利用本揭露為基礎可以設計或修飾其他製程和結構以實現和所述實施例相同的目的及/或達成相同優勢。本領域具有通常知識者也應了解與此同等的架構並沒有偏離本揭露的精神和範圍,且可以在不偏離本揭露的精神和範圍下做出各種變化、交換和取代。
本揭露之一態樣係提供一種半導體元件,包含:第一導電特徵、設置於第一導電特徵上方的第一介電層、以及延伸穿透第一介電層且電性地耦接至第一導電特徵的第一接觸特徵。其中第一接觸特徵的上部係藉由第二介電層側向地從第一介電層的第一內側壁分離,且第一接觸特徵的下部係與第一介電層的第一內側壁接觸。
本揭露之另一態樣係提供一種半導體元件,包含:導電特徵、設置於導電特徵上方的介電層、以及延伸穿透介電層的接觸特徵;其中接觸特徵具有上部及下部,上部係以間隔層來從介電層分離,下部係電性地耦接至導電特徵且與介電層接觸。
本揭露之又一態樣係提供一種製作半導體元件的方法,包含:凹陷(recessing)設置於導電特徵上方之第一介電層的上部;以第二介電層填充此凹陷的上部,以形成嵌入在第二介電層中的孔洞;蝕刻第二介電層與第一介電層以形成接觸孔,此接觸孔使用此孔洞暴露出導電特徵的至少一部分,以使至少接觸孔的下部與導電特徵垂直地對齊;以及以導電材料填充接觸孔,以形成電性地耦接至導電特徵的接觸特徵。
100:方法
102:操作
104:操作
106:操作
108:操作
110:操作
200:半導體元件
202:基材
204:導電特徵
206:第一介電層
206S:第一介電層的內側壁
207:凹陷部分
208:第二介電層
210:孔洞
212:接觸孔
213:蝕刻製程
214:間隔層
216:接觸特徵
216I:中間邊界
216L:下部
216U:上部
800:半導體元件
801:基材
802:電晶體
802D:汲極特徵
802G:閘極特徵
802S:源極特徵
803:井
804:電晶體
804D:汲極特徵
804G:閘極特徵
804S:源極特徵
805:低介電常數介電層
806:接觸特徵
806U:接觸特徵的上部
807:間隔層
808:接觸特徵
808U:接觸特徵的上部
809:間隔層
850:圖案
900:半導體元件
902:電晶體
902D:汲極特徵
902G:閘極特徵
902S:源極特徵
904:電晶體
904D:汲極特徵
904G:閘極特徵
904S:源極特徵
905:低介電常數層
906:接觸特徵
906L:接觸特徵的下部
906U:接觸特徵的上部
907:間隔層
908:接觸特徵
908L:接觸特徵的下部
908U:接觸特徵的上部
909:間隔層
920:圖案
950:圖案
1000:半導體元件
1001:基材
1002:電晶體
1002D:汲極特徵
1002G:閘極特徵
1002S:源極特徵
1004:電晶體
1004D:汲極特徵
1004G:閘極特徵
1004S:源極特徵
1006:接觸特徵
1008:接觸特徵
1050:圖案
1100:半導體元件
1101:基材
1102:電晶體
1102D:汲極特徵
1102G:閘極特徵
1102S:源極特徵
1104:接觸特徵
1106:接觸特徵
1108:接觸特徵
1110:接觸特徵
1150:圖案
1155:圖案
1200:接觸特徵
1200L:接觸特徵的下部
1200U:接觸特徵的上部
1300:接觸特徵
1300L:接觸特徵的下部
1300U:接觸特徵的上部
T
1:厚度
T
2:深度
W
1:寬度
W
2:寬度
W
3:厚度
W
4:寬度
根據以下詳細說明並配合附圖閱讀,使本揭露的態樣獲致較佳的理解。需注意的是,如同業界的標準作法,許多特徵並不是按照比例繪示的。事實上,為了進行清楚討論,許多特徵的尺寸可以經過任意縮放。
圖1係根據一些實施例所繪示的用於形成半導體元件之例式性的方法的流程圖。
圖2至圖7係根據一些實施例所繪示的各種製造階段期間之例式性的半導體元件的剖面視圖,其係由圖1的方法所製作。
圖8A係根據一些實施例所繪示的包含一或多個接觸特徵之例式性的半導體元件,其係由圖1的方法所製作。
圖8B係根據一些實施例所繪示的圖8A之半導體元件的相對應俯視圖。
圖9A係根據一些實施例所繪示的包含一或多個接觸特徵之另一例式性的半導體元件,其係由圖1的方法所製作。
圖9B係根據一些實施例所繪示的圖9A之半導體元件的相對應俯視圖。
圖10A係根據一些實施例所繪示的包含一或多個接觸特徵之又一例式性的半導體元件,其係由圖1的方法所製作。
圖10B係根據一些實施例所繪示的圖10A之半導體元件的相對應俯視圖。
圖11A係根據一些實施例所繪示的包含一或多個接觸特徵之又一例式性的半導體元件,其係由圖1的方法所製作。
圖11B係根據一些實施例所繪示的圖11A之半導體元件的相對應俯視圖。
圖12係根據一些實施例所繪示的接觸特徵的例式性的俯視圖,其係由圖1的方法所製作。
圖13係根據一些實施例所繪示的另一接觸特徵的例式性的俯視圖,其係由圖1的方法所製作。
國內寄存資訊(請依寄存機構、日期、號碼順序註記)
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國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記)
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200:半導體元件
202:基材
204:導電特徵
206:第一介電層
206S:第一介電層的內側壁
214:間隔層
216:接觸特徵
216I:中間邊界
216L:下部
216U:上部
W1:寬度
W2:寬度
W3:厚度
W4:寬度
Claims (20)
- 一種半導體元件,包含: 一第一導電特徵; 一第一介電層,設置於該第一導電特徵上方;以及 一第一接觸特徵,延伸穿透該第一介電層,該第一接觸特徵電性地耦接至該第一導電特徵; 其中該第一接觸特徵的一上部係藉由一第二介電層側向地從該第一介電層的一第一內側壁分離,且該第一接觸特徵的一下部係與該第一介電層的該第一內側壁接觸。
- 如請求項1所述之元件,其中該第一導電特徵包含由一第一電晶體的一汲極特徵、該第一電晶體的一源極特徵、該第一電晶體的一閘極特徵、以及在一金屬化的層中側向地延伸的一第一互聯特徵所組成之一群組中所選擇之一特徵。
- 如請求項2所述之元件,更包含: 一第二導電特徵;以及 一第二接觸特徵,延伸穿透該第一介電層,該第二接觸特徵電性地耦接至該第二導電特徵; 其中該第二接觸特徵的一上部係藉由一第三介電層側向地從該第一介電層的一第二內側壁分離,該第三介電層係實質上地類似於該第二介電層。
- 如請求項3所述之元件,其中該第二導電特徵包含由該第一電晶體的該汲極特徵、該第一電晶體的該源極特徵、該第一電晶體的該閘極特徵、一第二電晶體的一汲極特徵、該第二電晶體的一源極特徵、該第二電晶體的一閘極特徵、以及在該金屬化的層中側向地延伸的一第二互聯特徵所組成之一群組中所選的一特徵。
- 如請求項3所述之元件,其中該第二介電層與該第三介電層中之每一者係以不同於該第一介電層的一第二蝕刻速率的一第一蝕刻速率被特性化。
- 如請求項1所述之元件,其中該第二介電層包含由一基於氧化物的介電材料、一基於氮化物的介電材料、以及一多晶矽材料所組成之一群組中所選的一材料。
- 如請求項1所述之元件,其中該下部的一第一側向寬度係實質上地小於該上部的一第二側向寬度與該第二介電層的一厚度的一總和。
- 如請求項1所述之元件,其中該下部的一第一側向寬度係等於或小於三分之一的該上部的一第二側向寬度與該第二介電層的一或多個厚度的一總和。
- 如請求項6所述之元件,其中該第一接觸特徵更包含在該上部與該下部之一交會處的一側向邊界。
- 一種半導體元件,包含: 一導電特徵; 一介電層,設置於該導電特徵上方;以及 一接觸特徵,延伸穿透該介電層; 其中該接觸特徵具有一上部及一下部,該上部係以一間隔層來從該介電層分離,該下部係電性地耦接至該導電特徵且與該介電層接觸。
- 如請求項10所述之元件,其中該接觸特徵之該下部的一第一側向寬度等於或小於三分之一的該接觸特徵之該上部的一第二側向寬度與一或多個該間隔層的厚度的總和。
- 如請求項10所述之元件,其中該間隔層包含由一基於氧化物的介電材料、一基於氮化物的介電材料、以及一多晶矽材料所組成之一群組中所選的一材料。
- 如請求項10所述之元件,其中該第一導電特徵包含由一電晶體的一汲極特徵、該電晶體的一源極特徵、該電晶體的一閘極特徵、以及在一金屬化的層中側向地延伸的一互聯特徵所組成之一群組中所選的一特徵。
- 一種製作半導體元件的方法,包含: 凹陷(recessing)設置於一導電特徵上方之一第一介電層的一上部; 以一第二介電層填充該凹陷的上部,以形成嵌入在該第二介電層中的一孔洞; 蝕刻該第二介電層與該第一介電層,以形成一接觸孔,該接觸孔使用該孔洞暴露出該導電特徵的至少一部分,以使至少該接觸孔的一下部與該導電特徵垂直地對齊;以及 以一導電材料填充該接觸孔,以形成電性地耦接至該導電特徵的一接觸特徵。
- 如請求項14所述之方法,其中以一第二介電層填充該凹陷的上部以形成一孔洞更包含: 調整填充該第二介電層的一沈積速率,以形成該第二介電層的一突出物,該突出物包含側向地朝向彼此延伸以包圍該孔洞的一第一部分與一第二部分。
- 如請求項14所述之方法,其中蝕刻該第二介電層與該第一介電層以形成一接觸孔更包含: 蝕刻該第二介電層的一部分與該第一介電層的一部分,該第二介電層的該部分與該第一介電層的該部分中之每一者係與該孔洞垂直地對齊,因而留下該第二介電層之一殘留部分且沿著該接觸孔之一上部的一內側壁延伸。
- 如請求項14所述之方法,其中蝕刻該第二介電層與該第一介電層以形成一接觸孔更包含: 蝕刻該第二介電層與該第一介電層,以形成該接觸孔的一上部,同時留下該第二介電層的一殘留部分且沿著該接觸孔之一上部的一內側壁延伸;以及 藉由形成該接觸孔的該下部來蝕刻該第一介電層,以暴露出該導電特徵。
- 如請求項14所述之方法,更包含: 在蝕刻該第二介電層與該第一介電層以形成一接觸孔之前,研磨該第一介電層與該第二介電層,以形成一實質上平坦的表面。
- 如請求項14所述之方法,其中該凹陷的上部的一第一側向寬度係實質上地大於該接觸孔之該下部的一第二側向寬度。
- 如請求項14所述之方法,其中該凹陷的上部的一第一側向寬度係等於或大於三倍的該接觸孔之該下部的一第二側向寬度。
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