TW202230668A - 封裝結構 - Google Patents

封裝結構 Download PDF

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TW202230668A
TW202230668A TW110108692A TW110108692A TW202230668A TW 202230668 A TW202230668 A TW 202230668A TW 110108692 A TW110108692 A TW 110108692A TW 110108692 A TW110108692 A TW 110108692A TW 202230668 A TW202230668 A TW 202230668A
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Taiwan
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package
ring
ring structure
semiconductor
semiconductor package
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TW110108692A
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TWI792217B (zh
Inventor
葉書伸
汪金華
林昱聖
林柏堯
鄭心圃
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台灣積體電路製造股份有限公司
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  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract

一種封裝結構包括線路基底、半導體封裝、第一環結構及第二環結構。半導體封裝設置在線路基底上且電性連接到線路基底。第一環結構貼合到線路基底且環繞半導體封裝，其中第一環結構包括中心開口及從中心開口的角落延伸出的多個角落開口，半導體封裝位於中心開口中，且所述多個角落開口環繞半導體封裝的角落。

Description

封裝結構
用於各種電子應用（例如，手機及其他移動電子設備）中的半導體元件及積體電路通常製造在單個半導體晶圓上。可以在晶圓級下，對晶圓的晶粒進行處理並將晶圓的晶粒與其他半導體元件或晶粒封裝在一起，且已開發各種技術來進行晶圓級封裝。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅是實例而非旨在進行限制。舉例來說，在以下說明中，在第一特徵之上或第一特徵上形成第二特徵可包括其中第二特徵與第一特徵被形成為直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成附加特徵從而使得第二特徵與第一特徵可不直接接觸的實施例。另外，本公開可在各種實例中重複使用參考編號及/或字母。此種重複使用是為了簡明及清晰起見，且自身並不表示所論述的各個實施例及/或配置之間的關係。
此外，為易於說明，本文中可使用例如“在…之下”、“在…下方”、“下部的”、“在…上”、“在…之上”、“上覆的”、“在…上方” 、“上部的”等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向之外還囊括器件在使用或操作中的不同取向。裝置可具有其他取向（旋轉90度或處於其他取向），且本文中所使用的空間相對性描述語可同樣相應地加以解釋。
在傳統封裝結構中，角落模塑（corner molding）通常由於模塑體積較大而具有較大的模塑應力，此會引發局部變形且帶來較高的模塑破裂及分層的風險。在本公開的一些實施例中，雖然提供環結構（加強環）來減小封裝基底的翹曲，但所述環結構的設計被修改以有助於減小模塑應力及封裝結構的翹曲。在一些實施例中，封裝結構的環結構的內表面與內半導體封裝之間的距離在角落部分處比在其他部分處更大。環結構的內表面在角落部分處收縮以使得距內半導體封裝的空間更大。
圖1A到圖1I是根據本公開的一些示例性實施例的製作半導體封裝的方法中的各個階段的示意性上視圖及剖面圖。參考圖1A，提供中介層結構100。在一些實施例中，中介層結構100包括核心部分102及形成在核心部分102中的多個穿孔104及導電焊盤106。在一些實施例中，核心部分102是基底，例如塊狀半導體基底、絕緣體上矽（silicon on insulator，SOI）基底或多層半導體材料基底。基底（核心部分102）的半導體材料可以是矽、鍺、矽鍺、碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦、銻化銦、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其組合。在一些實施例中，核心部分102經過摻雜或未經摻雜。
在一些實施例中，核心部分102的第一表面102a上形成有導電焊盤106。在一些實施例中，在核心部分102中形成穿孔104且穿孔104與導電焊盤106連接。在一些實施例中，穿孔104在核心部分102中延伸特定的深度。在一些實施例中，穿孔104是基底穿孔。在一些實施例中，當核心部分102是矽基底時，穿孔104是矽穿孔。在一些實施例中，通過在核心部分102中形成孔或凹槽，且接著是使用導電材料填充凹槽來形成穿孔104。在一些實施例中，通過例如蝕刻、研磨、雷射鑽孔等形成凹槽。在一些實施例中，導電材料是通過電化學鍍覆製程、化學氣相沉積（chemical vapor deposition，CVD）、原子層沉積（atomic layer deposition，ALD）或物理氣相沉積（physical vapor deposition，PVD）形成，且所述導電材料可包括銅、鎢、鋁、銀、金或其組合。在一些實施例中，與穿孔104連接的導電焊盤106被形成為形成在中介層結構100上的重佈線層的導電部。在一些實施例中，導電焊盤106包括凸塊下金屬（under bump metallurgies，UBM）。在某些實施例中，中介層結構100還可包括形成在核心部分102中的主動元件或被動元件，例如電晶體、電容器、電阻器或二極體。
如圖1A中所示，核心部分102具有多個封裝區PKR及將所述多個封裝區PKR中的每一者隔開的切割道DL。穿孔104及導電焊盤106在封裝區PKR內形成在核心部分102中。在一些實施例中，在中介層結構100上或在封裝區PKR內的核心部分102上設置多個半導體晶粒21（第一半導體晶粒）及多個半導體晶粒22（第二半導體晶粒）。半導體晶粒21及半導體晶粒22是從晶圓單體化而來的個別晶粒。在一些實施例中，半導體晶粒21含有相同的電路系統（例如，裝置及金屬化圖案），或半導體晶粒21是相同類型的晶粒。在一些實施例中，半導體晶粒22含有相同的電路系統，或半導體晶粒22是相同類型的晶粒。在某些實施例中，半導體晶粒21與半導體晶粒22具有不同的電路系統或是不同類型的晶粒。在一些實施例中，半導體晶粒21與半導體晶粒22可具有相同的電路系統。
在一些實施例中，半導體晶粒21是主晶粒，而半導體晶粒22是附屬晶粒。在一些實施例中，主晶粒在每一封裝區PKR的中心位置中排列在核心部分102上，而附屬晶粒並排地排列，且與主晶粒間隔開。在一些實施例中，附屬晶粒被排列成位於主晶粒旁邊且在主晶粒周圍或環繞主晶粒。在一個實施例中，在每一個封裝區PKR中，一個主晶粒周圍排列有4個、6個或8個附屬晶粒。舉例來說，參考圖1B，在示例性實施例中，在封裝區PKR中的每一者中，8個半導體晶粒22（附屬晶粒）環繞一個半導體晶粒21（主晶粒）。
返回參考圖1A，在一些實施例中，半導體晶粒21具有比半導體晶粒22的表面積大的表面積。此外，在一些實施例中，半導體晶粒21與半導體晶粒22具有不同的大小、包括不同的表面積及/或不同的厚度。在一些實施例中，半導體晶粒21是邏輯晶粒，包括中央處理單元（central processing unit，CPU）晶粒、圖形處理單元（graphics processing unit，GPU）晶粒、系統晶片（system-on-a-chip，SoC）晶粒、微控制器等。在一些實施例中，半導體晶粒21是功率管理晶粒，例如功率管理積體電路（power management integrated circuit，PMIC）晶粒。在一些實施例中，半導體晶粒22是記憶體晶粒，包括動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒或高頻寬記憶體（high bandwidth memory，HBM）晶粒。在一些替代實施例中，半導體晶粒22是不執行任何電性功能的虛設晶粒。本公開並不僅限於此，且可基於產品要求適當地調整設置在核心部分102上的半導體晶粒的數目、大小及類型。
如圖1A中所說明，半導體晶粒21包括本體210及連接焊盤212，連接焊盤212形成在本體210的主動表面211上。在某些實施例中，連接焊盤212還可包括用於將半導體晶粒21結合到其他結構的柱結構。在一些實施例中，半導體晶粒22包括本體220及連接焊盤222，連接焊盤222形成在本體220的主動表面221上。在其他實施例中，連接焊盤222還可包括用於將晶粒22結合到其他結構的柱結構。
在一些實施例中，例如是通過倒裝晶片結合經由電性連接件110將半導體晶粒21及半導體晶粒22貼合到核心部分102的第一表面102a上。通過回焊製程，電性連接件110形成在連接焊盤212、222與導電焊盤106之間，且在實體上將半導體晶粒21、22連接到中介層結構100的核心部分102。在一些實施例中，電性連接件110位於半導體晶粒21、22與中介層結構100的中間。在某些實施例中，半導體晶粒21、22通過電性連接件110電性連接到穿孔104及導電焊盤106。在一些替代實施例中，當半導體晶粒22是虛設晶粒時，半導體晶粒22可通過在實體上連接貼合到電性連接件110，但不建立與電性連接件110的電性連接。換句話說，半導體晶粒22的連接焊盤222可以例如是虛設焊盤。
在一個實施例中，電性連接件110是微凸塊，例如具有銅金屬柱的微凸塊。在另一實施例中，電性連接件110是焊料凸塊、無鉛焊料凸塊或例如受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊等微凸塊、或含有銅柱的微凸塊。在一些實施例中，半導體晶粒21、22與核心部分102之間的結合是焊料結合。在一些實施例中，半導體晶粒21、22與核心部分102之間的結合是直接的金屬對金屬結合，例如銅對銅結合。
參考圖1C，此後，可形成底部填充結構112以覆蓋所述多個電性連接件110且填滿半導體晶粒21、22與中介層結構100中間的空間。在一些實施例中，底部填充結構112進一步覆蓋半導體晶粒21、22的側壁且位於封裝區PKR內。此後，可在中介層結構100之上（或在核心部分102之上）形成絕緣包封體114（或模塑化合物）以覆蓋底部填充結構112且環繞半導體晶粒21及22。
在一些實施例中，絕緣包封體114形成在封裝區PKR中的核心部分102的第一表面102a上且形成在切割道DL之上。在一些實施例中，絕緣包封體114是例如通過壓縮模塑製程或轉移模塑而形成。在一個實施例中，是執行固化製程以固化絕緣包封體114。在一些實施例中，半導體晶粒21、22及電性連接件110被絕緣包封體114包封。在一些實施例中，執行包括研磨或拋光在內的平坦化製程以部分地移除絕緣包封體114，從而暴露出半導體晶粒21、22的背側表面21S、22S。因此，半導體晶粒21、22的背側表面21S、22S與絕緣包封體114的頂表面114a齊平。頂表面114a與絕緣包封體114的背側表面114b相對，其中背側表面114b與核心部分102接觸。在一些替代實施例中，半導體晶粒21、22的背側表面21S、22S並未從絕緣包封體114暴露出來，且受到絕緣包封體114的良好保護。
在一些實施例中，絕緣包封體114的材料包括聚合物（例如，環氧樹脂、酚醛樹脂、含矽樹脂或其他適合的樹脂）、具有低電容率（low permittivity，Dk）及低損耗角正切（low loss tangent，Df）性質的介電材料或其他適合的材料。在替代實施例中，絕緣包封體114可包含可接受的絕緣包封材料。在一些實施例中，絕緣包封體114還可包含無機填充物或無機化合物（例如，二氧化矽、黏土等），所述無機填充物或無機化合物可添加在絕緣包封體114中以優化絕緣包封體114的熱膨脹係數（coefficient of thermal expansion，CTE）。本公開並不僅限於此。
參考圖1D，將圖1C的結構倒置或翻轉，並放置在載體Cx上，以使得載體Cx直接接觸半導體晶粒21、22的背側表面21S、22S及絕緣包封體114的頂表面114a。如圖1D中所示，在此處理階段，中介層結構100尚未被薄化且具有厚度Tx。換句話說，穿孔104未被顯露出，且嵌置在中介層結構100的核心部分102中。
參考圖1E，對中介層100執行薄化製程以部分地移除或薄化中介層結構100的核心部分102，直到暴露出穿孔104且形成核心部分102的第二表面102b為止。在一些實施例中，薄化製程可包括背部研磨製程、拋光製程或蝕刻製程。在一些實施例中，在薄化製程之後，中介層結構100被薄化到厚度Ty。在一些實施例中，厚度Ty對厚度Tx的比率處於約0.1到約0.5的範圍內。
參考圖1F，在封裝區PKR中的核心部分102的第二表面102b上及在切割道DL之上形成重佈線結構116。核心部分102的第二表面102b與第一表面102a相對。在一些實施例中，重佈線結構116、核心部分102、穿孔104及導電焊盤106構成中介層結構100’。在一些實施例中，重佈線結構116將穿孔104電性連接及/或將穿孔104與外部器件電性連接。在某些實施例中，重佈線結構116包括至少一個介電層116a及位於介電層116a中的金屬化圖案116b。在一些實施例中，金屬化圖案116b可包括將穿孔104內連且進一步將穿孔104連接到一個或多個外部器件的焊盤、通孔及/或跡線。儘管圖1F中示出介電層116a中的一個層及金屬化圖案116b中的一個層，但應注意，介電層116a的層數及金屬化圖案116b的層數並不僅限於此，且此可基於要求進行調整。
在一些實施例中，介電層116a的材料包括氧化矽、氮化矽、碳化矽、氮氧化矽、或低介電常數（low-K）介電材料（例如，磷矽酸鹽玻璃（phosphosilicate glass，PSG）材料、氟矽酸鹽玻璃材料、硼磷矽酸鹽玻璃材料、SiOC、旋塗玻璃材料、旋塗聚合物或矽碳材料）。在一些實施例中，介電層116a是通過旋轉塗布或沉積而形成，所述沉積包括化學氣相沉積（CVD）、等離子體增強CVD（Plasma Enhanced CVD，PECVD）、高密度等離子體CVD（High-Density Plasma-CVD，HDP-CVD）等。在一些實施例中，金屬化圖案116b包括凸塊下金屬（UBM）。在一些實施例中，金屬化圖案116b的形成可包括：使用微影技術及一種或多種蝕刻製程將介電層圖案化，並將金屬材料填充到經圖案化介電層的開口中。可例如通過使用化學機械拋光製程移除介電層上的任何多餘導電材料。在一些實施例中，金屬化圖案116b的材料包括銅、鋁、鎢、銀及其組合。
如圖1F中進一步說明，多個導電端子118設置在金屬化圖案116b上，且電性耦合到穿孔104。在一些實施例中，導電端子118放置在重佈線結構116的頂表面116s上，且通過封裝區PKR內的金屬化圖案116b電性連接到穿孔104。在某些實施例中，導電端子118定位在金屬化圖案116b上且在實體上貼合到金屬化圖案116b。在一些實施例中，導電端子118包括無鉛焊料球、焊料球、球柵陣列（ballgridarray，BGA）球、凸塊、C4凸塊或微凸塊。在一些實施例中，導電端子118可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫或其組合等導電材料。在一些實施例中，通過例如蒸鍍、電鍍覆、印刷或焊料轉移在重佈線結構116上形成焊料膏來形成導電端子118，且然後將導電端子118回焊成所期望的凸塊形狀。在一些實施例中，通過植球等將導電端子118放置在重佈線結構116上。在其他實施例中，通過如以下方式形成導電端子118：通過濺鍍、印刷、無電鍍覆或電鍍覆或CVD形成無焊料金屬柱（例如，銅柱），且然後通過對所述金屬柱進行鍍覆形成無鉛頂蓋層。導電端子118可用於結合到外部器件或附加電元件。在一些實施例中，導電端子118用於結合到線路基底、半導體基底或封裝基底。
參考圖1G，在後續的步驟中，剝離載體Cx。舉例來說，剝離製程包括將光（例如，雷射或紫外線（ultraviolet，UV）光）投射在貼合到載體Cx的剝離層（例如，光熱轉換釋放層）上（未示出），以使得可容易地將載體Cx與剝離層一起移除。在一些實施例中，在剝離製程之後顯露出半導體晶粒21、22的背側表面21S、22S。
參考圖1H，在剝離載體Cx之後，將圖1G中所示的結構貼合到由框架FR支撐的條帶TP（例如，切割條帶）。隨後，沿著切割道DL對圖1G中所示的結構進行切割或單體化以形成多個半導體封裝SM。舉例來說，沿著切割道DL執行切割製程以切穿重佈線結構116、核心部分102及絕緣包封體114，以移除重佈線結構116的一些部分、核心部分102的一些部分及絕緣包封體114的一些部分。在一些實施例中，切割製程或單體化製程通常涉及使用旋轉刀片或雷射光束進行切割。換句話說，切割或單體化製程例如是雷射切分製程、機械鋸割製程或其他適合的製程。在剝離載體Cx之後，可獲得圖1I中所示的經單體化的半導體封裝SM。
圖2是根據本公開的一些其他示例性實施例的半導體封裝的示意性剖面圖。圖2中所說明的半導體封裝SM2類似於圖1I中所說明的半導體封裝SM。因此，相同的元件符號將用於表示相同或相似的元件，且本文中將不再對其加以贅述。實施例之間的差異在於，圖1I中所示的中介層結構100’被圖2中所示的重佈線層RDL取代。如圖2中所示，重佈線層RDL設置在絕緣包封體114上且通過電性連接件110電性連接到半導體晶粒21、22。
在一些實施例中，通過交替地依序形成一個或多個介電層101A及一個或多個導電層101B來形成重佈線層RDL。在某些實施例中，導電層101B夾置在介電層101A之間，並且電性連接且在實體上連接到電性連接件110。在示例性實施例中，重佈線層RDL中所包括的介電層101A及導電層101B的數目並不僅限於此，且可基於設計要求來指定並選擇。舉例來說，介電層101A的數目及導電層101B的數目可以是一個或多於一個。
在一些實施例中，介電層101A的材料是聚醯亞胺、聚苯並噁唑（polybenzoxazole，PBO）、苯並環丁烯（benzocyclobutene，BCB）、例如氮化矽等氮化物、例如氧化矽等氧化物、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）、其組合等，介電層101A的材料可使用微影製程及/或蝕刻製程來圖案化。在一些實施例中，介電層101A的材料是通過適合的製作技術（例如，旋轉塗布、化學氣相沉積（CVD）、等離子體增強化學氣相沉積（PECVD）等）來形成。本公開並不僅限於此。
在一些實施例中，導電層101B的材料由通過電鍍覆或沉積形成的導電材料製成，例如鋁、鈦、銅、鎳、鎢及/或其合金，可使用微影製程及蝕刻製程來將導電層101B的材料圖案化。在一些實施例中，導電層101B可以是經圖案化銅層或其他適合的經圖案化金屬層。在本說明通篇中，用語“銅”旨在包括實質上純元素銅、含有不可避免的雜質的銅及含有微量的例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等元素的銅合金。
在某些實施例中，重佈線層RDL還包括設置在導電層101B上以與導電端子118電性連接的多個導電焊盤101C。在一些實施例中，導電焊盤101C的材料可包括銅、鎳、鈦、鎢或其合金等，且可例如通過電鍍覆製程來形成。導電焊盤101C的數目在本公開中不受限制，且可基於設計佈局來選擇。在一些替代實施例中，可省略導電焊盤101C。換句話說，在後續的步驟中形成的導電端子118可直接設置在重佈線層RDL的導電層101B上。
圖3A到圖3D是根據本公開的一些示例性實施例的製作封裝結構的方法中的各個階段的示意性上視圖及剖面圖。參考圖3A，在一些實施例中，通過導電端子118將在圖1H中獲得的半導體封裝SM安裝或貼合到線路基底300上。在一些實施例中，線路基底300包括接觸焊盤310、接觸焊盤320、金屬化層330及通孔（未示出）。在一些實施例中，接觸焊盤310及接觸焊盤320分別分佈在線路基底300的相對的兩側上，且被暴露出以與後續形成的元件/特徵電性連接。在一些實施例中，金屬化層330及通孔嵌置在線路基底300中且一起為線路基底300提供佈線功能，其中金屬化層330及通孔電性連接到接觸焊盤310及接觸焊盤320。換句話說，接觸焊盤310中的至少一些接觸焊盤通過金屬化層330及通孔電性連接到接觸焊盤320中的一些接觸焊盤。在一些實施例中，接觸焊盤310及接觸焊盤320可包括金屬焊盤或金屬合金焊盤。在一些實施例中，金屬化層330的材料及通孔的材料可與接觸焊盤310的材料及接觸焊盤320的材料實質上相同或類似。
此外，在一些實施例中，通過將導電端子118與接觸焊盤310在實體上連接來將半導體封裝SM結合到線路基底300，以形成堆疊結構。在某些實施例中，半導體封裝SM電性連接到線路基底300。在一些實施例中，線路基底300例如是有機柔性基底或印刷電路板。在這些實施例中，導電端子118例如是晶片連接件。在一些實施例中，基底300上分別形成有多個導電球340。如圖3A中所示，舉例來說，導電球340連接到線路基底300的接觸焊盤320。換句話說，導電球340通過接觸焊盤320電性連接到線路基底300。通過接觸焊盤310及接觸焊盤320，導電球340中的一些導電球電性連接到半導體封裝SM（例如，半導體封裝SM所包括的半導體晶粒21及22）。在一些實施例中，導電球340例如是焊料球或BGA球。在一些實施例中，通過基底上覆晶圓上晶片（chip on wafer on substrate，CoWoS）封裝製程使導電端子118與線路基底300的接觸焊盤310在實體上連接，以將半導體封裝SM結合到線路基底300。另外，如圖3A中所說明，可將被動元件PDx（積體被動元件或表面安裝器件）安裝在線路基底300上。舉例來說，可通過焊接製程將被動元件PDx安裝在線路基底300的接觸焊盤310上。本公開並不僅限於此。在某些實施例中，可將被動元件PDx安裝在線路基底上，從而環繞半導體封裝SM。在一些替代實施例中，可省略被動元件PDx。
如圖3A中進一步說明，在一些實施例中，形成底部填充結構350以填滿線路基底300與半導體封裝SM中間的空間。在某些實施例中，底部填充結構350填滿相鄰的導電端子118之間的空間且覆蓋導電端子118。舉例來說，底部填充結構350環繞所述多個導電端子118。在一些實施例中，被動元件PDx由底部填充結構350暴露出，且與底部填充結構350間隔開一定距離。換句話說，底部填充結構350不覆蓋被動元件PDx。
參考圖3B，在後續的步驟中，通過第一黏合劑AD1將第一環結構RS1（第一加強環）貼合到線路基底300，且通過第二黏合劑AD2將第二環結構RS2（第二加強環）貼合到第一環結構RS2。第一環結構RS1可環繞中介層結構100’且部分地環繞絕緣包封體114，而第二環結構RS2可部分地環繞絕緣包封體114及半導體晶粒21、22。在一些實施例中，根據半導體晶粒21、22的厚度，第一環結構RS1也可部分地環繞半導體晶粒21、22。
在一些實施例中，第一環結構RS1由熱膨脹係數（CTE）比第二環結構RS2的材料的CTE小的材料製成。在一些實施例中，第一環結構RS1及第二環結構RS2兩者皆是由金屬材料形成。舉例來說，在一個實施例中，第一環結構RS1由不銹鋼304SS製成，且第二環結構RS2由不銹鋼430SS製成。本公開並不僅限於此。在將第一環結構RS1及第二環結構RS2貼合到線路基底300上之後，可實現根據本公開的一些實施例的封裝結構PKS1。
將參考圖3C及圖3D中所示的上視圖更詳細地闡述第一環結構RS1及第二環結構RS2。圖3C是示出第一環結構RS1的上視圖，而圖3D是示出第二環結構RS2的上視圖。在圖3C及圖3D的上視圖中，為易於說明起見，省略了底部填充結構350及被動元件PDx。
如圖3B及圖3C中所示，在一些實施例中，第一環結構RS1（第一加強環）貼合到線路基底300且環繞半導體封裝SM。此外，第一環結構RS1位於線路基底300與第二環結構RS2的中間。在一些實施例中，第一環結構RS1包括中心開口OP1及從中心開口OP1的角落延伸出的多個角落開口OP2。在一些實施例中，第一環結構RS1的中心開口OP1是具有四個角落的正方形或矩形開口，且在所述四個角落處執行角落挖蝕（corner digging）以形成所述多個角落開口OP2。換句話說，角落開口OP2與中心開口OP1接合，且從正方形或矩形中心開口OP1的四個角落延伸出。在某些實施例中，角落開口OP2具有多邊形輪廓。舉例來說，在示例性實施例中，在與中心開口OP1的四個角落交疊的位置處依照正方形輪廓執行角落挖蝕以形成角落開口OP2。
在一些實施例中，半導體封裝SM位於中心開口OP1中，且所述多個角落開口OP2環繞半導體封裝SM的角落。舉例來說，半導體封裝SM被第一環結構RS1的中心開口OP1及角落開口OP2包圍。在一些實施例中，角落開口OP2中的每一者具有在第一方向DR1上延伸的第一寬度d1及在第二方向DR2上延伸的第二寬度d2。舉例來說，第一方向DR1垂直於第二方向DR2，且第一寬度d1實質上等於第二寬度d2。此外，第一寬度d1及第二寬度d2不延伸超出第一環結構RS1的環腳（外角落）。即，第一環結構RS1形成連續環狀結構。
在一些實施例中，半導體封裝SM與中心開口OP1的邊界間隔開距離d3及距離d4。在一些實施例中，距離d3是在第一方向DR1上測量，且距離d4是在第二方向DR2上測量。在一些實施例中，距離d3及距離d4是從半導體封裝SM的對應側壁到中心開口OP1的對應內側壁的最小距離。距離d3可實質上等於距離d4，或者可大於或小於距離d4，且此可基於設計要求來調整。此外，在某些實施例中，距離d3小於第一寬度d1，而距離d4小於第二寬度d2。
在一些實施例中，半導體封裝SM與中心開口OP1的邊界的最小距離（距離d3或距離d4）小於從半導體封裝SM的角落到角落開口OP2的邊界的最大距離d5。在一些實施例中，最大距離d5可從半導體封裝SM的角落延伸到略大於中心開口OP1的角落的區域，或延伸到略小於第一環結構RS1的環腳（外角落）的區域。在某些實施例中，當半導體封裝SM的第一側壁到第一環結構RS1的內側壁的最小距離是距離d3、半導體封裝SM的第二側壁到第一環結構RS1的內側壁的最小距離是距離d4時，則從半導體封裝SM的角落到第一環結構RS1的內角落的最大距離d5滿足以下關係式：d5＞√((d3) 2+(d4) 2)。換句話說，可適當地調整最大距離d5，只要其在中心開口OP1的角落之上延伸且不延伸超出第一環結構RS1的環腳（外角落）即可。通過控制中心開口OP1及角落開口OP2的尺寸及相對距離，可明顯地減小半導體封裝SM中的模塑應力。
如圖3B及圖3C中進一步說明，在一些實施例中，第一環結構RS1（第一加強環）包括框架部分RS1-A及多個突出部RS1-B，所述多個突出部RS1-B從框架部分RS1-A的內表面朝半導體封裝SM延伸出。舉例來說，框架部分RS1-A是環形結構，且所述多個突出部RS1-B在貼合到框架部分RS1-A的內表面的同時彼此隔開。在某些實施例中，突出部RS1-B中的每一者朝半導體封裝SM的中介層結構100’延伸。框架部分RS1-A及所述多個突出部RS1-B的設計及形狀界定中心開口OP1及角落開口OP2的輪廓。
在一些實施例中，突出部RS1-B中的每一者包括第一側SD1、第二側SD2、第三側SD3及第四側SD4。舉例來說，第一側SD1與框架部分RS1-A接合。第二側SD2與第一側SD1相對，其中第二側SD1包括與（半導體封裝SM的）中介層結構100’的側表面SM-SD平行的平坦表面。此外，第三側SD3及第四側SD4分別將第二側SD2接合到第一側SD1。在示例性實施例中，突出部RS1-B中的每一者的第一側SD1、第二側SD2、第三側SD3及第四側SD4接合在一起以形成矩形輪廓。然而，本公開並不僅限於此，且突出部RS1-B的輪廓可基於設計要求來調整。通過將第一環結構RS1設計成包括面向中介層結構100’的側表面SM-SD的所述多個突出部RS1-B，可明顯地減小位於半導體封裝SM的角落處的模塑應力。
參考圖3B及圖3D，第二環結構RS2（第二加強環）貼合到第一環結構RS1以環繞半導體封裝SM。在一些實施例中，第二環結構RS2包括與第一環結構RS1的中心開口OP1交疊的第二中心開口OP3。在一些實施例中，第一環結構RS1的中心開口OP1的輪廓實質上等於第二環結構RS2的第二中心開口OP3的輪廓。即，第二中心開口OP3是具有四個角落的正方形或矩形開口（未進行角落挖蝕）。
此外，第二環結構RS2包括具有交疊部RS2-OV及非交疊部RS2-NV的第二框架部分RS2-A。舉例來說，第二框架部分RS2-A的交疊部RS2-OV與第一環結構RS1的框架部分RS1-A及所述多個突出部RS1-B交疊，而第二框架部分RS2-A的非交疊部RS2-NV位於第二加強環RS2的四個內角落處。在一些實施例中，第二框架部分RS2-A的非交疊部RS2-NV對應於第一環結構RS1的角落開口OP2的位置。在一些實施例中，第一環結構RS1具有第一厚度H1，而第二環結構RS2具有第二厚度H2。在一個實施例中，第一厚度H1大於第二厚度H2。舉例來說，第一厚度H1對第二厚度H2的比率可處於1.1:1到1.8:1的範圍內。然而，本公開並不僅限於此，且第一厚度H1及第二厚度H2可基於產品要求進行調整。在一些代替實施例中，第二厚度H2大於第一厚度H1。
在示例性實施例中，第一環結構RS1及第二環結構RS1可具有相加而實質上等於或大於線路基底300上的半導體封裝SM的高度的厚度。然而，本公開並不僅限於此，且可適當地調整第一環結構RS1的厚度及第二環結構RS1的厚度。此外，第一環結構RS1及第二環結構RS2可一起用於減小因將半導體封裝SM結合到線路基底300所導致的線路基底300的翹曲。另外，半導體封裝SM將受到第一環結構RS1及第二環結構RS2的約束，以在減小半導體封裝SM的內部應力的同時控制介面應力。整體來說，包括第一環結構RS1及第二環結構RS2的封裝結構PKS1的可靠性將得到改善。
圖4到圖8是根據本公開的各種實施例的第一環結構的上視圖。在各種實施例中，可根據圖4到圖8調整圖3C中所示的第一環結構RS1的設計，所有的這些設計皆可有助於減小半導體封裝SM中的模塑應力。圖4到圖8中所說明的第一環結構RS1的各種設計可類似於圖3C中所說明的第一環結構RS1。因此，使用相同的元件符號來表示相同或相似的元件，且本文中將不再對其加以贅述。
參考圖4，圖3C中所示的第一環結構RS1與圖4中所示的第一環結構RS1之間的差異在於角落開口OP2的設計。舉例來說，圖3C的角落開口OP2具有第一寬度d1，第一寬度d1實質上等於第二寬度d2。然而，本公開並不僅限於此。參考圖4，可將第一寬度d1調整為大於第二寬度d2。作為另外一種選擇，在一些其他實施例中，可將第一寬度d1調整為小於第二寬度d2。換句話說，角落開口OP2的第一寬度d1及第二寬度d2的尺寸可基於設計要求來調整。
參考圖5，圖3C中所示的第一環結構RS1與圖5中所示的第一環結構RS1之間的差異在於角落開口OP2的形狀。舉例來說，如圖5中所說明，角落開口OP2具有多邊形輪廓。在示例性實施例中，在與中心開口OP1的四個角落交疊的位置處依照六邊形輪廓執行角落挖蝕以形成角落開口OP2。另外，如圖5中所示，除具有框架部分RS1-A及多個突出部RS1-B之外，第一環結構RS1還可包括多個角落部RS1-B2，所述多個角落部RS1-B2位於框架部分RS1-A的四個角落處且與框架部分RS1-A接合。在一些實施例中，角落部RS1-B2與突出部RS1-B在實體上隔開。
參考圖6，圖3C中所示的第一環結構RS1與圖6中所示的第一環結構RS1之間的差異在於角落開口OP2的形狀。舉例來說，如圖6中所示，角落開口OP2具有彎曲的輪廓。在示例性實施例中，在與中心開口OP1的四個角落交疊的位置處依照圓形輪廓執行角落挖蝕以形成角落開口OP2。此外，如圖6中所示，在一些實施例中，突出部RS1-B中的每一者包括第一側SD1、第二側SD2、第三側SD3及第四側SD4，其中第三側SD3及第四側SD4具有彎曲的表面。在一些實施例中，除具有框架部分RS1-A及多個突出部RS1-B之外，第一環結構RS1還可包括多個角落部RS1-B2，所述多個角落部RS1-B2位於框架部分RS1-A的四個角落處且與框架部分RS1-A接合。在一些實施例中，角落部RS1-B2與突出部RS1-B在實體上隔開。
參考圖7，圖3C中所示的第一環結構RS1與圖7中所示的第一環結構RS1之間的差異在於角落開口OP2的設計。舉例來說，如圖7中所示，角落開口OP2具有多邊形輪廓。在示例性實施例中，相對於第一方向DR1或第二方向DR2以近似45度角（即，在角落挖蝕期間將正方形形狀轉動45度）在與中心開口OP1的四個角落交疊的位置處依照正方形輪廓執行角落挖蝕，以形成角落開口OP2。此外，在一些實施例中，突出部RS1-B中的每一者包括第一側SD1、第二側SD2、第三側SD3及第四側SD4，其中四個側（SD1、SD2、SD3及SD4）接合在一起以形成梯形輪廓。另外，在一些實施例中，除具有框架部分RS1-A及多個突出部RS1-B之外，第一環結構RS1還可包括多個角落部RS1-B2，所述多個角落部RS1-B2位於框架部分RS1-A的四個角落處且與框架部分RS1-A接合。在一些實施例中，角落部RS1-B2與突出部RS1-B在實體上隔開。
參考圖8，圖3C中所示的第一環結構RS1與圖8中所示的第一環結構RS1之間的差異在於角落開口OP2的數目及設計。如圖8中所示，角落開口OP2具有包括圓滑角落的正方形輪廓。在示例性實施例中，在與中心開口OP1的四個角落的側面對齊的位置處依照包括圓滑角落的正方形輪廓執行角落挖蝕，以形成所述多個角落開口OP2。舉例來說，在所說明的實施例中，兩個角落開口OP2從中心開口OP1的四個角落延伸出。與先前實施例類似，除具有框架部分RS1-A及多個突出部RS1-B之外，第一環結構RS1還可包括多個角落部RS1-B2，所述多個角落部RS1-B2位於框架部分RS1-A的四個角落處且與框架部分RS1-A接合。在一些實施例中，角落部RS1-B2與突出部RS1-B在實體上隔開。
基於圖4到圖8中所示的實施例，應注意的是，角落開口OP2的設計可基於設計要求來調整。舉例來說，可執行各種角落挖蝕方式以形成具有多邊形輪廓、彎曲的輪廓或不規則輪廓的角落開口OP2。通過在中心開口OP1的角落處形成角落開口OP2，可明顯地減小半導體封裝SM中的模塑應力。
圖9是根據本公開的一些示例性實施例的封裝結構的示意性剖面圖。圖9中所示的封裝結構PKS2類似於圖3B中所示的封裝結構PKS1。因此，使用相同的元件符號來表示相同或相似的元件，且本文中將不再對其加以贅述。實施例之間的差異在於使用半導體封裝SM2來取代圖9中的半導體封裝SM。半導體封裝SM2的細節可參考圖2的說明，因此本文中將不再重複。在先前實施例中，第一環結構RS1的各種設計是作為範例使用於半導體封裝SM中。然而，本公開並不僅限於此。舉例來說，可應用第一環結構RS1的各種設計以環繞半導體封裝SM2從而減小半導體封裝SM2的模塑應力。在一些實施例中，第一環結構RS1可環繞重佈線層RDL且部分地環繞絕緣包封體114，而第二環結構RS2可部分地環繞絕緣包封體114及半導體晶粒21、22。
圖10是根據本公開的一些其他示例性實施例的封裝結構的示意性剖面圖。圖10中所示的封裝結構PKS3類似於圖3B中所示的封裝結構PKS1。因此，使用相同的元件符號來表示相同或相似的元件，且本文中將不再對其加以贅述。實施例之間的差異在於圖10中進一步提供蓋結構401。參考圖10，在一些實施例中，蓋結構401可通過第三黏合劑（未示出）貼合到第二環結構RS2。蓋結構401可覆蓋半導體封裝SM，以使得半導體封裝SM位於蓋結構401與線路基底300的中間。在一些實施例中，當提供蓋結構401時，是進一步將熱介面金屬402貼合在半導體封裝SM的背側上。在某些實施例中，熱介面金屬402夾置在蓋結構401與半導體封裝SM的中間，且填滿蓋結構401與半導體封裝SM之間的空間以增強散熱。
在上述實施例中，封裝結構包括設置在線路基底上從而環繞半導體封裝的至少一個第一環結構（第一加強環）及第二環結構（第二加強環）。第一環結構被設計成包括中心開口及通過角落挖蝕而形成的多個角落開口。通過以此方式來設計第一環結構，可明顯地減小半導體封裝的角落處的模塑應力，同時適當地控制封裝結構的翹曲。整體來說，可防止模塑破裂或分層的風險，且可改善封裝結構的可靠性。
根據本公開的一些實施例，一種封裝結構包括線路基底、半導體封裝及第一環結構。所述半導體封裝設置在所述線路基底上且電性連接到所述線路基底。所述第一環結構貼合到所述線路基底且環繞所述半導體封裝，其中所述第一環結構包括中心開口及從所述中心開口的角落延伸出的多個角落開口，所述半導體封裝位於所述中心開口中，且所述多個角落開口環繞所述半導體封裝的角落。
根據本公開的一些其他實施例，一種封裝結構包括線路基底、中介層結構、第一半導體晶粒及多個第二半導體晶粒、絕緣包封體、第一加強環及第二加強環。所述中介層結構設置在所述線路基底上且電性連接到所述線路基底。所述第一半導體晶粒及所述第二半導體晶粒設置在所述中介層結構的背側表面上且電性連接到所述中介層結構。所述絕緣包封體設置在所述中介層結構的所述背側表面上且環繞所述第一半導體晶粒及所述多個第二半導體晶粒。所述第一加強環及所述第二加強環貼合到所述線路基底，其中所述第一加強環位於所述線路基底與所述第二加強環的中間，且所述中介層結構、所述第一半導體晶粒及所述多個第二半導體晶粒被所述第一加強環及所述第二加強環包圍。所述第一加強結構包括框架部分及從所述框架部分的內表面朝所述中介層結構延伸出的多個突出部，且所述多個突出部中的每一者彼此隔開。
根據本公開的一些其他實施例，提供一種包括半導體封裝及環結構的封裝結構。所述半導體封裝設置在基底上。所述環結構設置在所述基底上且環繞所述半導體封裝，其中當所述半導體封裝的第一側壁到所述環結構的內側壁的最小距離為d3、所述半導體封裝的第二側壁到所述環結構的內側壁的最小距離為d4時，則從所述半導體封裝的角落到所述環結構的內角落的最大距離d5滿足以下關係式：d5＞√((d3) 2+(d4) 2)，且所述第一側壁垂直於所述第二側壁。
根據本公開的又一實施例，闡述一種製作封裝結構的方法。所述方法包括以下步驟。提供線路基底。在所述線路基底上設置半導體封裝，且所述半導體封裝電性連接到所述線路基底。將第一環結構貼合到所述線路基底以環繞所述半導體封裝，其中所述第一環結構包括中心開口及從所述中心開口的角落延伸出的多個角落開口，所述半導體封裝位於所述中心開口中，且所述多個角落開口環繞半導體封裝的角落。將第二環結構貼合到所述第一環結構以環繞所述半導體封裝，其中所述第二環結構包括與所述第一環結構的所述中心開口交疊的第二中心開口。
還可包括其他特徵及製程。舉例來說，可包括測試結構，以輔助對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試焊盤，以使得能夠對3D封裝或3DIC進行測試、能夠使用探針及/或探針卡等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包括對已知良好晶粒進行中間驗證的測試方法來使用，以提高良率並降低成本。
以上概述了若干實施例的特徵，以使本領域中的技術人員可更好地理解本公開的各個方面。本領域中的技術人員應理解，其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。本領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下在本文中作出各種改變、代替及變更。
21、22:半導體晶粒 21S、22S、114b:背側表面 100:中介層結構/中介層 100’:中介層結構 101A、116a:介電層 101B:導電層 101C、106:導電焊盤 102:核心部分 102a:第一表面 102b:第二表面 104:穿孔 110:電性連接件 112、350:底部填充結構 114:絕緣包封體 114a、116s:頂表面 116:重佈線結構 116b:金屬化圖案 118:導電端子 211、220:本體 211、221:主動表面 212、222:連接焊盤 300:線路基底/基底 310、320:接觸焊盤 330:金屬化層 340:導電球 401:蓋結構 402:熱介面金屬 AD1:第一黏合劑 AD2:第二黏合劑 Cx:載體 d1:第一寬度 d2:第二寬度 d3、d4:距離 d5:最大距離 DL:切割道 DR1:第一方向 DR2:第二方向 FR:框架 H1:第一厚度 H2:第二厚度 OP1:中心開口 OP2:角落開口 OP3:第二中心開口 PKR:封裝區 PKS1、PKS2、PKS3:封裝結構 PDX:被動元件 RDL:重佈線層 RS1:第一環結構 RS1-A:框架部分 RS1-B:突出部 RS1-B2:角落部 RS2:第二環結構 RS2-A:第二框架部分 RS2-NV:非交疊部 RS2-OV:交疊部 SD1:第一側 SD2:第二側 SD3:第三側 SD4:第四側 SM、SM2:半導體封裝 SM-SD:側表面 TP:條帶 Tx、Ty:厚度
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述的清晰起見，可任意增大或減小各種關鍵特徵的尺寸。 圖1A到圖1I是根據本公開的一些示例性實施例的製作半導體封裝的方法中的各個階段的示意性上視圖及剖面圖。 圖2是根據本公開的一些其他示例性實施例的半導體封裝的示意性剖面圖。 圖3A到圖3D是根據本公開的一些示例性實施例的製作封裝結構的方法中的各個階段的示意性上視圖及剖面圖。 圖4到圖8是根據本公開的各種實施例的第一環結構的上視圖。 圖9是根據本公開的一些示例性實施例的封裝結構的示意性剖面圖。 圖10是根據本公開的一些其他示例性實施例的封裝結構的示意性剖面圖。
d1:第一寬度
d2:第二寬度
d3、d4:距離
d5:最大距離
DR1:第一方向
DR2:第二方向
OP1:中心開口
OP2:角落開口
RS1:第一環結構
RS1-A:框架部分
RS1-B:突出部
SD1:第一側
SD2:第二側
SD3:第三側
SD4:第四側
SM:半導體封裝
SM-SD:側表面

Claims (20)

  1. 一種封裝結構，包括： 線路基底； 半導體封裝，設置在所述線路基底上且電性連接到所述線路基底；以及 第一環結構，貼合到所述線路基底且環繞所述半導體封裝，其中所述第一環結構包括中心開口及從所述中心開口的角落延伸出的多個角落開口，所述半導體封裝位於所述中心開口中，且所述多個角落開口環繞所述半導體封裝的角落。
  2. 如請求項1所述的封裝結構，其中所述第一環結構的所述中心開口是具有四個角落的正方形或矩形開口，且所述多個角落開口從所述正方形或矩形開口的所述四個角落延伸出。
  3. 如請求項2所述的封裝結構，其中所述多個角落開口具有多邊形輪廓、彎曲的輪廓或不規則的輪廓。
  4. 如請求項2所述的封裝結構，其中所述多個角落開口中的兩者從所述正方形或矩形開口的所述四個角落中的每一者延伸出。
  5. 如請求項1所述的封裝結構，其中所述半導體封裝到所述中心開口的邊界的最小距離小於從所述半導體封裝的角落到所述多個角落開口的邊界的最大距離。
  6. 如請求項1所述的封裝結構，更包括： 第二環結構，貼合到所述第一環結構且環繞所述半導體封裝，其中所述第二環結構包括與所述第一環結構的所述中心開口交疊的第二中心開口。
  7. 如請求項6所述的封裝結構，其中所述第一環結構的厚度大於所述第二環結構的厚度。
  8. 如請求項6所述的封裝結構，其中所述第一環結構通過第一黏合劑貼合到所述線路基底，且所述第二環結構通過第二黏合劑貼合到所述第一環結構。
  9. 如請求項6所述的封裝結構，其中所述第一環結構的所述中心開口的輪廓實質上等於所述第二環結構的所述第二中心開口的輪廓。
  10. 一種封裝結構，包括： 線路基底； 中介層結構，設置在所述線路基底上且電性連接到所述線路基底； 第一半導體晶粒及多個第二半導體晶粒，設置在所述中介層結構的背側表面上且電性連接到所述中介層結構； 絕緣包封體，設置在所述中介層結構的所述背側表面上且環繞所述第一半導體晶粒及所述多個第二半導體晶粒； 第一加強環及第二加強環，貼合到所述線路基底，其中所述第一加強環位於所述線路基底與所述第二加強環的中間，且 所述中介層結構、所述第一半導體晶粒及所述多個第二半導體晶粒被所述第一加強環及所述第二加強環包圍，且 其中所述第一加強環包括框架部分及從所述框架部分的內表面朝所述中介層結構延伸出的多個突出部，且所述多個突出部中的每一者彼此隔開。
  11. 如請求項10所述的封裝結構，其中所述第二加強環包括第二框架部分，所述第二框架部分具有交疊部及非交疊部，所述第二框架部分的所述交疊部與所述第一加強環的所述框架部分及所述多個突出部交疊，且所述第二框架部分的所述非交疊部位於所述第二加強環的四個內角落處。
  12. 如請求項10所述的封裝結構，其中所述多個突出部中的每一者包括： 第一側，與所述框架部分接合； 第二側，與所述第一側相對，其中所述第二側包括與所述中介層結構的側表面平行的平坦表面；以及 第三側及第四側，分別將所述第二側接合到所述第一側。
  13. 如請求項12所述的封裝結構，其中所述第三側及所述第四側包括彎曲的表面。
  14. 如請求項12所述的封裝結構，其中所述多個突出部中的每一者的所述第一側、所述第二側、所述第三側及所述第四側接合到一起，以形成矩形輪廓或梯形輪廓。
  15. 如請求項10所述的封裝結構，其中所述第一加強環的厚度大於所述第二加強環的厚度。
  16. 如請求項10所述的封裝結構，其中所述多個第二半導體晶粒是不具有任何電性功能的虛設晶粒。
  17. 一種封裝結構，包括： 半導體封裝，設置在基底上；以及 環結構，設置在所述基底上且環繞所述半導體封裝，其中當所述半導體封裝的第一側壁到所述環結構的內側壁的最小距離為d3、所述半導體封裝的第二側壁到所述環結構的內側壁的最小距離為d4時，則從所述半導體封裝的角落到所述環結構的內角落的最大距離d5滿足以下關係式： d5＞√((d3) 2+(d4) 2)，且 所述第一側壁垂直於所述第二側壁。
  18. 如請求項17所述的封裝結構，其中所述環結構包括框架部分及從所述框架部分的內表面朝所述半導體封裝延伸出的多個突出部，且所述多個突出部中的每一者彼此隔開。
  19. 如請求項18所述的封裝結構，還包括第二環結構，所述第二環結構設置在所述環結構上且環繞所述半導體封裝，其中所述第二環結構包括具有交疊部及非交疊部的第二框架部分，所述第二框架部分的所述交疊部與所述環結構的所述框架部分及所述多個突出部交疊，且所述第二框架部分的所述非交疊部位於所述第二環結構的四個內角落處。
  20. 如請求項19所述的封裝結構，其中所述環結構是由熱膨脹係數比所述第二環結構的材料小的材料製成。
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