TW202226036A - 積體電路晶片介面和佈置其介面的方法 - Google Patents
積體電路晶片介面和佈置其介面的方法 Download PDFInfo
- Publication number
- TW202226036A TW202226036A TW110110498A TW110110498A TW202226036A TW 202226036 A TW202226036 A TW 202226036A TW 110110498 A TW110110498 A TW 110110498A TW 110110498 A TW110110498 A TW 110110498A TW 202226036 A TW202226036 A TW 202226036A
- Authority
- TW
- Taiwan
- Prior art keywords
- interface
- contact elements
- integrated circuit
- group
- contact element
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Theoretical Computer Science (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本發明提供一種積體電路(IC)晶片的介面,所述介面包含形成為對應於平行匯流排的接觸元件圖案的多個接觸元件。接觸元件以列和行的陣列佈置,且劃分成傳輸群組和接收群組。傳輸群組的接觸元件具有第一接觸元件序列,且接收群組的接觸元件具有第二接觸元件序列,第一接觸元件序列與第二接觸元件序列相同。當接觸元件圖案相對於列方向和行方向幾何旋轉180
o時,具有第一接觸元件序列和第二接觸元件序列的接觸元件相匹配。
Description
本發明涉及半導體裝置的製造,且更確切地說,涉及積體電路(integrated circuit, IC)晶片的介面和佈置IC晶片的介面的方法。
基於半導體積體電路的數位電子裝置,例如手機、數碼相機、個人數位助理(personal digital assistant, PDA)等等,其設計成具有更強大的功能性以適應現代數位世界中的各種應用。然而,隨著半導體製造的趨勢,數位電子裝置意圖為更小和更輕,具有改進的功能性和更高性能。半導體裝置可以封裝成2.5D半導體裝置,其中若干電路晶片可以整合為更大的積體電路,其中接觸元件、插入件或重佈線層(Redistribution Layer, RDL)是用在晶片之間的連接。
已提出集成扇出型(Integrated Fan-Out;InFO)和晶粒對晶片對基板(chip-on-wafer-on-substrate;CoWoS)的封裝技術以封裝並排組裝的多個晶片。
關於整個電子電路,主電路可以基於2.5D封裝技術進行製造。另外,多個專用積體電路(application-specific integrated circuit;ASIC)晶片和串行器/解串行器(SerDes)晶片可以通過涉及平行匯流排的互連介面彼此連接地額外安置在主電路上。
將連接的兩個晶片的介面通常分別包含用於彼此連接的接觸元件圖案。晶片的接觸元件圖案包含用於連接到另一晶片的接觸元件的多個接觸元件。如何佈置晶片的接觸元件圖案以改進連接品質仍為一個設計問題。
本發明提供一種積體電路晶片的介面和一種佈置積體電路晶片的介面的方法。接觸元件圖案的接觸元件被配置成具有傳輸群組和接收群組。傳輸群組和接收群組的接觸元件以對稱方式佈置。晶片可容易地安置在插入件或重佈線層層上。
在實一施例中,本發明提供一種積體電路(IC)晶片的介面,所述介面包含形成為對應於平行匯流排的接觸元件圖案的多個接觸元件。所述接觸元件以列和行的陣列佈置,且劃分成傳輸群組和接收群組。傳輸群組的接觸元件具有第一接觸元件序列,且接收群組的接觸元件具有第二接觸元件序列,第一接觸元件序列與第二接觸元件序列相同。當接觸元件圖案相對於列方向和行方向幾何旋轉180
o時,具有第一接觸元件序列和第二接觸元件序列的接觸元件相匹配。
在實一施例中,本發明提供一種用於佈置積體電路(IC)晶片的介面的方法。本發明包含將多個接觸元件配置成形成為對應於平行匯流排的接觸元件圖案,其中接觸元件以列和行的陣列佈置且劃分成傳輸群組和接收群組。傳輸群組的接觸元件分配有第一接觸元件序列,且接收群組的接觸元件分配有第二接觸元件序列。第一接觸元件序列與第二接觸元件序列相同。當接觸元件圖案相對於列方向和行方向幾何旋轉180
o時,具有第一接觸元件序列和第二接觸元件序列的接觸元件相匹配。
為了可更好地理解前述內容,如下參考圖式詳細地描述若干實施例。
本發明涉及2.5D半導體裝置的介面,其中晶片安置於插入件或重佈線層層上。晶片的接觸元件圖案配置成具有幾何對稱關係。晶片通過介面更自由地連接。接觸元件之間的佈線長度也可以更均等且更短地設置。
以下提供了若干實施例用於描述本發明,但本發明並不僅受限於所述實施例。
圖1是根據本發明的實施例示意性地示出具有介面的2.5D半導體裝置的截面堆疊結構的圖。參考圖1,在另一應用中,基於2.5D封裝技術形成具有預期IC結構的CoWoS或InFO平臺50。CoWoS或InFO平臺50可包含具有底部焊球104和頂部C4接觸元件106的封裝襯底100。通孔102可用於從底部焊球104連接到頂部接觸元件106。此外,可進一步在襯底100上形成與C4接觸元件106連接的插入件或重佈線層層110。插入件或重佈線層層110還可包含矽穿孔(Through-Silicon-Via, TSV) 112、互連佈線114以及接觸元件116。此處,視所採用的製造工藝而定,接觸元件116可為通孔或凸塊焊盤或用於端子到端子接觸的任何合適的連接結構。本發明並未將接觸元件106限制為特定類型。
在實際應用中,也可以使用額外晶片,例如ASIC晶片130和SerDes晶片120來實施CoWoS或InFO平臺50。ASIC晶片130和SerDes晶片120通過佈線114和介面連接。一個ASIC晶片130可與多個SerDes晶片120連接以用於各種週邊通信。
圖2是根據本發明的實施例示意性地示出一個晶片通過介面連接到多個其他晶片的介面的圖。參考圖2,一個IC晶片200(例如處理器或ASIC晶片)可通過介面204與多個晶片202連接。介面204以在晶片200與晶片202之間涉及平行匯流排進行通信。介面204可包含佈線和接觸元件圖案中的接觸元件,從而使得晶片200可連接到晶片202。
圖3是根據本發明的實施例示意性地示出用於多個處理器晶片之間的連接的介面的圖。參考圖3,在另一應用中,多個處理器200'可連接在一起以形成具有更強大功能的大型處理器。在這種情況下,這些處理器200'也通過介面204進行連接。
如前文描述,2.5D封裝工藝可應用於將各種晶片並排堆疊在一起而不實質上進一步消耗裝置區域。然而,為了允許晶片更自由地連接在一起,需要以緊湊的方式適當地佈置介面204中的接觸元件並且進一步對稱以用於接收和傳輸信號。兩個晶片200到晶片202之間的通信可容易地安置在週邊區。此處,介面204也可以是指市場上所提供的Glink介面。
圖4是根據本發明的實施例示意性地示出接觸元件圖案的結構的圖。參考圖4,介面中所涉及的接觸元件的總數可以是並行地通信以用於傳輸和接收的信號的數目。
介面中所涉及的接觸元件的總數可以是較大的數目。信號在晶片之間並行地通信以用於傳輸和接收。取決於一個匯流排中的資料大小,具有操作電壓和其他功能信號的32位元資料大小是設置成為一個圖塊,如接觸元件圖案300的一個電路片。接觸元件圖案300可以以某一數目(例如8)來複製,以適應並行通信的總數據大小。在實例中,資料對應於具有R_D0到R_D31和T_D0到T_D31的序列的32位,在所述序列上,T表示用於傳輸的接觸元件且R表示用於接收的接觸元件。另外,接觸元件圖案300中還包含多個低電壓信號VSS和多個高電壓VDDP。另外,還包含各種功能信號,包含幀 T/R_FR;時脈T/R_DCKP/N;流量控制T/R_FC[1:0];DBI T/R_DBI [3:0];同位T/R_PAR;以及通路修復T/R_LR[1:0]。然而,用於功能信號的接觸元件不僅限於所述實施例。
表1是定義一個傳輸(T)群組或接收(R)群組的接觸元件的實例。傳輸群組和接收群組具有相同數目個接觸元件。
表1
接觸元件類型 | 數目 | 定義 |
數據,T/R [31:0] | 32 | 與CLK同步的資料位元 |
幀,T/R_幀 | 1 | 與CLK同步的幀位 |
時脈,T/R_DCK_P/N | 2 | CLK差分對 |
流量控制,T/R_FC[1:0] | 2 | 與資料匯流排非同步且呈不同方向 |
DBI,T/R_DBI[3:0] | 4 | 每位元組一個DBI,用於使匯流排內容反轉以用於更好的單點登錄(single sign-on, SSO) |
同位,T/R_PAR | 1 | 每32位元一個,用於識別錯誤情況 |
通路修復,T/R_LR[1:0] | 2 | 通路修復位元,用於修復資料、同位以及DBI,不用於修復CLK、幀以及FC信號 |
如所提及,每一接觸元件用使用時的功能特定地定義,以便形成接觸元件序列。接觸元件序列包含資料接觸元件和各種功能接觸元件。在實例中,接觸元件圖案包含8個列和15個行以形成規則正方形或矩形形狀的陣列。
圖5是根據本發明的實施例示意性地示出接觸元件圖案於傳輸群組和接收群組中的配置的圖。參考圖5,接觸元件被配置成具有多個列和多個行的陣列,所述陣列形成為對應於用以傳輸信號和接收信號的平行匯流排的接觸元件圖案300。接觸元件圖案300中的接觸元件以列和行的陣列佈置,且劃分成傳輸群組302和接收群組304。傳輸群組302的接觸元件由“T_”標示,且接收群組304的接觸元件由「R_」標示。
在實一施例中,列數N為奇數或偶數。在實一施例中,以8列作為實例。行數M也可為奇數或偶數。在實一施例中,以15行作為實例。為了具有緊密佈置,中心行可劃分成用於傳輸群組302和接收群組304的兩個部分。一般來說,在實一施例中,N和M可為偶數或奇數。在實一施例中,N為偶數且M為奇數。在實一施例中,N為奇數且M為偶數。
然而,本發明不僅限於所述實施例。在實一施例中,也可利用虛設接觸元件來分開傳輸群組302和接收群組304。換句話說,行數可為偶數,其中可額外添加虛設接觸元件以明確地分開傳輸群組302和接收群組304。本發明不限於所述實施例。
針對傳輸群組302和接收群組304分配接觸元件的原則是使得傳輸群組302與接收群組304對稱。忽略傳輸標示“T_”和接收標示“R_”,傳輸群組302和接收群組304的接觸元件序列相同。換句話說,當接觸元件圖案300以列方向作為旋轉軸旋轉180
o且接觸元件圖案300以行方向作為旋轉軸進一步旋轉180
o時,接觸元件序列相同。
在實例中,以接收群組304的左上角處的接觸元件R_DBI3作為實例,在旋轉後,所述接觸元件將與傳輸群組302的接觸元件T_DBI3匹配。因此,一個晶片的接觸元件序列中的傳輸接觸元件與另一晶片的接收接觸元件匹配。
圖6是根據本發明的實施例示意性地示出晶片之間的連接的圖。參考圖6,基於接觸元件圖案300用於一個介面電路片H,實際介面包含用於一個介面250的多個介面電路片H。在實例中,利用如由Glink0至Glink N所標示的N個介面來進行描述。晶片210可包含多個介面250以用於與晶片212的不同通信。在實一施例中,以一個晶片210和另一晶片212作為實例。晶片210包含Glink0至Glink N 250的多個介面250。晶片212也包含Glink0至Glink N的多個介面250。在實例中,介面250(Glink0至Glink N)中的每一介面可包含8個介面電路片H。每一介面電路片H具有接觸元件圖案300,其中接觸元件成對稱佈置。根據實際需要,可在介面電路片H之間的中心處實施額外功能電路片306。在實例中,功能電路片306可與用於驗證時序信號的鎖相環(phase locked loop, PLL)有關。在實一施例中,本發明不僅限於功能電路片306。
當晶片212在封裝工藝中安置於主晶片上時,可使晶片212相對於軸線400旋轉180
o,其中具有對稱佈置的晶片212的接觸元件圖案仍可容易地與晶片210的接觸元件圖案匹配。在實例中,晶片210的介面Glink0與晶片212的介面GlinkN匹配。類似地,晶片210的介面Glink1與晶片212的介面GlinkN-1匹配,等等。換句話說,即使晶片212因封裝工藝需要而旋轉,晶片210的每一電路片H的接觸元件圖案仍允許接觸元件與另一晶片212的電路片H匹配。
此外,軸線400可沿X軸方向或Y軸方向延伸。另外,根據作為實例的圖2和圖3,可涉及沿X軸方向和Y軸方向兩個延伸的多個軸線400。然而,仍保持接觸元件圖案的對稱性質。
圖7是根據本發明的實施例示意性地示出具有對稱接觸元件圖案的兩個連接晶片的接觸元件之間的連接關係的圖。參考圖7,以晶片210和晶片212的一個鍵合圖案300作為實例來進一步描述,示出具有如在接觸元件圖案300中指定的接觸元件序列的接觸元件之間的跡線路徑。
歸因於對稱性質,晶片212的接觸元件圖案300的接觸元件序列由於如在封裝工藝中所需的旋轉而與晶片210的接觸元件圖案300的接觸元件序列相同,預期傳輸群組“T_”對應於接收群組“R_”。在實例中,晶片210的接觸元件T_D0連接至晶片212的接觸元件R_D0,且晶片210的接觸元件R_D6連接至晶片212的接觸元件T_D6。
圖8是根據本發明的實施例示意性地示出具有對稱接觸元件圖案的兩個連接晶片之間的佈線效果的圖。參考圖7和圖8,晶片210和晶片212的接觸元件之間的跡線路徑310可保持大體上相同長度。接觸元件圖案的這些特徵可具有優點。由於相同的連接長度,來自GLink TX的同步平行匯流排完全同步地到達GLink RX,位之間具有最小時間差。此情形允許GLink RX接收器同步地採樣平行匯流排,且在高頻率下實現高品質採樣。
如同樣參考圖3,晶片210可為ASIC晶片130,且晶片212可為SerDes晶片120。在實例中也可採用圖2和圖3中的連接。
本發明提供具有對稱佈置的接觸元件圖案。
在實一施例中,本發明提供一種積體電路(IC)晶片的介面,所述介面包含形成為對應於平行匯流排的接觸元件圖案的多個接觸元件。所述接觸元件以列和行的陣列佈置,且劃分成傳輸群組和接收群組。傳輸群組的接觸元件具有第一接觸元件序列,且接收群組的接觸元件具有第二接觸元件序列。第一接觸元件序列與第二接觸元件序列相同。當接觸元件圖案相對於列方向和行方向幾何旋轉180
o時,具有第一接觸元件序列和第二接觸元件序列的接觸元件相匹配。
在實一施例中,本發明提供一種用於佈置積體電路(IC)晶片的介面的方法。本發明包含將多個接觸元件配置成形成為對應於平行匯流排的接觸元件圖案,其中接觸元件以列和行的陣列佈置且劃分成傳輸群組和接收群組。傳輸群組的接觸元件分配有第一接觸元件序列,且接收群組的接觸元件分配有第二接觸元件序列。第一接觸元件序列與第二接觸元件序列相同。當接觸元件圖案相對於列方向和行方向幾何旋轉180
o時,具有第一接觸元件序列和第二接觸元件序列的接觸元件相匹配。
在實一施例中,傳輸群組和接收群組中的每一個包含一組資料接觸元件和多個功能接觸元件以及電壓接觸元件。
在實一施例中,傳輸群組和接收群組沿列方向位於接觸元件圖案的兩側且接合在一起。
在實一施例中,接觸元件圖案具有呈正方形形狀或矩形形狀的N個列和M個行。在實一施例中,N和M可為偶數或奇數。在實一施例中,N為偶數且M為奇數。在實一施例中,N為奇數且M為偶數。
在實一施例中,接觸元件圖案的中心行均等地劃分成用於傳輸群組和接收部分的兩個部分。
在實一施例中,N等於8且M等於15,以用於傳輸/接收具有32位元大小的資料。
在實一施例中,介面包含多個接觸元件圖案。
在實一施例中,介面包含多個介面電路片,且介面電路片中的每一者包括接觸元件圖案。
對於所屬領域的技術人員將顯而易見的是,可在不脫離本公開的範圍或精神的情況下對所公開的實施例進行各種修改和變化。鑒於前述內容,希望本公開涵蓋修改和變化,只要所述修改和變化屬於所附權利要求書和其等效物的範圍內。
50:平臺
100:封裝襯底
102:通孔
104:底部焊球
106:頂部接觸元件
110:插入件或重佈線層
112:矽穿孔
114:互連佈線
116:接觸元件
120:串行器/解串行器晶片
130:專用積體電路晶片
200:積體電路晶片
200':處理器
202、210、212:晶片
204、250:介面
300:接觸元件圖案
302:傳輸群組
304:接收群組
306:功能電路片
310:跡線路徑
400:軸線
圖1是根據本發明的實施例示意性地示出具有介面的2.5D半導體裝置的截面堆疊結構的圖。
圖2是根據本發明的實施例示意性地示出一個晶片通過介面連接到多個其他晶片的介面的圖。
圖3是根據本發明的實施例示意性地示出用於多個晶片之間的連接的介面的圖。
圖4是根據本發明的實施例示意性地示出接觸元件圖案的結構的圖。
圖5是根據本發明的實施例示意性地示出接觸元件圖案於傳輸群組和接收群組中的配置的圖。
圖6是根據本發明的實施例示意性地示出晶片之間的連接的圖。
圖7是根據本發明的實施例示意性地示出具有對稱接觸元件圖案的兩個連接晶片的接觸元件之間的連接關係的圖。
圖8是根據本發明的實施例示意性地示出具有對稱接觸元件圖案的兩個連接晶片之間的佈線效果的圖。
300:接觸元件圖案
302:傳輸群組
304:接收群組
Claims (20)
- 一種積體電路晶片的介面,包括: 多個接觸元件,形成為對應於平行匯流排的接觸元件圖案,其中所述接觸元件以列和行的陣列佈置且劃分成傳輸群組和接收群組, 其中所述傳輸群組的接觸元件具有第一接觸元件序列,且所述接收群組的接觸元件具有第二接觸元件序列,所述第一接觸元件序列與所述第二接觸元件序列相同, 其中當所述接觸元件圖案相對於列方向和行方向幾何旋轉180 o時,具有所述第一接觸元件序列和所述第二接觸元件序列的所述接觸元件相匹配。
- 如請求項1所述的積體電路晶片的介面,其中所述傳輸群組和所述接收群組中的每一者包含一組資料接觸元件和多個功能接觸元件以及電壓接觸元件。
- 如請求項1所述的積體電路晶片的介面,其中所述傳輸群組和所述接收群組沿列方向位於所述接觸元件圖案的兩側且接合在一起。
- 如請求項3所述的積體電路晶片的介面,其中所述接觸元件圖案具有呈正方形形狀或矩形形狀的N個列和M個行,其中所述N和所述M為整數。
- 如請求項4所述的積體電路晶片的介面,其中所述N和所述M為偶數或奇數。
- 如請求項4所述的積體電路晶片的介面,其中所述N為偶數且所述M為奇數,或所述N為奇數且所述M為偶數。
- 如請求項6所述的積體電路晶片的介面,其中所述接觸元件圖案的中心行均等地劃分成用於所述傳輸群組和所述接收部分的兩個部分。
- 如請求項7所述的積體電路晶片的介面,其中所述N等於8且所述M等於15,以用於傳輸/接收具有32位元大小的資料。
- 如請求項1所述的積體電路晶片的介面,其中所述介面包含多個所述接觸元件圖案。
- 如請求項1所述的積體電路晶片的介面,其中所述介面包含多個介面電路片,且所述介面電路片中的每一者包括所述接觸元件圖案。
- 一種用於佈置積體電路晶片的介面的方法,包括: 將多個接觸元件配置成形成為接觸元件圖案,其對應於平行匯流排,其中所述接觸元件以列和行的陣列佈置且劃分成傳輸群組和接收群組;以及 對所述傳輸群組的接觸元件分配出第一接觸元件序列,且對所述接收群組的接觸元件分配出第二接觸元件序列,其中所述第一接觸元件序列與所述第二接觸元件序列相同, 其中當所述接觸元件圖案相對於列方向和行方向幾何旋轉180 o時,具有所述第一接觸元件序列和所述第二接觸元件序列的所述接觸元件相匹配。
- 如請求項11所述的用於佈置積體電路晶片介面的方法,其中所佈置的所述傳輸群組和所述接收群組中的每一者包含一組資料接觸元件和多個功能接觸元件以及電壓接觸元件。
- 如請求項11所述的用於佈置積體電路晶片介面的方法,其中所述傳輸群組和所述接收群組沿列方向位於所述接觸元件圖案的兩側且接合在一起。
- 如請求項13所述的用於佈置積體電路晶片介面的方法,其中所佈置的所述接觸元件圖案具有呈正方形形狀或矩形形狀的N個列和M個行,其中所述N和所述M為整數。
- 如請求項14所述的用於佈置積體電路晶片介面的方法,其中所述N和所述M被配置成具有偶數或奇數。
- 如請求項14所述的用於佈置積體電路晶片介面的方法,其中所述N被配置為偶數且所述M被配置為奇數,或所述N被配置為奇數且所述M被配置為偶數。
- 如請求項16所述的用於佈置積體電路晶片介面的方法,其中所述接觸元件圖案的中心行均等地劃分成用於所述傳輸群組和所述接收部分的兩個部分。
- 如請求項17所述的用於佈置積體電路晶片介面的方法,其中所述N等於8且所述M等於15,以用於傳輸/接收具有32位元大小的資料。
- 如請求項11所述的用於佈置積體電路晶片介面的方法,其中所述介面包含多個所述接觸元件圖案。
- 如請求項11所述的用於佈置積體電路晶片介面的方法,其中所述介面包含多個介面電路片,且所述介面電路片中的每一個包括所述接觸元件圖案。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/134,534 US11742295B2 (en) | 2020-12-28 | 2020-12-28 | Interface of integrated circuit die and method for arranging interface thereof |
US17/134,534 | 2020-12-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202226036A true TW202226036A (zh) | 2022-07-01 |
TWI806024B TWI806024B (zh) | 2023-06-21 |
Family
ID=82119625
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110110498A TWI806024B (zh) | 2020-12-28 | 2021-03-24 | 積體電路晶片介面和佈置其介面的方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11742295B2 (zh) |
CN (1) | CN114692547A (zh) |
TW (1) | TWI806024B (zh) |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5629950A (en) * | 1992-04-24 | 1997-05-13 | Digital Equipment Corporation | Fault management scheme for a cache memory |
US7544977B2 (en) * | 2006-01-27 | 2009-06-09 | Hewlett-Packard Development Company, L.P. | Mixed-scale electronic interface |
US8653646B2 (en) * | 2011-10-03 | 2014-02-18 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
WO2013052372A2 (en) | 2011-10-03 | 2013-04-11 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US9267988B2 (en) | 2013-03-14 | 2016-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | On-chip eye diagram capture |
US8786069B1 (en) * | 2013-03-15 | 2014-07-22 | Invensas Corporation | Reconfigurable pop |
US10152445B2 (en) | 2015-02-17 | 2018-12-11 | Mediatek Inc. | Signal count reduction between semiconductor dies assembled in wafer-level package |
US10515939B2 (en) * | 2015-02-17 | 2019-12-24 | Mediatek Inc. | Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method |
US10037293B2 (en) | 2015-02-17 | 2018-07-31 | Nephos (Hefei) Co. Ltd. | Wafer-level package having asynchronous FIFO buffer used to deal with data transfer between different dies and associated method |
US9934179B2 (en) | 2015-02-17 | 2018-04-03 | Mediatek Inc. | Wafer-level package with at least one input/output port connected to at least one management bus |
JP6500736B2 (ja) * | 2015-10-14 | 2019-04-17 | 富士通株式会社 | 半導体装置および半導体装置の制御方法 |
GB2569844B (en) | 2017-10-20 | 2021-01-06 | Graphcore Ltd | Sending data off-chip |
DE102018106508B4 (de) | 2017-11-30 | 2020-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid-interconnect-bauelement und verfahren |
US10746923B2 (en) | 2018-06-27 | 2020-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photonic semiconductor device and method |
KR102530321B1 (ko) * | 2018-12-21 | 2023-05-09 | 삼성전자주식회사 | 반도체 패키지 및 이를 포함하는 전자 기기 |
US11417628B2 (en) * | 2018-12-26 | 2022-08-16 | Ap Memory Technology Corporation | Method for manufacturing semiconductor structure |
DE102020119103A1 (de) | 2019-09-19 | 2021-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Photonische halbleitervorrichtung und herstellungsverfahren |
-
2020
- 2020-12-28 US US17/134,534 patent/US11742295B2/en active Active
-
2021
- 2021-03-24 TW TW110110498A patent/TWI806024B/zh active
- 2021-03-24 CN CN202110314311.5A patent/CN114692547A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
TWI806024B (zh) | 2023-06-21 |
US20220208684A1 (en) | 2022-06-30 |
US11742295B2 (en) | 2023-08-29 |
CN114692547A (zh) | 2022-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US12033982B2 (en) | Fully interconnected heterogeneous multi-layer reconstructed silicon device | |
EP3828928B1 (en) | Embedded multi-die interconnect bridge with improved power delivery | |
US8008764B2 (en) | Bridges for interconnecting interposers in multi-chip integrated circuits | |
US9087765B2 (en) | System-in-package with interposer pitch adapter | |
TW201944574A (zh) | 用於實施可擴充系統之系統及方法 | |
US9349707B1 (en) | Contact arrangements for stackable microelectronic package structures with multiple ranks | |
US20110309468A1 (en) | Semiconductor chip package and method of manufacturing the same | |
TWI755331B (zh) | 處理晶粒與記憶體晶粒之間的通信介面結構 | |
CN114641860A (zh) | 多芯片堆叠器件 | |
Tummala et al. | Heterogeneous and homogeneous package integration technologies at device and system levels | |
US11842986B1 (en) | Multi-chip module (MCM) with interface adapter circuitry | |
WO2022132232A1 (en) | Clock tree routing in a chip stack | |
CN113451260A (zh) | 一种基于系统总线的三维芯片及其三维化方法 | |
CN117577614A (zh) | 芯片封装结构、方法及电子设备 | |
TWI806024B (zh) | 積體電路晶片介面和佈置其介面的方法 | |
WO2016123607A2 (en) | Contact arrangements for stackable microelectronic package structures | |
TW202308071A (zh) | 半導體封裝 | |
US9337170B1 (en) | Contact arrangements for stackable microelectronic package structures | |
TW202236924A (zh) | 晶片之間的佈線結構及晶片之間的佈線方法 | |
CN217847954U (zh) | 封装结构 | |
TWI773244B (zh) | 積體電路封裝、形成積體電路封裝之方法及在積體電路封裝中分配電力之方法 | |
CN221352759U (zh) | 晶圆键合布局结构及三维集成电路芯片 | |
US20240038721A1 (en) | Semiconductor devices and methods of manufacturing thereof | |
TWI690029B (zh) | 重組態之寬輸入輸出記憶體模組及使用其之封裝架構 | |
TW202404005A (zh) | 通信介面結構和晶粒對晶粒封裝 |