TW202224033A - 晶片封裝方法以及晶片封裝單元 - Google Patents
晶片封裝方法以及晶片封裝單元 Download PDFInfo
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Abstract
本發明提出一種晶片封裝方法,包含:提供一晶圓,晶圓上包含多個凸點;切割晶圓為多個晶片,並覆蓋晶片於一底材上,其中在晶圓或晶片上設置多個垂直導熱結構;以及提供一封裝材料,以封裝各晶片的側邊以及各晶片中面對底材的底面,以形成各晶片封裝單元。晶片封裝單元中,晶片上的凸點抵接於底材,其中垂直導熱結構通過底材中多個貫穿孔、或者直接連接底材。
Description
本發明係有關一種晶片封裝方法,特別是指一種藉由打線(Wiring)方式產生的多個垂直導熱結構,以加強晶片散熱能力的晶片封裝方法。
先前技術中,參照圖1,其顯示美國專利案US 9984992的晶片封裝結構,其中包含兩晶片,下方晶片CH設置於底材110上,位於多個打線材100所環繞形成的法拉第籠(Faraday cage)中,其形成一內部電磁保護結構。打線材100設置於底材110上,與底材110中線路相連,為封裝材料120所包覆,此為防電磁感擾設計。
參照圖2,其顯示美國專利案US 9812402的晶片封裝結構。類似於圖1,圖2的打線材100環繞形成一法拉第籠,打線材100與底材110中線路相連,以形成防電磁感擾設計。
又參照圖3,其中顯示美國專利案US 7355289的晶片封裝結構,其中為加強晶片CH的熱傳導,在晶片CH上形成多個打線材100,以加強晶片CH散熱效果。其中打線材100外露於晶片CH上方的封裝材料120外側。此設計雖考慮散熱需求,但打線材100離底板距離遠,其各別外露面積小,散熱效果有限,且晶片CH受限於打線式(Wire bond)的引線連接方式,其應用時較受限。
針對先前技術,本發明提供一晶片封裝技術,其具有散熱能力佳、製造容易、應用範圍廣等優點。
就其中一個觀點言,本發明提供了一種晶片封裝方法,以解決前述之困擾。此晶片封裝方法包含:提供一晶圓,晶圓上包含多個凸點;切割晶圓為多個晶片,並覆蓋晶片於一底材上,其中在晶圓或晶片上設置多個垂直導熱結構;以及提供一封裝材料,以封裝各晶片的側邊以及各晶片中面對底材的底面,以形成多個晶片封裝單元。晶片封裝單元中,晶片上的凸點抵接於底材,垂直導熱結構通過底材中多個貫穿孔、或者直接連接底材。
在一些實施例中,切割晶圓為多個晶片、設置晶片於底材上、以及其中設置垂直導熱結構於晶圓或從晶圓切割的多個晶片上的步驟中,可依需要有不同的實施方式:切割晶圓為多個晶片,之後,在各晶片上設置多個垂直導熱結構,之後,以及覆蓋各晶片於底材上;或者,在晶圓上設置多個垂直導熱結構,之後,切割晶圓為多個晶片,其中各晶片上包含多個垂直導熱結構,之後,並覆蓋各晶片於底材上;或者,切割晶圓為多個晶片,之後,覆蓋各晶片於底材上,之後,並在各晶片上設置多個垂直導熱結構,以連接底材。
一實施例中,垂直導熱結構為藉由在晶圓上進行打線(Wire bond)所產生的引線,垂直導熱結構為往垂直方向拉直引線所形成。一實施例中,垂直導熱結構設置於晶圓上無功能墊(No connective pad)。
一實施例中,晶片與底材間,具有覆晶式(Flip chip)的引線連接方式。一實施例中,底材為一引線框架(Lead frame)。
就其中一個觀點言,本發明提供了一種晶片封裝單元,包含:一引線框架;一晶片,包含多個凸點與多個垂直導熱結構,凸點與垂直導熱結構位於晶片的同一側,晶片設置於引線框架上,垂直導熱結構通過引線框架中多個貫穿孔、或直接連接引線框架;以及一封裝材料,封裝晶片的側邊以及晶片中面對引線框架的底面。
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明中的圖式均屬示意,主要意在表示各電路組成部分間之相互關係,至於形狀與尺寸則並未依照比例繪製。
圖4A至4E顯示本發明的一個實施例。根據本發明之晶片封裝方法包括:提供一晶圓WF,晶圓WF上包含多個凸點130(圖4A);之後,從晶圓WF切割的多個晶片CH上(圖4B),設置多個垂直導熱結構140(圖4C),之後,並覆蓋晶片CH於一底材110上(圖4D);之後,以及提供一封裝材料120,以封裝各晶片CH的側邊以及各晶片CH中面對底材110的底面,以形成多個晶片封裝單元10(圖4E)。晶片封裝單元10中,晶片CH上的凸點130抵接於底材110,垂直導熱結構140通過底材110中多個貫穿孔、或者直接連接底材110。其中,每個晶片CH上包括至少一個凸點130。
圖5A至5E顯示本發明的另一個實施例。本發明之晶片封裝方法包括:提供一晶圓WF,晶圓WF上包含多個凸點130(圖5A);之後,在晶圓WF上設置多個垂直導熱結構140後切割為多個晶片CH(圖5B、5C),之後,並覆蓋晶片CH於一底材110上(圖5D);之後,以及提供一封裝材料120,以封裝各晶片CH的側邊以及各晶片CH中面對底材110的底面,以形成多個晶片封裝單元10(圖5E)。晶片封裝單元10中,晶片CH上的凸點130抵接於底材110,垂直導熱結構140通過底材110中多個貫穿孔、或者直接連接底材110。其中,每個晶片CH上包括至少一個凸點130。
在一實施例中,凸點130包含晶片CH與底材110間連接訊號的一互連結構,其可為錫球或其他方式構成。
一些實施例中,前述的切割晶圓WF為多個晶片CH、設置晶片CH於底材110上、以及其中設置垂直導熱結構140於晶圓WF上或晶圓WF切割的多個晶片CH上的步驟中,可依需要有不同的實施方式:
(1)切割晶圓WF為多個晶片CH(圖4A、4B),之後,在各晶片CH上設置多個垂直導熱結構140(與凸點130在晶片CH的同一側,圖4C),之後,以及覆蓋各晶片CH於底材110上(圖4D)。
(2)在晶圓WF上設置多個垂直導熱結構140 (與凸點130在晶片CH的同一側,圖5A、5B),之後,切割晶圓WF為多個晶片CH(圖5C),各晶片CH上包含多個垂直導熱結構140,之後,並覆蓋各晶片CH於底材110上(圖5D)。
(3)切割晶圓WF為多個晶片CH,之後,覆蓋各晶片CH於底材110上,之後,並在各晶片CH上設置多個垂直導熱結構140(可與凸點在晶片CH的同側或不同側),以連接底材110(例如圖6中,垂直導熱結構140連接底材110,用以增加傳熱至底材110的效率)。若需要,可根據前述三種方式中部分特徵進行組合,例如結合(1)、(2)實施方式中,其中晶圓WF與晶片CH皆設置垂直導熱結構140等。
一實施例中,垂直導熱結構140為藉由在晶圓WF上進行打線(Wire bond)所產生的引線,垂直導熱結構140為往垂直方向拉直引線所形成。一實施例中,垂直導熱結構140設置於晶圓WF上無功能墊(No connective pad),此無功能墊與晶片間無訊號連接。
封裝材料120為適用於包覆晶片的材料,其包覆性良好,散熱效果一般。垂直導熱結構140的熱傳係數較高於封裝材料120,透過垂直導熱結構140,形成晶片CH與晶片封裝單元10、20的外部間的熱傳路徑(圖4F、6B,其中虛線箭頭示意的熱傳路徑)。一實施例中,垂直導熱結構的材料包含銅、鋁、銀、鎳、或複合金屬材料,例如銅合金、銀合金等。
參照圖4D、4E,垂直導熱結構140的一側外露於晶片封裝單元10的表面,此設計為藉由垂直導熱結構140或與垂直導熱結構140所通過底材110的貫穿孔,以向外傳遞熱。晶片CH上的凸點130抵接於底材110(可形成訊號連接),垂直導熱結構140的高度較高於凸點130通過貫穿孔,封裝材料120填充垂直導熱結構140與貫穿孔間的空隙,其中的垂直導熱結構140與底材110十分靠近,底材110通過封裝材料120仍具有相當程度的間接輔助散熱效果。或者,垂直導熱結構140連接底材110(圖6),藉由底材110以形成晶片CH與晶片封裝單元20的外部間的熱傳路徑。換言之,晶片封裝單元10、20中,晶片CH的主要熱傳方向之一為朝向底材110的方向。
一實施例中,晶片CH與底材110間,具有覆晶式(Flip chip)的引線連接方式。一實施例中,底材110為一引線框架(Lead frame)。一些實施例中,封裝方式例如:方形扁平無引腳封裝 (Quad Flat No-Lead,QFN)、雙側扁平無引腳封裝 (Dual Flat No-Lead,DFN)、小外型電晶體封裝 (Small Outline Transistor,SOT)或小外型封裝 (Small Out-Line Package,SOP)等。舉例而言,其中,在底材110為一引線框架的實施例中,垂直導熱結構140例如為導線,由晶片CH向外貫穿引線框架複數的接腳(lead)間的縫隙。
參照圖4E、6A,就其中一個觀點言,本發明提供了一種晶片封裝單元10、20,包含:一引線框架110;一晶片CH,包含多個凸點130與多個垂直導熱結構140,凸點130與垂直導熱結構140位於晶片CH的同一側,晶片CH設置於引線框架110上,垂直導熱結構140通過引線框架110中多個貫穿孔、或直接連接引線框架110;以及一封裝材料120,封裝晶片CH的側邊以及晶片CH中面對引線框架110的底面。
以上已針對實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如,本發明之用語「耦接」包括直接連接與間接連接。本發明的範圍應涵蓋上述及其他所有等效變化。
10,20:晶片封裝單元
100:打線材
110:底材
120:封裝材料
130:凸點
140:垂直導熱結構
CH:晶片
WF:晶圓
圖1、2、3顯示先前技術中晶片封裝結構的示意圖。
圖4A至4F顯示根據本發明一實施例中晶片封裝方法的示意圖。
圖5A至5F顯示根據本發明另一實施例中晶片封裝方法的示意圖。
圖6A、6B顯示與本發明一實施例的晶片封裝單元的示意圖
10:晶片封裝單元
110:底材
120:封裝材料
130:凸點
140:垂直導熱結構
CH:晶片
Claims (15)
- 一種晶片封裝方法,包含: 提供一晶圓,該晶圓上包含多個凸點; 切割該晶圓為多個晶片,並覆蓋該些晶片於一底材上,其中在該晶圓或該些晶片上設置多個垂直導熱結構;以及 提供一封裝材料,以封裝各該晶片的側邊以及各該晶片中面對該底材的底面,以形成各晶片封裝單元; 其中,各該晶片封裝單元中,該些晶片上的該些凸點抵接於該底材,該些垂直導熱結構通過該底材中多個貫穿孔或者直接連接該底材。
- 如請求項1所述之晶片封裝方法,其中前述的切割該晶圓為該些晶片,覆蓋該些晶片於該底材上,其中在該晶圓或該些晶片上設置該些垂直導熱結構的步驟,包含:切割該晶圓為該些晶片,之後,在各該晶片上設置多個該垂直導熱結構,之後,以及覆蓋該些晶片於該底材上;或者,在該晶圓上設置該些垂直導熱結構,之後,切割該晶圓為該些晶片,各該晶片包含多個該垂直導熱結構,之後,並覆蓋該些晶片於該底材上;或者,切割該晶圓為該些晶片,之後,覆蓋該些晶片於該底材上,之後,並在各該晶片上設置多個該垂直導熱結構,以連接該底材。
- 如請求項1所述之晶片封裝方法,其中該些垂直導熱結構為藉由在該晶圓上進行打線(Wiring)所產生的引線,該些垂直導熱結構為往垂直方向拉直該引線所形成。
- 如請求項3所述之晶片封裝方法,其中該些垂直導熱結構為於該晶圓上無功能墊(No connective pad)進行打線所產生。
- 如請求項1所述之晶片封裝方法,其中該些垂直導熱結構的一側外露於該些晶片封裝單元的表面,或者該些垂直導熱結構連接該底材,以形成各該晶片與各該晶片封裝單元的外部間的熱傳路徑。
- 如請求項1所述之晶片封裝方法,其中該晶片與該底材間,具有覆晶式(Flip chip)的引線連接方式。
- 如請求項1所述之晶片封裝方法,其中該些垂直導熱結構的熱傳係數較高於該封裝材料。
- 如請求項1所述之晶片封裝方法,其中該些垂直導熱結構的材料包含銅、鋁、銀、鎳、或複合金屬材料。
- 如請求項1所述之晶片封裝方法,其中各該晶片藉由該些凸點抵接於該底材上。
- 如請求項1所述之晶片封裝方法,其中該底材為一引線框架(Lead frame)。
- 如請求項1所述之晶片封裝方法,其中該晶片的封裝方式包含:方形扁平無引腳封裝 (Quad Flat No-Lead)、雙側扁平無引腳封裝 (Dual Flat No-Lead)、小外型電晶體封裝 (Small Outline Transistor)或小外型封裝 (Small Out-Line Package)。
- 如請求項1所述之晶片封裝方法,其中各該晶片封裝單元中,該垂直導熱結構設置於各該晶片中面對該底材的一側。
- 一種晶片封裝單元,包含: 一引線框架(Lead frame),包含多個貫穿孔; 一晶片,包含多個凸點與多個垂直導熱結構,該些凸點與該些垂直導熱結構位於該晶片的同一側,該晶片設置於該引線框架上,該些垂直導熱結構通過該引線框架中多個貫穿孔、或者直接連接該引線框架; 一封裝材料,封裝各該晶片的側邊以及各該晶片中面對該引線框架的底面。
- 如請求項13所述之晶片封裝單元,該些垂直導熱結構的一側外露於該些晶片封裝單元的表面,或直接連接該引線框架,形成該晶片與該晶片封裝單元的外部間多個熱傳路徑。
- 如請求項13所述之晶片封裝單元,其中該封裝材料填充該些垂直導熱結構與該些貫穿孔間的空隙。
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