CN114597182A - 芯片封装方法以及芯片封装单元 - Google Patents
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Abstract
本发明提出一种芯片封装方法以及芯片封装单元。该芯片封装方法包含:提供一晶圆,晶圆上包含多个凸点;切割晶圆为多个芯片,并覆盖芯片于一底材上,其中在晶圆或芯片上设置多个垂直导热结构;以及提供一封装材料,以封装各芯片的侧边以及各芯片中面对底材的底面,以形成各芯片封装单元。芯片封装单元中,芯片上的凸点抵接于底材,其中垂直导热结构通过底材中多个贯穿孔、或者直接连接底材。
Description
技术领域
本发明涉及一种芯片封装方法,特别涉及一种通过打线(Wiring)方式产生的多个垂直导热结构,以加强芯片散热能力的芯片封装方法。
背景技术
现有技术中,参照图1,其显示美国专利案US 9984992的芯片封装结构,其中包含两芯片,下方芯片CH设置于底材110上,位于多个打线材100所环绕形成的法拉第笼(Faraday cage)中,其形成一内部电磁保护结构。打线材100设置于底材110上,与底材110中线路相连,为封装材料120所包覆,此为防电磁感扰设计。
参照图2,其显示美国专利案US 9812402的芯片封装结构。类似于图1,图2的打线材100环绕形成一法拉第笼,打线材100与底材110中线路相连,以形成防电磁感扰设计。
又参照图3,其中显示美国专利案US 7355289的芯片封装结构,其中为加强芯片CH的热传导,在芯片CH上形成多个打线材100,以加强芯片CH散热效果。其中打线材100外露于芯片CH上方的封装材料120外侧。此设计虽考虑散热需求,但打线材100离底板距离远,其各别外露面积小,散热效果有限,且芯片CH受限于打线式(Wire bond)的引线连接方式,其应用时较受限。
针对现有技术,本发明提供一芯片封装技术,其具有散热能力佳、制造容易、应用范围广等优点。
发明内容
就其中一个观点言,本发明提供了一种芯片封装方法,以解决前述的困扰。此芯片封装方法包含:提供一晶圆,晶圆上包含多个凸点;切割晶圆为多个芯片,并覆盖芯片于一底材上,其中在晶圆或芯片上设置多个垂直导热结构;以及提供一封装材料,以封装各芯片的侧边以及各芯片中面对底材的底面,以形成多个芯片封装单元。芯片封装单元中,芯片上的凸点抵接于底材,垂直导热结构通过底材中多个贯穿孔、或者直接连接底材。
在一些实施例中,切割晶圆为多个芯片、设置芯片于底材上、以及其中设置垂直导热结构于晶圆或从晶圆切割的多个芯片上的步骤中,可依需要有不同的实施方式:切割晶圆为多个芯片,之后,在各芯片上设置多个垂直导热结构,之后,以及覆盖各芯片于底材上;或者,在晶圆上设置多个垂直导热结构,之后,切割晶圆为多个芯片,其中各芯片上包含多个垂直导热结构,之后,并覆盖各芯片于底材上;或者,切割晶圆为多个芯片,之后,覆盖各芯片于底材上,之后,并在各芯片上设置多个垂直导热结构,以连接底材。
一实施例中,垂直导热结构为通过在晶圆上进行打线(Wire bond)所产生的引线,垂直导热结构为往垂直方向拉直引线所形成。一实施例中,垂直导热结构设置于晶圆上无功能垫(No connective pad)。
一实施例中,芯片与底材间,具有倒装芯片式(Flip chip)的引线连接方式。一实施例中,底材为一引线框架(Lead frame)。
就其中一个观点言,本发明提供了一种芯片封装单元,包含:一引线框架;一芯片,包含多个凸点与多个垂直导热结构,凸点与垂直导热结构位于芯片的同一侧,芯片设置于引线框架上,垂直导热结构通过引线框架中多个贯穿孔、或直接连接引线框架;以及一封装材料,封装芯片的侧边以及芯片中面对引线框架的底面。
以下通过具体实施例详加说明,当更容易了解本发明的目的、技术内容、特点及其所达成的功效。
附图说明
图1、图2、图3显示现有技术中芯片封装结构的示意图。
图4A至图4F显示根据本发明一实施例中芯片封装方法的示意图。
图5A至图5F显示根据本发明另一实施例中芯片封装方法的示意图。
图6A、图6B显示与本发明一实施例的芯片封装单元的示意图
图中符号说明
10,20:芯片封装单元
100:打线材
110:底材
120:封装材料
130:凸点
140:垂直导热结构
CH:芯片
WF:晶圆
具体实施方式
本发明中的附图均属示意,主要意在表示各电路组成部分间的相互关系,至于形状与尺寸则并未依照比例绘制。
图4A至图4E显示本发明的一个实施例。根据本发明的芯片封装方法包括:提供一晶圆WF,晶圆WF上包含多个凸点130(图4A);之后,从晶圆WF切割的多个芯片CH上(图4B),设置多个垂直导热结构140(图4C),之后,并覆盖芯片CH于一底材110上(图4D);之后,以及提供一封装材料120,以封装各芯片CH的侧边以及各芯片CH中面对底材110的底面,以形成多个芯片封装单元10(图4E)。芯片封装单元10中,芯片CH上的凸点130抵接于底材110,垂直导热结构140通过底材110中多个贯穿孔、或者直接连接底材110。其中,每个芯片CH上包括至少一个凸点130。
图5A至图5E显示本发明的另一个实施例。本发明的芯片封装方法包括:提供一晶圆WF,晶圆WF上包含多个凸点130(图5A);之后,在晶圆WF上设置多个垂直导热结构140后切割为多个芯片CH(图5B、图5C),之后,并覆盖芯片CH于一底材110上(图5D);之后,以及提供一封装材料120,以封装各芯片CH的侧边以及各芯片CH中面对底材110的底面,以形成多个芯片封装单元10(图5E)。芯片封装单元10中,芯片CH上的凸点130抵接于底材110,垂直导热结构140通过底材110中多个贯穿孔、或者直接连接底材110。其中,每个芯片CH上包括至少一个凸点130。
在一实施例中,凸点130包含芯片CH与底材110间连接信号的一互连结构,其可为锡球或其他方式构成。
一些实施例中,前述的切割晶圆WF为多个芯片CH、设置芯片CH于底材110上、以及其中设置垂直导热结构140于晶圆WF上或晶圆WF切割的多个芯片CH上的步骤中,可依需要有不同的实施方式:
(1)切割晶圆WF为多个芯片CH(图4A、图4B),之后,在各芯片CH上设置多个垂直导热结构140(与凸点130在芯片CH的同一侧,图4C),之后,以及覆盖各芯片CH于底材110上(图4D)。
(2)在晶圆WF上设置多个垂直导热结构140(与凸点130在芯片CH的同一侧,图5A、图5B),之后,切割晶圆WF为多个芯片CH(图5C),各芯片CH上包含多个垂直导热结构140,之后,并覆盖各芯片CH于底材110上(图5D)。
(3)切割晶圆WF为多个芯片CH,之后,覆盖各芯片CH于底材110上,之后,并在各芯片CH上设置多个垂直导热结构140(可与凸点在芯片CH的同侧或不同侧),以连接底材110(例如图6中,垂直导热结构140连接底材110,用以增加传热至底材110的效率)。若需要,可根据前述三种方式中部分特征进行组合,例如结合(1)、(2)实施方式中,其中晶圆WF与芯片CH都设置垂直导热结构140等。
一实施例中,垂直导热结构140为通过在晶圆WF上进行打线(Wire bond)所产生的引线,垂直导热结构140为往垂直方向拉直引线所形成。一实施例中,垂直导热结构140设置于晶圆WF上无功能垫(No connective pad),此无功能垫与芯片间无信号连接。
封装材料120为适用于包覆芯片的材料,其包覆性良好,散热效果一般。垂直导热结构140的热传系数较高于封装材料120,透过垂直导热结构140,形成芯片CH与芯片封装单元10、20的外部间的热传路径(图4F、图6B,其中虚线箭头示意的热传路径)。一实施例中,垂直导热结构的材料包含铜、铝、银、镍、或复合金属材料,例如铜合金、银合金等。
参照图4D、图4E,垂直导热结构140的一侧外露于芯片封装单元10的表面,此设计为通过垂直导热结构140或与垂直导热结构140所通过底材110的贯穿孔,以向外传递热。芯片CH上的凸点130抵接于底材110(可形成信号连接),垂直导热结构140的高度较高于凸点130通过贯穿孔,封装材料120填充垂直导热结构140与贯穿孔间的空隙,其中的垂直导热结构140与底材110十分靠近,底材110通过封装材料120仍具有相当程度的间接辅助散热效果。或者,垂直导热结构140连接底材110(图6),通过底材110以形成芯片CH与芯片封装单元20的外部间的热传路径。换言之,芯片封装单元10、20中,芯片CH的主要热传方向之一为朝向底材110的方向。
一实施例中,芯片CH与底材110间,具有倒装芯片式(Flip chip)的引线连接方式。一实施例中,底材110为一引线框架(Lead frame)。一些实施例中,封装方式例如:方形扁平无引脚封装(Quad Flat No-Lead,QFN)、双侧扁平无引脚封装(Dual Flat No-Lead,DFN)、小外型晶体管封装(Small Outline Transistor,SOT)或小外型封装(Small Out-LinePackage,SOP)等。举例而言,其中,在底材110为一引线框架的实施例中,垂直导热结构140例如为导线,由芯片CH向外贯穿引线框架多个的接脚(lead)间的缝隙。
参照图4E、图6A,就其中一个观点言,本发明提供了一种芯片封装单元10、20,包含:一引线框架110;一芯片CH,包含多个凸点130与多个垂直导热结构140,凸点130与垂直导热结构140位于芯片CH的同一侧,芯片CH设置于引线框架110上,垂直导热结构140通过引线框架110中多个贯穿孔、或直接连接引线框架110;以及一封装材料120,封装芯片CH的侧边以及芯片CH中面对引线框架110的底面。
以上已针对实施例来说明本发明,但以上所述,为使本领域技术人员易于了解本发明的内容,并非用来限定本发明的权利范围。在本发明的相同精神下,本领域技术人员可以想到各种等效变化。例如,本发明的用语“耦接”包括直接连接与间接连接。本发明的范围应涵盖上述及其他所有等效变化。
Claims (15)
1.一种芯片封装方法,包含:
提供一晶圆,该晶圆上包含多个凸点;
切割该晶圆为多个芯片,并覆盖该些芯片于一底材上,其中在该晶圆或该些芯片上设置多个垂直导热结构;以及
提供一封装材料,以封装各该芯片的侧边以及各该芯片中面对该底材的底面,以形成各芯片封装单元;
其中,各该芯片封装单元中,该些芯片上的该些凸点抵接于该底材,该些垂直导热结构通过该底材中多个贯穿孔或者直接连接该底材。
2.如权利要求1所述的芯片封装方法,其中,前述的切割该晶圆为该些芯片,覆盖该些芯片于该底材上,其中,在该晶圆或该些芯片上设置该些垂直导热结构的步骤,包含:切割该晶圆为该些芯片,之后,在各该芯片上设置多个该垂直导热结构,之后,以及覆盖该些芯片于该底材上;或者,在该晶圆上设置该些垂直导热结构,之后,切割该晶圆为该些芯片,各该芯片包含多个该垂直导热结构,之后,并覆盖该些芯片于该底材上;或者,切割该晶圆为该些芯片,之后,覆盖该些芯片于该底材上,之后,并在各该芯片上设置多个该垂直导热结构,以连接该底材。
3.如权利要求1所述的芯片封装方法,其中,该些垂直导热结构为通过在该晶圆上进行打线所产生的引线,该些垂直导热结构为往垂直方向拉直该引线所形成。
4.如权利要求3所述的芯片封装方法,其中,该些垂直导热结构为于该晶圆上无功能垫进行打线所产生。
5.如权利要求1所述的芯片封装方法,其中,该些垂直导热结构的一侧外露于该些芯片封装单元的表面,或者该些垂直导热结构连接该底材,以形成各该芯片与各该芯片封装单元的外部间的热传路径。
6.如权利要求1所述的芯片封装方法,其中,该芯片与该底材间,具有倒装芯片式的引线连接方式。
7.如权利要求1所述的芯片封装方法,其中,该些垂直导热结构的热传系数较高于该封装材料。
8.如权利要求1所述的芯片封装方法,其中,该些垂直导热结构的材料包含铜、铝、银、镍、或复合金属材料。
9.如权利要求1所述的芯片封装方法,其中,各该芯片通过该些凸点抵接于该底材上。
10.如权利要求1所述的芯片封装方法,其中,该底材为一引线框架。
11.如权利要求1所述的芯片封装方法,其中,该芯片的封装方式包含:方形扁平无引脚封装、双侧扁平无引脚封装、小外型晶体管封装或小外型封装。
12.如权利要求1所述的芯片封装方法,其中,各该芯片封装单元中,该垂直导热结构设置于各该芯片中面对该底材的一侧。
13.一种芯片封装单元,包含:
一引线框架,包含多个贯穿孔;
一芯片,包含多个凸点与多个垂直导热结构,该些凸点与该些垂直导热结构位于该芯片的同一侧,该芯片设置于该引线框架上,该些垂直导热结构通过该引线框架中多个贯穿孔、或者直接连接该引线框架;
一封装材料,封装各该芯片的侧边以及各该芯片中面对该引线框架的底面。
14.如权利要求13所述的芯片封装单元,其中,该些垂直导热结构的一侧外露于该些芯片封装单元的表面,或直接连接该引线框架,形成该芯片与该芯片封装单元的外部间多个热传路径。
15.如权利要求13所述的芯片封装单元,其中,该封装材料填充该些垂直导热结构与该些贯穿孔间的空隙。
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