TW202205379A - Semiconductor structure and method of forming the same - Google Patents

Abstract

A method of forming a semiconductor structure includes sequentially forming an epitaxial layer and a semiconductor layer on a substrate. A patterned hard mask layer is formed on the semiconductor layer. The patterned hard mask layer includes at least two openings. The semiconductor layer is etched with the patterned hard mask layer as an etching mask to remove the semiconductor layer under the at least two openings. The patterned hard mask layer between the at least two openings is removed. The semiconductor layer and the epitaxial layer are etched with a remaining portion of the patterned hard mask layer as an etch mask so that the epitaxial layer has a recess and a convex portion. The convex portion is on an upper surface of the recess and under the patterned hard mask layer between the at least two openings. The remaining portion of the patterned hard mask layer is removed. A first dielectric layer having a first trench is formed on the semiconductor layer and the epitaxial layer.

Description

Semiconductor structure and method of forming the same

The present invention relates to a semiconductor structure and a method for forming the same, and more particularly, to a semiconductor structure including an epitaxial layer with grooves and protrusions and a method for forming the same.

Due to the trench structure in the trench MOSFET, it has a smaller device pitch and a lower gate-drain capacitance (C _gd ), so it can Effectively reduce on-resistance (R _{ds_on} ) and reduce switching loss. However, as user demands increase, transistors are expected to have smaller size, faster response speed, and lower switching losses. If the size of the transistor needs to be reduced, it is usually necessary to reduce the width of the trench accordingly. Even so, the gate-drain charge (Q _gd ) or gate-drain capacitance cannot be reduced effectively, resulting in no significant improvement in switching speed.

Therefore, a shielded gate trench (SGT) MOSFET has been developed. The SGT-MOSFET is provided with a source electrode serving as a shield electrode, that is, a source shielded structure is provided therein. Therefore, SGT-MOSFET can obtain lower on-resistance and better switching performance based on charge balance technology.

However, although existing semiconductor structures and methods of forming them have gradually met their intended uses, they have not yet fully met the requirements in all respects. Therefore, there are still some problems to be overcome with respect to the semiconductor structure and the method of forming it which can be used as SGT-MOSFET after further processing.

In view of the above problems, the present invention further provides a drain electrode as a shield electrode, that is, a drain shielded structure is further provided to make the electric field and charge in the semiconductor structure more uniform, so as to obtain a better electric field. sexual characteristics.

According to some embodiments, methods of forming semiconductor structures are provided. The method for forming a semiconductor structure includes: sequentially forming an epitaxial layer and a semiconductor layer on a substrate. A patterned hard mask layer is formed on the semiconductor layer. The patterned hard mask layer includes at least two openings. The patterned hard mask layer is used as an etch mask, and the semiconductor layer is etched to remove the semiconductor layer under the at least two openings. The patterned hard mask layer between the at least two openings is removed. The remaining part of the patterned hard mask layer is used as an etching mask, and the semiconductor layer and the epitaxial layer are etched so that the epitaxial layer has grooves and protrusions. The convex portion is located on the bottom surface of the groove and below the patterned hard mask layer between the at least two openings. Remove the remainder of the patterned hardmask layer. A first dielectric layer having a first trench is formed on the semiconductor layer and the epitaxial layer.

According to some embodiments, semiconductor structures are provided. The semiconductor structure includes: a substrate, an epitaxial layer, a semiconductor layer, a dielectric layer, a source electrode and a gate electrode. The substrate has a first conductivity type. The epitaxial layer has a first conductivity type, is disposed on the substrate, and includes a groove and a convex portion disposed on the bottom surface of the groove. The semiconductor layer has a second conductivity type different from the first conductivity type, is arranged on the epitaxial layer, and is not arranged on the groove. The dielectric layer is disposed on the epitaxial layer and the semiconductor layer. The source electrode is disposed on the dielectric layer. The gate electrode is arranged on the dielectric layer.

The semiconductor structure of the present invention can be applied to various types of semiconductor devices. In order to make the features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with the accompanying drawings.

The following disclosure provides many different embodiments or examples for implementing different elements of the provided semiconductor structures. Specific examples of elements and their configurations are described below to simplify embodiments of the invention. Of course, these are only examples and are not intended to limit the present invention. For example, if the description mentions that the first element is formed on the second element, it may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements , so that they are not in direct contact with the examples. Furthermore, embodiments of the present invention may repeat reference numerals and/or letters in different instances. This repetition is for brevity and clarity and is not intended to represent a relationship between the different embodiments and/or aspects discussed.

Some variations of the embodiments are described below. In the different drawings and the illustrated embodiments, like reference numerals are used to designate like elements. It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or deleted for other embodiments of the method.

FIGS. 1-18 are schematic cross-sectional views illustrating various stages of forming the semiconductor structure shown in FIG. 19 according to some embodiments of the present invention.

Referring to FIG. 1 , an epitaxial layer 200 and a semiconductor layer 300 are sequentially formed on the substrate 100 . The substrate 100 may be a bulk semiconductor. The substrate 100 can be a wafer, such as a silicon wafer.

The epitaxial layer 200 may include silicon, germanium, silicon and germanium, III-V compounds, or a combination thereof. The above-mentioned epitaxial layer 200 can be formed by an epitaxial growth process.

In some embodiments, the substrate 100 and the epitaxial layer 200 have a first conductivity type, and the semiconductor layer 300 has a second conductivity type different from the first conductivity type. For example, if the first conductivity type of the substrate 100 and the epitaxial layer 200 is N-type, the second conductivity type of the semiconductor layer 300 is P-type; conversely, if the substrate 100 and the epitaxial layer 200 have the P-type conductivity The first conductivity type is P-type, and the second conductivity type of the semiconductor layer 300 is N-type. The first conductivity type and the second conductivity type can be adjusted according to requirements, and at the same time, the doping concentration, the doping depth and the size of the doping region can also be adjusted according to the requirements. In some embodiments, the substrate 100 and the epitaxial layer 200 have an N-type conductivity; and the semiconductor layer 300 has a P-type conductivity. In some embodiments, the semiconductor layer 300 can also be formed after the gate electrode is subsequently formed.

Referring to FIG. 2 , a patterned hard mask layer 400 is formed on the semiconductor layer 300 . The patterned hard mask layer 400 includes at least two openings OP. The opening OP of the patterned hard mask layer 400 exposes a portion of the upper surface of the semiconductor layer 300 .

The patterned hard mask layer 400 may include oxide, nitride, or a combination thereof. It can be understood that suitable hard mask materials can be matched according to process conditions, so the embodiments of the present invention are not limited thereto.

In some embodiments, the patterned hard mask layer 400 is an oxide. In some embodiments, the step of forming the patterned hard mask layer 400 on the semiconductor layer 300 may further include: depositing an oxide layer on the semiconductor layer 300 ; forming a photoresist layer on the oxide layer; layer is exposed to obtain a patterned photoresist layer; and using the patterned photoresist layer as an etch mask, the oxide layer is etched to form a patterned oxide layer to obtain a patterned hard mask layer on the semiconductor layer 300 400. The oxide layer can be deposited by chemical vapor deposition (CVD), or other suitable processes.

The patterned hard mask layer 400 is used as an etch mask, and the semiconductor layer 300 is etched to remove the semiconductor layer 300 in the at least two openings OP in the patterned hard mask layer 400 . That is, the parts of the semiconductor layer 300 corresponding to the at least two openings OP are removed, so that the semiconductor layer 300 forms the grooves 301 corresponding to the at least two openings OP and the protrusions 302 between the grooves 301, that is, The surface of the semiconductor layer 300 has a shallow twin-trench formation. In some embodiments, the etched semiconductor layer 300 is not penetrated, in other words, the semiconductor layer 300 still completely covers the upper surface of the epitaxial layer 200 without exposing the upper surface of the epitaxial layer 200 . It can be understood that the depth of etching the semiconductor layer 300 can be adjusted according to requirements.

Referring to FIGS. 3 to 5 , the patterned hard mask layer 400 between the at least two openings OP is removed. The patterned hard mask layer 400 may be removed by performing an etching process or other suitable process. The etching process may include dry etching, wet etching, or other etching methods (eg, reactive ion etching). The etching process can also be pure chemical etching (plasma etching), pure physical etching (ion milling), or a combination thereof.

In some embodiments, the patterned hard mask layer 400 may include a first patterned hard mask 400A and a second patterned hard mask 400B between at least two openings OP. In some embodiments, the second patterned hard mask 400B may be adjacent to the first patterned hard mask 400A. In some embodiments, the second patterned hard mask 400B has an opening OP between the first patterned hard mask 400A adjacent thereto. In some embodiments, the first patterned hard mask 400A may be interposed between two adjacent second patterned hard masks 400B. In some embodiments, an etching process is performed to remove the first patterned hard mask 400A and leave the second patterned hard mask 400B to adjust the patterned hard mask as an etching mask for a subsequent etching process The pattern of layer 400.

In detail, as shown in FIG. 3 , before removing the first patterned hard mask 400A between the at least two openings OP, a photoresist layer 500 is formed on the second patterned hard mask 400B. The photoresist layer 500 can be formed by applying a suitable photoresist on the semiconductor layer 300 and the patterned hard mask layer 400 by a spin coating process, and using a suitable mask to expose the photoresist to form a mask only The second patterned hard mask 400B does not mask the photoresist layer 500 of the first patterned hard mask 400A. Next, as shown in FIG. 4 , the first patterned hard mask 400A between the at least two openings OP that is not shielded by the photoresist layer 500 is removed to expose the semiconductor under the first patterned hard mask 400A Layer 300. That is, by removing the first patterned hard mask 400A, the top surface and sidewalls of the protrusions 302 of the semiconductor layer 300 are exposed. The convex portion 302 of the semiconductor layer 300 may correspond to a position below the first patterned hard mask 400A of the patterned hard mask 400 that has been removed. Then, as shown in FIG. 5 , after removing the first patterned hard mask 400A, the photoresist layer 500 is removed. The photoresist layer 500 may be removed using ashing and/or wet strip processes.

According to some embodiments of the present invention, by disposing the photoresist layer 500 on the patterned hard mask layer 400; removing a part of the patterned hard mask layer 400, that is, removing the first patterned hard mask 400A; And the remaining part of the patterned hard mask layer 400 is retained, that is, the second patterned hard mask 400B is retained to adjust the pattern of the patterned hard mask layer 400 as an etching mask for the subsequent etching process.

Referring to FIG. 6 , the remaining part of the patterned hard mask layer is used, that is, the second patterned hard mask 400B is used as an etching mask, and the semiconductor layer 300 and the epitaxial layer 200 are etched according to a specific etching rate and etching rate The selectivity enables the pattern of the surface of the semiconductor layer 300 to be transferred onto the surface of the epitaxial layer 200 . Since the surface of the semiconductor layer 300 has the grooves 301 and the protrusions 302 between the grooves 301 , after the etching process, the epitaxial layer 200 can also have the grooves 210 and the protrusions 220 . Although the semiconductor layer 300 is disposed on the epitaxial layer 200 , it is not disposed on the groove 210 . The groove 210 is concave toward the direction of the substrate 100 . In the epitaxial layer 200 , the bottom surface of the groove 210 is closest to the substrate 100 . The convex part 220 may be located on the bottom surface of the groove 210 . The convex portion 220 may correspond to a position below the first patterned hard mask 400A of the patterned hard mask 400 that has been removed, and below the convex portion 302 of the semiconductor layer 300 .

In some embodiments, the protrusion 220 extends outward from the bottom surface of the groove 210 in a direction away from the substrate 100 . In addition, when the dotted line in FIG. 6 is used as a virtual reference line, the convex portion 220 has a height H. As shown in FIG. Preferably, the height H can be 1/2~1/6 of the trench depth L, wherein the trench depth L is the distance from the bottom of the semiconductor layer 300 to the virtual reference line in FIG. 6; more preferably, it can be 1 /3~1/5. The width W of the convex portion 220 may correspond to the width of the first patterned hard mask 400A. Preferably, the width W may be 1/2˜3/1 of the width of the groove 210 of the epitaxial layer 200 ; more preferably, it may be 1/1˜2/1. Here, the protruding portion 220 of the epitaxial layer 200 can be used as a drain shielded structure to be disposed in the SGT-MOSFET to be formed subsequently. Therefore, the present invention can increase the depth of the shielding electrode in the drift region by setting the drain shielding structure, further improve the charge balance effect, make the charge distribution more uniform, and keep the maximum electric field strength away from the corners of the trench to achieve To achieve the purpose of reducing the on-resistance and increasing the breakdown voltage of the component.

In some embodiments, since the width of the opening OP corresponds to the distance D between the convex portion 220 and the sidewall of the groove 210 , the width between the convex portion 220 and the sidewall of the groove 210 can be adjusted by adjusting the width of the opening OP. distance D. Preferably, the distance D is not zero. Preferably, the ratio of the distance D to the width W is 1:3~2:1; more preferably, 1:2~1:1. Furthermore, by changing the distance D between the convex portion 220 and the sidewall of the groove 210, the capacitance between the convex portion 220 and the sidewall of the groove 210 is adjusted to reduce the epitaxial resistance in the epitaxial layer 200 ( epitaxy resistance), reducing the on-resistance, increasing the breakdown voltage, and maintaining the gate charge (Qg) without increasing the gate charge. Therefore, the Figure of Merits (FOM) of the subsequently formed SGT-MOSFET can be further improved, so as to reduce the switching loss of the high-voltage side, reduce the conduction loss of the low-voltage side, and improve the circuit efficiency.

Referring to FIG. 7 , the second patterned hard mask 400B is removed to expose the upper surface of the semiconductor layer 300 . The process for removing the second patterned hard mask 400B is the same as the process for removing the first patterned hard mask 400A, or it can be removed by any suitable process. Next, a first dielectric layer 600 having a first trench T1 is formed on the semiconductor layer 300 and the epitaxial layer 200 to obtain the semiconductor structure of the present invention. The first dielectric layer 600 may be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable dielectric material, or a combination thereof. The material of the high dielectric constant dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, zirconium Silicates, zirconium aluminates. In some embodiments, the first dielectric layer 600 may include oxide.

The first dielectric layer 600 may be formed by CVD or thermal oxidation. CVD can be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD) ), PECVD, atomic layer deposition (ALD) or other suitable CVD process.

In some embodiments, the first dielectric layer 600 is conformally formed on the epitaxial layer 200 and the semiconductor layer 300 . Specifically, the first dielectric layer 600 is disposed on the top surface and sidewall of the semiconductor layer 300 , on the sidewall and bottom surface of the groove 210 of the epitaxial layer 200 , and on the sidewall and top of the convex portion 220 of the epitaxial layer 200 on the surface.

It should be noted that, generally speaking, SGT-MOSFET can be divided into left and right split gate type and up and down split gate type. Commonly, the shield electrodes of the left and right separated gate type are sandwiched between the gate electrodes, and the shield electrodes of the upper and lower separated gate type are arranged below the gate electrodes. The semiconductor structure of the present invention can be widely applied to the above two common SGT-MOSFETs, and the formation method of the semiconductor structure of the present invention can further improve the SGT-MOSFET by adding a drain shielding structure under the condition of changing only a few steps. electrical characteristics.

According to some embodiments of the present invention, by adjusting the shape of the first dielectric layer 600, the shape of the source electrode 700 and/or the gate electrode 800 formed subsequently is adjusted, thereby changing the gate and drain capacitances to improve performance. In addition, the semiconductor structure of the present invention can be formed by performing further processes to form the SGT-MOSFET of one of the embodiments of the present invention.

In some embodiments, the first dielectric layer 600 has a first trench T1. The first trench T1 has a substantially flat bottom surface, and the bottom surface of the first trench T1 is substantially parallel to the top surface of the protruding portion 220 . Therefore, the semiconductor in the shape of the first dielectric layer 600 will be included in the following. The structure is called semiconductor structure 1. In some embodiments, the first dielectric layer 600 has a first trench T1. The bottom surface of the first trench T1 is not substantially flat. The first trench T1 has a protruding shape corresponding to the protruding portion 220 extending away from the substrate 100 . Therefore, the semiconductor structure including the shape of the first dielectric layer 600 is hereinafter referred to as the semiconductor structure 2 (shown in the 20th picture).

In the following, the left and right split gate type of SGT-MOSFET is used as an example to explain:

Referring to FIGS. 8 to 13 , based on the semiconductor structure 1 , the source electrode 700 and the gate electrode 800 are formed on the first dielectric layer 600 under the condition that the first trench T1 has a substantially flat bottom surface. The source electrode 700 is formed on the convex portion 220 of the epitaxial layer 200 . The gate electrode 800 is formed on the groove 210 of the epitaxial layer 200 , but is not formed on the convex portion 220 of the epitaxial layer 200 , but is formed at positions on both sides of the source electrode 700 .

In detail, as shown in FIG. 8 , a first material is filled in the first trench T1 of the first dielectric layer 600 to form the source electrode 700 . The first material is a conductive material, and may include polysilicon, amorphous silicon, metal, metal nitride, conductive metal oxide, or other suitable materials. In some embodiments, the first material may be polysilicon. The method of filling the first material includes, but is not limited to, CVD, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process. In addition, after filling the first material, an etchback or chemical mechanical polishing (CMP) process may be further performed, so that the top surface of the source electrode 700 and the top surface of the first dielectric layer 600 are substantially substantially upper coplanar.

Next, as shown in FIG. 9 , the source electrode 700 is etched back so that the top surface of the source electrode 700 is lower than the top surface of the first dielectric layer 600 . As shown in FIG. 10, the first dielectric layer 600 is etched until the upper surface of the semiconductor layer 300 is exposed, a part of the sidewall of the source electrode 700 is exposed, and a part of the sidewall of the groove 210 of the epitaxial layer 200 is exposed, to form the second trench T2. The second trench T2 is interposed between the semiconductor layer 300 and the source electrode 700 . As shown in FIG. 11 , a second dielectric layer 610 is conformally formed on the second trench T2 , the semiconductor layer 300 and the source electrode 700 . The second dielectric layer 610 has a third trench T3. In some embodiments, the second dielectric layer 610 and the first dielectric layer 600 may be formed of the same material or different materials. In some embodiments, the second dielectric layer 610 may be silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, or any other suitable dielectric material, or any of the above combination. In some embodiments, the second dielectric layer 610 may include oxide. In some embodiments, the second dielectric layer 610 and the first dielectric layer 600 may be formed by the same or different processes.

As shown in FIG. 12 , the second material is filled in the third trench T3 to form the gate electrode 800 . In some embodiments, the second material and the first material may be formed of the same or different materials. In some embodiments, the second material and the first material may be formed by the same or different processes. In some embodiments, the second material may be polysilicon.

As shown in FIG. 13, after the second material is filled in the third trench T3, a planarization process may be further performed to planarize the second material until the upper surface of the source electrode 700 is exposed and the second dielectric is retained At least a portion of layer 610 is on semiconductor layer 300 . The source electrode 700 can be sandwiched between the gate electrodes 800 . The planarization process may include using, for example, a CMP process.

As shown in FIG. 14 , a first doped region 310 is formed on the surface of the semiconductor layer 300 away from the substrate 100 . The manner of forming the first doped region 310 includes, for example, ion implantation or diffusion process, but is not limited thereto. In addition, the implanted dopants can be activated by a rapid thermal annealing (RTA) process.

As shown in FIG. 15 , an interlayer dielectric layer 900 is formed over the first doped region 310 , the source electrode 700 , the gate electrode 800 and the second dielectric layer 610 . In some embodiments, the interlayer dielectric layer 900 and the second dielectric layer 610 may be formed of the same material. In some embodiments, the interlayer dielectric layer 900 and the second dielectric layer 610 may be formed by the same or different processes.

As shown in FIG. 16, the contact through hole CT is formed. The contact via CT may penetrate through the first doped region 310 , the second dielectric layer 610 and the interlayer dielectric layer 900 . The contact through hole CT does not penetrate the semiconductor layer 300 . The contact through hole CT exposes a portion of the semiconductor layer 300 disposed on the epitaxial layer 200 .

As shown in FIG. 17 , a second doped region 320 is formed under the contact via CT and in the semiconductor layer 300 . The first doped region 310 and the second doped region 320 have different conductivity types. As shown in FIG. 18 , the through hole material is filled in the contact through hole CT to form the contact plug 330 . In some embodiments, the via material may comprise metallic material, conductive material, or other suitable material. As shown in FIG. 19, a metal layer 910 is formed on the interlayer dielectric layer 900, so that the metal layer 910 and the contact plug 330 are in contact with each other, so as to obtain an SGT-MOSFET according to an embodiment of the present invention.

In some embodiments, the substrate 100 , the epitaxial layer 200 , and the first doped region 310 have a first conductivity type. The doping concentration of the first doping region 310 may be higher than the doping concentration of the substrate 100 and the epitaxial layer 200 . The semiconductor layer 300 and the second doped region 320 have a second conductivity type different from the first conductivity type. The doping concentration of the second doping region 320 may be higher than that of the semiconductor layer 300 . Specifically, when the substrate 100 and the epitaxial layer 200 are N-type and the semiconductor layer 300 is P-type, the first doped region 310 can be a heavily doped N+ type, and the second doped region 320 can be heavily doped The P+ form.

In some embodiments of the present invention, the semiconductor structure may include a source electrode 700 , a gate electrode 800 and a bump 220 . The source electrode 700 is sandwiched in the gate electrode 800 . The source electrode 700 may be a source electrode serving as a shield electrode. The gate 800 may be a gate electrode. The convex portion 220 can be a drain electrode serving as a shielding electrode. By further disposing the convex portion 220 in the epitaxial layer 200, the capacitance between the convex portion 220 and the sidewall of the groove 210 of the epitaxial layer 200 is changed, so as to improve the electrical performance of the left and right split gate type of the SGT-MOSFET.

In the following, the upper and lower separated gate type of SGT-MOSFET is used as an example to illustrate:

For the convenience of description, since all the previous steps are described with reference to FIGS. 1 to 6 , they will not be repeated here. In addition, steps similar to the aforementioned steps will not be described again.

Similar to FIGS. 7 to 13, referring to FIGS. 20 to 25, a source electrode 700 is formed on the groove 210 of the epitaxial layer 200, and a gate electrode 800 is formed on the source electrode 700, so that the gate electrode is relatively The source electrode 700 is further away from the substrate 100 .

It should be noted that, as shown in FIG. 20 , since the shape of the bottom surface of the source electrode 700 is affected by the first trench T1 of the first dielectric layer 600 , the following description is based on the semiconductor structure 2 . In this embodiment, since the first dielectric layer 600 is compliantly formed over the epitaxial layer 200 and the semiconductor layer 300 , the first dielectric layer 600 forms the protruding surface 600 a above the relative position corresponding to the convex portion 220 , The bottom surface of the first trench T1 of the first dielectric layer 600 is not substantially flat, that is, the first trench T1 has a protruding shape corresponding to the protruding portion 220 extending away from the substrate 100 . As described above, the description of the steps of forming the source electrode 700 and the gate electrode 800 on the first dielectric layer 600 is continued. In addition, when based on the semiconductor structure 1, that is, when the first trench T1 has a substantially flat bottom surface, a source electrode 700 with a corresponding flat bottom surface can be formed, and the semiconductor structure 1 can still be obtained by further processes. The SGT-MOSFET of one of the embodiments of the present invention.

As shown in FIG. 21 , a first material is filled in the first trench T1 of the first dielectric layer 600 to form a source electrode 700 . Wherein, since the first trench T1 of the first dielectric layer 600 has a protruding shape corresponding to the protruding portion 220 of the epitaxial layer 200, that is, corresponding to the protruding surface 600a of the first dielectric layer 600, therefore, The source electrode 700 disposed in the first trench T1 has a concave shape corresponding to the convex portion 220 of the epitaxial layer 200 . In other words, in some embodiments, the source electrode 700 has two extending portions extending toward the substrate 100 , and the portion between the extending portions of the source electrode 700 is recessed in a direction away from the substrate 100 .

As shown in FIG. 22, the first dielectric layer 600 is etched and a portion of the source electrode 700 is removed until the top surface of the first dielectric layer 600 and the top surface of the source electrode 700 are substantially coplanar, and the first dielectric The top surface of the layer 600 is lower than the interface between the epitaxial layer 200 and the semiconductor layer 300 to form the second trench T2.

As shown in FIG. 23 , a second dielectric layer 610 is formed on the second trench T2 and on the semiconductor layer 300 . The second dielectric layer 610 has a third trench T3. As shown in FIG. 24 , the second material is filled in the third trench T3 to form the gate electrode 800 . The width of the gate electrode 800 may be greater than that of the source electrode 700 . In addition, after filling the second material, a CMP process may be further performed, so that the top surface of the gate electrode 800 and the top surface of the second dielectric layer 610 are substantially coplanar. As shown in FIG. 25 , the gate electrode 800 is etched back so that the top surface of the gate electrode 800 is lower than the top surface of the second dielectric layer 610 .

Continuing the above, similar to FIGS. 14 to 19 , referring to FIGS. 26 to 31 , the first doped region 310 , the second doped region 320 , the contact plug 330 , the interlayer dielectric layer 900 , and the metal layer 910 are formed to The SGT-MOSFET of one of the embodiments of the present invention is obtained. Here, descriptions similar to those described above will not be repeated here. In particular, since the top surface of the gate electrode 800 is lower than the top surface of the second dielectric layer 610 in this embodiment, when the interlayer dielectric layer 900 is disposed on the second dielectric layer, the interlayer dielectric layer 900 has A portion extending toward the substrate 100 .

In some embodiments of the present invention, the semiconductor structure may include a source electrode 700 , a gate electrode 800 and a bump 220 . The source electrode 700 is disposed under the gate electrode 800 . The source electrode 700 may be a source electrode serving as a shielding electrode. The convex portion 220 can be a drain electrode serving as a shielding electrode. By further disposing the protruding portion 220 in the epitaxial layer 200, the capacitance between the protruding portion 220 and the sidewall of the groove 210 of the epitaxial layer 200 is changed, so as to improve the electrical performance of the upper and lower separated gate type of the SGT-MOSFET.

To sum up, according to some embodiments of the present invention, the present invention further improves the electrical performance by arranging the source shielding structure and the drain shielding structure at the same time. For example, on-resistance and switching loss can be reduced. In addition, since the present invention arranges the protrusions on the epitaxial layer by adjusting the shape of the epitaxial layer, the formation method of the present invention can be widely applied to the improvement of various transistors, for example, whether it is SGT- MOSFET left and right separated gate type or upper and lower separated gate type are applicable.

Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can learn some implementations from the present disclosure. In the disclosure of the examples, it is understood that processes, machines, manufactures, compositions of matter, devices, methods and steps developed in the present or in the future, as long as substantially the same functions can be implemented or substantially the same results can be obtained in the embodiments described herein. Some embodiments of the present disclosure are used. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods and steps. In addition, each claimed scope constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each claimed scope and the embodiments.

Several embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should appreciate that they can, based on the embodiments of the present invention, design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can, without departing from the spirit and scope of the present invention, Make all kinds of changes, substitutions, and substitutions.

1,2: Semiconductor structure 100: Substrate 200: epitaxial layer 210, 301: Grooves 220,302: convex part 300: Semiconductor layer 310: the first doped region 320: the second doping region 330: Contact Plug 400: Patterned hard mask layer 400A: First patterned hard mask 400B: Second patterned hard mask 500: photoresist layer 600: first dielectric layer 600a: Protruding surface 610: Second Dielectric Layer 700: source 800: Gate 900: Interlayer dielectric layer 910: Metal Layer CT: Contact Via D: distance H: height L: depth OP: opening T1: First trench T2: Second trench T3: Third trench W: width

Through the following detailed description in conjunction with the accompanying drawings, we can better understand the viewpoints of the embodiments of the present invention. Notably, according to standard industry practice, some features may not be drawn to scale. In fact, the dimensions of various components may be increased or decreased for clarity of discussion. 1 to 18 are schematic cross-sectional views illustrating the formation of semiconductor structures at various stages according to some embodiments of the present invention; 19 is a schematic cross-sectional view illustrating an SGT-MOSFET formed from a semiconductor structure according to one embodiment of the present invention according to some embodiments of the present invention; FIGS. 20-30 are schematic cross-sectional views illustrating semiconductor structures according to some embodiments of the present invention; and FIG. 31 is a schematic cross-sectional view illustrating an SGT-MOSFET formed from a semiconductor structure according to one embodiment of the present invention, according to some embodiments of the present invention.

100: Substrate

200: epitaxial layer

220: convex part

300: Semiconductor layer

310: the first doped region

320: the second doping region

330: Contact Plug

600: first dielectric layer

610: Second Dielectric Layer

700: source

800: Gate

900: Interlayer dielectric layer

910: Metal Layer

Claims (15)

A method for forming a semiconductor structure, comprising: forming an epitaxial layer and a semiconductor layer on a substrate in sequence; forming a patterned hard mask layer on the semiconductor layer, the patterned hard mask layer including at least two openings; using the patterned hard mask layer as an etching mask, and etching the semiconductor layer to remove the semiconductor layer under the at least two openings; removing the patterned hard mask layer between the at least two openings; Using the remainder of the patterned hard mask layer as an etch mask, and etching the semiconductor layer and the epitaxial layer so that the epitaxial layer has a groove and is located on the bottom surface of the groove and between a convex portion below the patterned hard mask layer between the at least two openings; removing the remaining portion of the patterned hard mask layer; and A first dielectric layer having a first trench is formed on the semiconductor layer and the epitaxial layer. The forming method of claim 1, wherein before removing the patterned hard mask layer between the at least two openings, a photoresist layer is formed on the remaining portion of the patterned hard mask layer, and The photoresist layer is removed after removing the patterned hard mask layer between the at least two openings. The forming method of claim 1, further comprising an electrode forming step, the electrode forming step comprising: forming a source electrode on the convex portion of the epitaxial layer; and A gate electrode is formed on the groove of the epitaxial layer, and the gate electrode is not formed on the convex portion of the epitaxial layer. The forming method of claim 3, wherein the electrode forming step further comprises: filling a first material in the first trench of the first dielectric layer to form the source; etching the first dielectric layer until the upper surface of the semiconductor layer is exposed to form a second trench; forming a second dielectric layer on the second trench, the semiconductor layer and the source, the second dielectric layer has a third trench; and Filling a second material in the third trench to form the gate, wherein the step of forming the gate further comprises: The second material is planarized until the upper surface of the source electrode is exposed, and at least a part of the second dielectric layer is left on the semiconductor layer. The forming method of claim 1, further comprising an electrode forming step, the electrode forming step comprising: forming a source on the groove of the epitaxial layer; and A gate is formed on the source, so that the gate is farther away from the substrate than the source. The forming method of claim 5, wherein the electrode forming step further comprises: filling a first material in the first trench of the first dielectric layer to form the source; etching the first dielectric layer until the top surface of the first dielectric layer is coplanar with the top surface of the source to form a second trench; forming a second dielectric layer on the second trench and on the semiconductor layer, the second dielectric layer has a third trench; and A second material is filled in the third trench to form the gate. The forming method of claim 6, wherein a protruding shape corresponding to the protruding portion of the epitaxial layer is formed in the first trench of the first dielectric layer, so that the source electrode has a shape corresponding to the epitaxial layer A concave shape of the convex portion of the crystal layer. The formation method of claim 1, further comprising: forming a first doped region on the semiconductor layer; forming an interlayer dielectric layer on the first doped region; forming a contact via that exposes a portion of the semiconductor layer disposed on the epitaxial layer; forming a second doped region under the contact via and in the semiconductor layer; filling a through hole material in the contact through hole to form a contact plug; A metal layer is formed on the interlayer dielectric layer so that the metal layer and the contact plug are in contact with each other. The formation method of claim 8, wherein the substrate, the epitaxial layer, and the first doped region have a first conductivity type, and the semiconductor layer and the second doped region have a different conductivity than the first conductivity A second conductivity type of the type. A semiconductor structure comprising: a substrate having a first conductivity type; an epitaxial layer, having the first conductivity type, disposed on the substrate, comprising a groove and a protrusion disposed on the bottom surface of the groove; a semiconductor layer having a second conductivity type different from the first conductivity type, disposed on the epitaxial layer and not disposed on the groove; a dielectric layer disposed on the epitaxial layer and the semiconductor layer; a source electrode disposed on the dielectric layer; and A gate electrode is arranged on the dielectric layer. The semiconductor structure of claim 10, wherein the dielectric layer is disposed on the top surface and sidewalls of the semiconductor layer, on the sidewalls and the bottom surface of the recess of the epitaxial layer, and the convex portion of the epitaxial layer on the side walls and top surface. The semiconductor structure of claim 10, wherein: the source electrode is disposed on the convex portion of the epitaxial layer; and The gate electrode is arranged on the groove of the epitaxial layer, and is not arranged on the convex portion of the epitaxial layer. The semiconductor structure of claim 10, wherein: The source electrode is disposed on the groove of the epitaxial layer, wherein the source electrode has a concave shape corresponding to the convex portion of the epitaxial layer, and the concave shape is larger than the bottom surface of the source electrode away from the substrate; and The gate electrode is disposed on the source electrode, and the gate electrode is farther away from the substrate than the source electrode. The semiconductor structure of claim 10, wherein the width of the gate electrode is greater than the width of the source electrode. The semiconductor structure of claim 10, comprising: a first doped region with the first conductivity type disposed on the semiconductor layer; an interlayer dielectric layer disposed on the dielectric layer; a contact plug, penetrating the interlayer dielectric layer, the dielectric layer, and the first doped region, and not penetrating the semiconductor layer; a second doped region, having the second conductivity type, disposed on the semiconductor layer and in contact with the contact plug; and A metal layer is disposed on the interlayer dielectric layer and is in contact with the contact plug.

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