TWI834121B - Semiconductor device and method forming the same - Google Patents

Abstract

A semiconductor device, including: a substrate having a first conductive type, an epitaxial layer disposed on the substrate, a doped region disposed in the epitaxial layer, and a gate electrode disposed through the doped region and extending into the epitaxial layer. The epitaxial layer has the first conductive type, and the doped region has a second conductive type different from the first conductive type. The gate electrode includes a first structure having a first dimension, and a second structure above the first structure. The second structure includes a main portion and a protruding portion below the main portion, wherein the main portion has a second dimension larger than the first dimension, and the protruding portion has the first dimension.

Description

Semiconductor components and methods of forming the same

Embodiments of the present disclosure relate to semiconductor devices and methods of forming the same, and in particular to the design of "split-gate" and methods of forming the same.

Traditional metal-oxide semiconductor field effect transistor (MOSFET) is a popular discrete power component. Certain power devices (components with vertical diffusion configurations) have a PN junction structure consisting of an N-type drift region and an upper P-type doped region. The PN junction structure is mainly used to withstand the voltage applied to traditional metal oxide semiconductor field effect transistors. When improving the operating voltage of metal oxide semiconductor field effect transistors, less doping concentration and a thicker N-type drift region are required. The method used to improve the voltage withstanding of the PN junction structure results in a larger on-resistance of traditional metal oxide semiconductor field effect transistors. The on-resistance of traditional metal oxide semiconductor field effect transistors is limited by the doping concentration and thickness of the N-type drift region.

The vertical diffusion configuration has the advantage of using up less space in the circuit. However, due to the vertical diffusion configuration, the thickness of the N-type drift region may affect the overall performance of the device. Although increasing the thickness of the N-type drift region can improve the operating voltage and thus the breakdown voltage, doing so may also increase the on-resistance, resulting in higher heating and greater power loss. In other words, there is a trade-off between breakdown voltage and on-resistance. Therefore, innovative methods need to be proposed to solve the problem of trade-offs.

In one embodiment, a semiconductor device includes a substrate having a first conductivity type, an epitaxial layer disposed on the substrate, a doped region disposed in the epitaxial layer, and a doped region disposed through the doped region and extending into the epitaxial layer. gate electrode in the layer. The epitaxial layer has a first conductivity type, and the doped region has a second conductivity type, the second conductivity type being different from the first conductivity type. The gate electrode includes a first structure having a first size and a second structure on the first structure. The second structure includes a main body portion and a protruding portion under the main body portion, wherein the main body portion has a second size, the second size is larger than the first size, and the protruding portion has a first size.

In another embodiment, a method of forming a semiconductor device includes providing a substrate and an epitaxial layer on the substrate; forming a doped region in the epitaxial layer; and forming a gate trench passing through the doped region and extending into the epitaxial layer. in the crystal layer. The gate trench includes a first opening and a second opening below the first opening. The first opening has a first width and the second opening has a second width, the second width being less than the first width. The method of forming the semiconductor device further includes filling the second opening with a metal material; etching back the metal material to form a first structure of the gate electrode, wherein the top surface of the first structure is lower than the top of the second opening; and depositing a gate dielectric layer on the top surface of the first structure, wherein the position of the gate dielectric layer is lower than the top of the second opening; and forming a second structure of the gate electrode on the gate dielectric layer and filling the remaining portion of the second opening and the first opening.

The following disclosure provides many different embodiments or examples for implementing various components of the invention. Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, the description mentioning that the first component is formed on the second component may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. , an embodiment in which the first and second components are not in direct contact.

It should be understood that additional operational steps may be performed before, during, or after the method, and that some of the operational steps may be replaced or omitted in other embodiments of the method.

In addition, spatially related terms such as "below", "below", "lower", "above", "above", "higher" and similar terms may be used here to describe e.g. Diagrams show the relationship between one element or component and other elements or components. These spatial terms are intended to include the various orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90° or at any other orientation, the spatially relative descriptors used herein may be interpreted similarly to the rotated orientation.

In the embodiments of this disclosure, the terms "about", "approximately" and "approximately" generally mean within ±20%, or within ±10%, or within ±5% of a given value or range, Or within ±3%, or within ±2%, or within ±1%, or even within ±0.5%. The quantities given here are approximate. That is to say, without specifying "about", "approximately", and "approximately", the meaning of "approximately", "approximately", and "approximately" can still be implied.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It should be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal way. interpretation, unless otherwise defined in the embodiments of this disclosure.

Different embodiments disclosed below may reuse the same reference symbols and/or labels. These repetitions are for purposes of simplicity and clarity and are not intended to dictate the relationship between the various embodiments and/or structures discussed.

Power components, such as metal-oxide semiconductor field effect transistor (MOSFET), can be widely used in power system components of analog circuits and digital circuits. In order to reduce the power loss of power components, the on-resistance must be reduced. From previous experiments, it has been found that reducing the epitaxial thickness reduces unwanted on-resistance. However, when the epitaxial thickness is reduced beyond a certain level, the breakdown voltage of the power device may not be maintained at an acceptable level. Simply put, increasing the epitaxial thickness can simultaneously increase the breakdown voltage and on-resistance, while decreasing the epitaxial thickness can reduce both the breakdown voltage and on-resistance. Simply adjusting the epitaxial thickness cannot simultaneously increase the breakdown voltage and suppress the on-resistance.

It has been found that the use of "split-gate" in metal oxide semiconductor field effect transistors can maintain the breakdown voltage and reduce the on-resistance. The configuration of the "split gate" structure drives the electric field to the drain terminal, thereby increasing the breakdown voltage and reducing the on-resistance. "Split gate" consists of two structures of different sizes. Structures with larger dimensions determine the on-resistance, while structures with smaller dimensions determine the breakdown voltage. More specifically, the present disclosure introduces an innovative protruding portion extending with a larger size. The protrusion has its smaller size so that the on-resistance can be further suppressed.

Figure 1 is a schematic cross-sectional view of a semiconductor device 10 according to some embodiments of the present disclosure. In some embodiments, vertically configured semiconductor devices may include any number of staggered gate and source structures, depending on the application and design requirements. For the sake of simplicity, FIG. 1 only shows one gate structure disposed laterally between a pair of source structures. According to some embodiments of the present disclosure, the semiconductor device 10 includes a substrate 100, an epitaxial layer 110, a doped region 120, a well region 130, a gate dielectric layer 150, a gate electrode 160, and an interlayer dielectric (ILD). Layer 200, doped contact region 220, source electrode 230, and drain electrode 240. In some embodiments, the gate dielectric layer 150 may include a first portion 150A, a second portion 150B, and a third portion 150C. Furthermore, the gate electrode 160 may include a first structure 160A and a second structure 160B.

Referring to FIG. 1 , the substrate 100 may be, for example, a wafer or a die, but the embodiment of the present disclosure is not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide , SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (indium antimonide, InSb); alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, arsenic Aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and/or gallium indium arsenide phosphide (GaInAsP) Alloys, or combinations thereof.

In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor substrate on the insulating layer may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In addition, the substrate 100 may be of the first conductivity type or the second conductivity type. In the following embodiments, the first conductivity type and the second conductivity type may represent N type and P type respectively. The first conductivity type (N type) and the second conductivity type (P type) can be individually doped with appropriate dopants (or impurities). N-type dopants may include phosphorus, and P-type dopants may include boron. In a specific embodiment of the present disclosure, the substrate 100 may be of the first conductivity type (N-type), and its doping concentration is approximately between 1×10 ¹⁹ cm ⁻³ and 3×10 ¹⁹ cm ⁻³ .

In other embodiments, the substrate 100 may include an isolation structure (not shown) to define an active region and electrically isolate active region components within or on the substrate 100 , but the embodiments of the present disclosure are not limited thereto. The isolation structure may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, or a local oxidation of silicon (LOCOS) structure. In some embodiments, forming the isolation structure may include, for example, forming an insulating layer on the substrate 100, and selectively etching the insulating layer and the substrate 100 to form a trench extending from the top surface of the substrate 100 to a location within the substrate 100, where the trench Located between adjacent active zones. Next, forming the isolation structure may include growing a liner layer rich in nitrogen (such as silicon oxynitride (SiON)) along the trench, and then depositing an insulating material (such as silicon dioxide (SiO ₂ ) through a deposition process ), silicon nitride (SiN), or silicon oxynitride) is filled into the trench. Afterwards, an annealing process is performed on the insulating material in the trench, and a planarization process is performed on the substrate 100 to remove excess insulating material, so that the insulating material in the trench is flush with the top surface of the substrate 100 .

Continuing to refer to FIG. 1 , an epitaxial layer 110 is provided on the substrate 100 . According to some embodiments of the present disclosure, the epitaxial layer 110 has a first conductivity type, and its doping concentration is approximately between 2.9×10 ¹⁴ cm ⁻³ and 5.0×10 ¹⁴ cm ⁻³ . In a specific embodiment of the present disclosure, the substrate 100 and the epitaxial layer 110 have the same conductivity type, and the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 110 . The material of the epitaxial layer 110 may include arsenic, other similar materials, or combinations thereof. The thickness of the epitaxial layer 110 may be approximately between 4 μm and 8 μm, such as approximately 6 μm. The epitaxial layer 110 may be formed by epitaxial growth.

Continuing to refer to FIG. 1 , a doped region 120 may be formed in the epitaxial layer 110 and may extend from the top surface of the epitaxial layer 110 . In some embodiments, the doped region 120 can reduce body resistance, avoid punch-through of the subsequently formed source electrode 230 , and improve the durability of the unclamped inductive load switch. load switching ruggedness). According to some embodiments of the present disclosure, the doping region 120 has a second conductivity type (P-type), and its doping concentration is approximately between 1×10 ¹² cm ⁻³ and 5×10 ¹² cm ⁻³ . The thickness of doped region 120 may be approximately between 0.8 μm and 1.2 μm. The doped region 120 may be formed by, for example, ion implantation and/or a diffusion process.

Continuing to refer to FIG. 1 , a well region 130 may be formed within the doped region 120 and may extend from a top surface of the doped region 120 . In some embodiments, well region 130 has a first conductivity type (N-type). It should be noted that the configuration of the well region 130 (N-type) within the doped region 120 (P-type) and the doped region 120 within the epitaxial layer 110 (N-type) may constitute a bipolar (NPN) junction. During device operation, depletion regions can be formed in the bipolar junction to reduce leakage current and increase breakdown voltage. According to some embodiments of the present disclosure, the well region 130 has a doping concentration of approximately between 4×10 ¹² cm ⁻³ and 7×10 ¹² cm ⁻³ . The thickness of the well region 130 may be approximately between 1.2 μm and 1.8 μm. The formation method of the well region 130 may be similar to the formation method of the doping region 120, and the details thereof will not be repeated here.

Referring to FIG. 1 , a gate dielectric layer 150 and a gate electrode 160 may be formed through the well region 130 and the doping region 120 and extend into the epitaxial layer 110 . As mentioned previously, the gate electrode 160 may include a first structure 160A and a second structure 160B. The second structure 160B is located above the first structure 160A. The gate electrode 160 may serve as a transistor gate terminal of the semiconductor device 10 . In some embodiments, the gate electrode 160 may be isolated from the vertical channel region by a gate dielectric layer 150 (details of which are discussed below). The material of the gate electrode 160 may include metal, metal nitride (such as titanium nitride, TiN), metal oxide (such as titanium oxide (TiO)), other suitable materials, or combinations thereof, However, the embodiments of the present disclosure are not limited to this. Metals may include cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), copper (copper, Cu), titanium (Ti), tantalum (Ta) ), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), zinc (zinc, Zn), chromium (Cr), molybdenum (Molybdenum, Mo) , niobium (Nb), other similar materials, combinations thereof, or multi-film layers thereof, but the embodiments of the disclosure are not limited thereto.

The first structure 160A and the second structure 160B of the gate electrode 160 are "separated" by a portion of the gate dielectric layer 150 (or the second portion 150B), exhibiting the "separated gate" feature of the embodiment of the present disclosure. The first structure 160A has a lateral dimension of approximately between 0.6 μm and 0.8 μm, and a vertical dimension of approximately between 3.5 μm and 4.0 μm. According to some embodiments of the present disclosure, the second structure 160B of the gate electrode 160 further includes a main body part and a protruding part extending outward from the bottom of the main body part. The body portion of the second structure 160B has a lateral dimension approximately between 0.85 μm and 0.95 μm, and a vertical dimension approximately between 1.2 μm and 1.5 μm. The protrusions of the second structure 160B have the same lateral dimensions as the first structure 160A, while the vertical dimensions of the protrusions of the second structure 160B may be approximately between 0.15 μm and 0.25 μm, such as approximately 0.20 μm.

As shown in FIG. 1 , the protruding portion of the second structure 160B is vertically located between the first structure 160A and the main body portion of the second structure 160B. As mentioned above, the first structure 160A determines the breakdown voltage of the semiconductor device 10 , and the second structure 160B determines the on-resistance of the semiconductor device 10 . The traditional "split gate" structure does not have a protruding portion, which can serve as the interface between the first structure 160A and the second structure 160B. Although the traditional "split gate" feature can reduce the on-resistance and maintain the breakdown voltage, the presence of the protrusion provides a size reduction behavior on the second structure 160B, so that the on-resistance can be further suppressed. It should be understood that the vertical dimension of the protrusion (or protrusion depth E in Figure 2K) cannot exceed the specified range (eg approximately between 0.15 μm and 0.25 μm). If the protrusion depth E (shown in FIG. 2K ) is too small, the electrical characteristics of the semiconductor device 10 may not be significantly improved. On the contrary, if the protrusion depth E is too large, the second portion 150B of the gate dielectric layer 150 may be consumed.

Continuing with reference to FIG. 1 , in addition to the second portion 150B, the first portion 150A and the third portion 150C of the gate dielectric layer 150 surround the periphery of the first structure 160A and the second structure 160B, respectively. More specifically, the first portion 150A of the gate dielectric layer 150 is conformably disposed on opposite sides and the bottom of the first structure 160A. The third portion 150C is compliantly disposed on the opposite sides of the second structure 160B and on the exposed bottom surface of the main body of the second structure 160B. Gate dielectric layer 150 provides insulation between first structure 160A and second structure 160B, and between gate electrode 160 and doped layers (eg, epitaxial layer 110, doped region 120, or well region 130). Insulation. It should be understood that during operation of the device, vertical channel regions are created through the well region 130, the doped region 120, and the epitaxial layer 110.

The material of the gate dielectric layer 150 may include silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, gate dielectric layer 150 includes a material with a high dielectric constant, and in these embodiments, gate dielectric layer 150 may have a dielectric constant (or k-value) greater than about 7.0, and May include metal oxides or hafnium (Hf), aluminum, zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium, lead (Pb) ), other similar materials, or silicates of combinations thereof. The thickness of the gate dielectric layer 150 may be approximately between 500 Å and 700 Å, such as approximately 600 Å. According to some embodiments of the present disclosure, the first portion 150A, the second portion 150B, and the third portion 150C may have the same thickness. It should be understood that if the thickness of the gate dielectric layer 150 is too large, excessive capacitance may be generated (especially between the first structure 160A and the second structure 160B). If the thickness of the gate dielectric layer 150 is too small, the insulation function may be impaired. It can be achieved by molecular beam deposition (MBD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), other similar methods, or combinations thereof Gate dielectric layer 150 is formed.

As shown in FIG. 1 , the first structure 160A of the gate electrode 160 and the first portion 150A of the gate dielectric layer 150 are vertically disposed across the doped region 120 and the epitaxial layer 110 . The protruding portion of the second structure 160B of the gate electrode 160 and the second portion 150B of the gate dielectric layer 150 are completely disposed within the doped region 120 . The main portion of the second structure 160B of the gate electrode 160 and the third portion 150C of the gate dielectric layer 150 are disposed through the well region 130 and extend into the doped region 120 . It should be understood that the main body portion of the second structure 160B of the gate electrode 160 and the third portion 150C of the gate dielectric layer 150 must extend into the doped region 120 to push the electric field toward the drain terminal, thereby increasing the breakdown voltage. However, the main body portion of the second structure 160B of the gate electrode 160 and the third portion 150C of the gate dielectric layer 150 cannot extend into the epitaxial layer 110, and doing so may cause collapse failure. Furthermore, the first structure 160A of the gate electrode 160 and the first portion 150A of the gate dielectric layer 150 cannot touch the substrate 100, which may cause operational failure.

Referring to FIG. 1 , an interlayer dielectric layer 200 may be formed on the epitaxial layer 110 , the gate dielectric layer 150 , and the gate electrode 160 . More specifically, the interlayer dielectric layer 200 covers the well region 130 , the third portion 150C of the gate dielectric layer 150 , and the second structure 160B of the gate electrode 160 . In some embodiments, interlayer dielectric layer 200 may provide mechanical protection and insulation from underlying structures. The material of the interlayer dielectric layer 200 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitride carbide (silicon oxynitrocarbide, SiO _x N _y C _1-xy , where x and y range from 0 to 1 range), tetraethylorthosilicate (TEOS), undoped silicic acid glass, doped silica (such as boronphosphosilicate glass (BPSG), fused silica glass , FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low dielectric constant (low-k) dielectric materials, or other suitable dielectric material. It can be processed by chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-assisted chemical vapor deposition, and mobile chemical vapor deposition. The interlayer dielectric layer 200 is formed by flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or combinations thereof.

Continuing to refer to FIG. 1 , the doped contact region 220 and the source electrode 230 may be sequentially formed through the interlayer dielectric layer 200 and the well region 130 , and extend into the doped region 120 . More specifically, the doped contact region 220 is vertically disposed across the well region 130 and the doped region 120 . The source electrode 230 is disposed through the interlayer dielectric layer 200 and extends into the well region 130 . The material of doped contact region 220 may include arsenic, other similar materials, or combinations thereof. According to some embodiments of the present disclosure, the doped contact region 220 has a second conductivity type (P-type), and its doping concentration is approximately between 1×10 ¹⁵ cm ⁻³ and 3×10 ¹⁵ cm ⁻³ . The thickness of doped contact region 220 may be approximately between 0.6 μm and 0.8 μm.

The source electrode 230 may serve as a transistor source terminal of the semiconductor device 10 . The material of the source electrode 230 may be similar to the material of the gate electrode 160, and the details thereof will not be repeated here. The thickness of the source electrode 230 may be approximately between 0.35 μm and 0.55 μm. The doped contact region 220 and the source electrode 230 may be formed by chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition, other similar methods, or a combination thereof. After the doped contact region 220 is formed and before the source electrode 230 is formed, the doped contact region 220 may be doped using an ion implantation and/or diffusion process.

Referring to FIG. 1 , the drain electrode 240 may be formed on the backside of the substrate 100 or on the surface opposite to the epitaxial layer 110 (the epitaxial layer 110 is disposed on the front side of the substrate 100 ). . More specifically, the drain electrode 240 covers the back side of the substrate 100 . The drain electrode 240 may serve as a transistor drain terminal of the semiconductor device 10 . It should be understood that source electrode 230 and drain electrode 240 define the previously mentioned vertical channel regions created during operation of the device. The material of the drain electrode 240 may be similar to the gate electrode 160 or the source electrode 230, and the details thereof will not be repeated here. The thickness of the drain electrode 240 may be approximately between 10 μm and 20 μm. The drain electrode 240 may be formed by back metallization using a method similar to that used to form the source electrode 230, the details of which will not be repeated here.

Figures 2A-2K are schematic cross-sectional views at an intermediate stage of manufacturing the semiconductor device 10 according to some embodiments of the present disclosure. It should be noted that the step-by-step steps in Figures 2A-2K are for illustrative purposes only and are not intended to limit the embodiments of the present disclosure. For example, various steps shown in Figures 2A-2K can be added, removed, replaced, reorganized, and repeated.

Referring to Figure 2A, a substrate 100 and an epitaxial layer 110 are provided. As mentioned previously, the epitaxial layer 110 can be formed on the substrate 100 through epitaxial growth. The epitaxial growth can include metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (molecular beam epitaxy). beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), other similar methods, or combinations thereof . Both the substrate 100 and the epitaxial layer 110 may have a first conductivity type (N-type).

Referring to FIG. 2B , a doped region 120 may be formed in the epitaxial layer 110 . In an alternative embodiment, the doped region 120 may be doped in situ during the growth of the epitaxial layer 110 without using ion implantation and/or diffusion processes (as described above). In other embodiments, in-situ and implanted doping may be used together. The doped region 120 has a second conductivity type (P type), which is different from the conductivity type of the substrate 100 or the epitaxial layer 110 .

Referring to FIG. 2C , a well region 130 may be formed in the doped region 120 , and the doped region 120 is formed in the epitaxial layer 110 . The well region 130 has a first conductivity type (N-type). As mentioned previously, the configuration of the epitaxial layer 110, the doped region 120, and the well region 130 form a bipolar junction to reduce leakage current and increase breakdown voltage during device operation.

Figures 2D and 2E illustrate the formation of gate trench 140 in which gate dielectric layer 150 and gate electrode 160 will be formed. The gate trench 140 may include a first opening 140A and a second opening 140B. The second opening 140B is provided below the first opening 140A.

Referring to FIG. 2D , a first opening 140A is first formed through the well region 130 and extends into the doping region 120 . The first opening 140A has a first width W1 and a first depth D1. The first width W1 may be approximately between 0.6 μm and 1.4 μm, such as approximately 0.95 μm. It should be noted that the first opening 140A of the present disclosure includes rounded corners, so that the subsequently formed gate dielectric layer 150 and the gate electrode 160 can adopt a profile that generates less stress than using a profile with sharp corners. the stress produced. The first opening 140A can be formed by a photolithography process followed by an etching process. The lithography process may include photoresist coating, soft baking, exposure, post-exposure baking, development, other similar techniques, or combinations thereof. The etching process may include dry etching, wet etching, other similar methods, or combinations thereof.

Referring to FIG. 2E , after the first opening 140A is formed, the second opening 140B may be formed from the bottom surface of the first opening 140A. The second opening 140B is vertically disposed across the doped region 120 and the epitaxial layer 110 . The second opening 140B has a second width W2 and a second depth D2. The second width W2 may be approximately between 0.2 μm and 0.9 μm, such as approximately 0.55 μm. Similar to the features of first opening 140A, second opening 140B includes a rounded bottom. The second opening 140B is formed similarly to the first opening 140A, and the details thereof will not be repeated here.

As shown in Figure 2E, the gate trench 140 has a total depth D that is approximately between 2.2 μm and 3.0 μm, such as approximately 2.6 μm. According to some embodiments of the present disclosure, the first width W1 is approximately 1.5 to 2.0 times larger than the second width W2. The second depth D2 is approximately 4 to 6 times greater than the first depth D1. Although this embodiment shows that the first opening 140A is formed before the second opening 140B is formed, the disclosed embodiment is not limited thereto. For example, an opening with a second width W2 and a total depth D may be initially formed, and then etching is performed to expand the upper portion of the opening to have the first width W1.

Figures 2F and 2G illustrate forming gate dielectric layer 150 and gate electrode 160 in gate trench 140 to have the previously defined profile. The gate dielectric layer 150 may be conformably deposited along the sidewalls and bottom of the gate trench 140 to isolate the gate electrode 160 from the doped layer (such as the epitaxial layer 110, the doped region 120, or the well region 130) . The second opening 140B may be filled first, and then the first opening 140A may be filled.

Referring to FIG. 2F , the first portion 150A of the gate dielectric layer 150 and the first structure 160A of the gate electrode 160 may be deposited in the second opening 140B of the gate trench 140 . After performing the etching process to form the second opening 140B, and before removing the lithography pattern, the gate dielectric material and the gate electrode material may be sequentially filled into the second opening 140B. After filling the second opening 140B, a planarization process (such as chemical mechanical polish (CMP) or etchback) may be performed to remove the photolithographic pattern and excess gate dielectric material and gate electrode material. According to some embodiments of the present disclosure, the gate dielectric material and gate electrode material are further etched under the top of the second opening 140B (or the joint between the first opening 140A and the second opening 140B). The remaining gate dielectric material and gate electrode material become the first portion 150A of the gate dielectric layer 150 and the first structure 160A of the gate electrode 160 respectively. By having the top surfaces of the first portion 150A and the first structure 160A below the top of the second opening 140B, the subsequently formed second structure 160B can have protrusions as a key feature of the disclosed embodiments.

Referring to FIG. 2G , a second portion 150B of the gate dielectric layer 150 may be deposited in the remaining portion of the gate trench 140 (or more specifically, the remaining portion of the second opening 140B and the entire first opening 140A). The third portion 150C, and the second structure 160B of the gate electrode 160. The same gate dielectric material may be conformably formed on the sidewalls of the first opening 140A, on the sidewalls of the remainder of the second opening 140B, and on the top surfaces of the first portion 150A and the first structure 160A. Afterwards, the same gate electrode material can completely fill the gate trench 140 . The same planarization process may be performed to remove excess gate dielectric material and gate electrode material outside the gate trench 140 . After the planarization process, the top surfaces of the well region 130, the gate dielectric material, and the gate electrode material are flush with each other. The portion of the gate dielectric material that contacts the first portion 150A and the top surface of the first structure 160A becomes the second portion 150B, while the remainder of the gate dielectric material becomes the third portion 150C. The gate electrode material surrounded by the second portion 150B and the third portion 150C becomes the second structure 160B.

Referring to FIG. 2H , an interlayer dielectric layer 200 may be deposited on the well region 130 , the gate dielectric layer 150 , and the gate electrode 160 . In some embodiments, the interlayer dielectric layer 200 seals the gate trench 140 . Gate electrode 160 may be separated from the overlying structure to avoid any potential short circuits.

Referring to FIG. 2I, a pair of source trenches 210 are formed through the interlayer dielectric layer 200 and the well region 130, and extend into the doping region 120. It should be noted that the source trenches 210 are laterally disposed on opposite sides of the gate electrode 160 . Gate electrode 160 may be laterally located between subsequently formed source electrodes 230 .

Referring to FIG. 2J , the source trench 210 may be filled with contact material and source electrode material in sequence. More specifically, the contact material may only fill the lower portion of the source trench 210 , while the source electrode material may fill the remaining portion of the source trench 210 . A planarization process may be performed to remove excess source electrode material outside the source trench 210 . After the planarization process, the top surfaces of the interlayer dielectric layer 200 and the source electrode material are flush with each other. The contact material becomes doped contact region 220 and the remaining source electrode material becomes source electrode 230 . The lateral distance between adjacent source electrodes 230 can be defined as the pitch P of the semiconductor device 10 .

Referring to FIG. 2K , the drain electrode 240 may be formed on the backside of the substrate 100 , thereby completing the fabrication of the semiconductor device 10 (or at least its active component). In some embodiments, the drain electrode 240 covers the entire backside surface of the substrate 100 so that the drain electrode 240 can be shared by each source electrode 230 where a vertical channel region can be created.

The lateral distance between the gate electrode 160 and one of the source electrodes 230 can be defined as a mesa width. As shown in FIG. 2K , the gate electrode 160 is laterally located in the middle of the pair of source electrodes 230 . In other words, the mesa width on either side of the gate electrode 160 is the same, thus exhibiting symmetrical behavior. Since the gate electrode 160 in the embodiment of the present disclosure includes two structures of different sizes, it has two different mesa widths. The first mesa width M1 defines the distance between the second structure 160B of the gate electrode 160 and one of the source electrodes 230 , while the second mesa width M2 defines the first structure 160A of the gate electrode 160 and one of the source electrodes 230 distance between. As mentioned above, the gate electrode 160 is laterally located in the middle of the pair of source electrodes 230 , and the first mesa width M1 or the second mesa width M2 on opposite sides of the gate electrode 160 is symmetrical. Therefore, on either side of the gate electrode 160 sides have the same dimensions.

In one specific embodiment, an example device with a "split gate" feature is compared to a conventional device with a single gate electrode of uniform size. List design features and measure electrical parameters. Relevant data are summarized in Table 1. Table 1 Design and electrical parameters traditional design Innovative design difference Epitaxial thickness 6.0μm 6.0μm 0 Gate trench depth 2.60μm 2.60μm 0 Groove first width (not applicable) 0.95μm (not applicable) Groove second width 0.55μm 0.55μm 0 First table width (not applicable) 1.15μm (not applicable) Second table width 1.35μm 1.35μm 0 Pitch 3.25μm 3.25μm 0 breakdown voltage 46.98V 59.10V +20.51% On-resistance 4.06 m-ohm 2.60m-ohm -35.96% critical voltage 3.62V 2.79V -23.04% Saturation drain current 8.05×10 ^-6 A 1.24×10 ^-5 A +53.79%

In order to achieve a valid comparison, some parameters (such as epitaxial thickness, gate trench depth, and pitch) will remain consistent between the traditional design and the innovative design. Since conventionally designed trenches are only of a single size, they can only have one trench width and therefore only one table width. It should be noted that the pitch is equal to the sum of twice the mesa width and the trench width. For innovative designs, the pitch is equal to the sum of twice the first mesa width and the first trench width (3.25μm = 2 × 1.15μm + 0.95μm), or the sum of twice the second mesa width and the second trench width (3.25μm = 2 × 1.35μm + 0.55μm).

In this particular embodiment, applying the "split gate" feature with protrusions can increase the breakdown voltage by 20.51% and reduce the on-resistance by 35.96%. The threshold voltage dropped by 23.04%, but the amount of displacement was still acceptable by industry standards. Furthermore, due to the increase in operating voltage, the saturation drain current is also improved.

Although additional masks may be required to fabricate gate trenches 140 with two different sizes, the resulting device exhibits superior electrical performance. In a conventional design, the electric field may be concentrated near the bottom of the gate electrode. The innovatively designed "split gate" feature drives the electric field to the drain terminal to increase the breakdown voltage. The larger size of the protruding portion of the gate structure can further suppress the on-resistance. With the above characteristics, the semiconductor device 10 can successfully increase the breakdown voltage while reducing the on-resistance.

The features of several embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present invention belongs can better understand the viewpoints of the disclosed embodiments. It should be understood by those of ordinary skill in the art that other processes and structures can be easily designed or modified based on the embodiments of the present disclosure to achieve the same purposes and/or advantages as the embodiments introduced here. Those of ordinary skill in the technical field to which the present invention belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present disclosure, and can be used without departing from the spirit and scope of the embodiments of the present disclosure. Make all kinds of changes, substitutions and substitutions. Therefore, the protection scope of the embodiments of the present disclosure shall be determined by the appended patent application scope. In addition, although the present disclosure has disclosed several preferred embodiments as above, they are not used to limit the scope of the embodiments of the present disclosure.

Reference throughout this specification to features, advantages, or similar language does not imply that all features and advantages that may be realized using embodiments of the disclosure should or can be realized in any single embodiment of the disclosure. In contrast, language referring to features and advantages is to be understood to mean that a particular feature, advantage, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of features and advantages, and similar language, throughout this specification may, but are not necessarily, representative of the same embodiments.

Furthermore, the described features, advantages, and characteristics of the disclosed embodiments may be combined in any suitable manner in one or more embodiments. From the description herein, one of ordinary skill in the art will appreciate that embodiments of the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present disclosure.

10:Semiconductor components 100:Base 110: Epitaxial layer 120: Doped area 130:Well area 140: Gate trench 140A: First opening 140B:Second opening 150: Gate dielectric layer 150A:Part 1 150B:Part 2 150C:Part 3 160: Gate electrode 160A: First structure 160B: Second structure 200: Interlayer dielectric layer 210: Source trench 220: Doped contact area 230: Source electrode 240: Drain electrode D:Total depth D1: first depth D2: Second depth E:Protrusion depth M1: first table width M2: Second table width P: pitch W1: first width W2: second width

Various aspects of the disclosed embodiments will be described in detail below with reference to the accompanying drawings. Note that, as is standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present disclosure. Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. 2A-2K are schematic cross-sectional views at an intermediate stage of manufacturing a semiconductor device according to some embodiments of the present disclosure.

without

10:Semiconductor components

100:Base

110: Epitaxial layer

120: Doped area

130:Well area

150: Gate dielectric layer

150A:Part 1

150B:Part 2

150C:Part 3

160: Gate electrode

160A: First structure

160B: Second structure

200: Interlayer dielectric layer

220: Doped contact area

230: Source electrode

240: Drain electrode

Claims (20)

A semiconductor element including: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has the first conductivity type; and a doping region disposed on the epitaxial layer wherein the doped region has a second conductivity type, the second conductivity type is different from the first conductivity type; and a gate electrode is disposed through the doped region and extends into the epitaxial layer, wherein The gate electrode includes: a first structure having a first lateral dimension; and a second structure on the first structure, wherein the second structure includes a main body and a protrusion. part below the main body part, wherein the main body part has a second lateral dimension, the second lateral dimension is greater than the first lateral dimension, and the protruding part has the first lateral dimension, wherein the vertical dimension of the protruding part The dimensions are smaller than the vertical dimensions of the body portion. The semiconductor device of claim 1 further includes a gate dielectric layer, wherein the gate dielectric layer includes: a first part disposed on opposite sides and the bottom of the first structure; a second part disposed between the first structure and the protruding portion of the second structure; and a third portion disposed on opposite sides of the second structure. The semiconductor device of claim 1, wherein the protrusion of the second structure The outlet portion is vertically located between the first structure and the main body portion of the second structure. The semiconductor device of claim 1 further includes a well region disposed in the doping region, wherein the well region has the first conductivity type. The semiconductor device of claim 4, wherein the main body portion of the second structure of the gate electrode is disposed through the well region and extends into the doping region. The semiconductor device of claim 1, wherein the protruding portion of the second structure of the gate electrode is completely disposed in the doped region. The semiconductor device of claim 1, wherein the first structure of the gate electrode is disposed across the doping region and the epitaxial layer. The semiconductor device of claim 4 further includes an interlayer dielectric (ILD) layer disposed on the epitaxial layer and the gate electrode. The semiconductor device of claim 8 further includes a source electrode disposed through the interlayer dielectric layer and extending into the well region. The semiconductor device of claim 9 further includes a doped contact region under the source electrode and extending into the doped region, wherein the doped contact region has the second conductivity type. The semiconductor device of claim 1 further includes a drain electrode disposed on the other side of the substrate relative to the epitaxial layer. A method of forming a semiconductor element, including: providing a substrate and an epitaxial layer on the substrate; forming a doped region in the epitaxial layer; A gate trench is formed through the doping region and extending into the epitaxial layer, wherein the gate trench includes: a first opening having a first width; and a second opening in the first Under the opening, the second opening has a second width, and the second width is smaller than the first width; filling the second opening with a metal material; etching back the metal material to become a first gate electrode structure, wherein the top surface of the first structure is lower than the top of the second opening; depositing a gate dielectric layer on the top surface of the first structure, wherein the position of the gate dielectric layer is lower than the second the top of the opening; and forming a second structure of the gate electrode on the gate dielectric layer and filling a remaining portion of the second opening and the first opening. The method of forming a semiconductor device according to claim 12, wherein the gate dielectric layer further extends on opposite sides and bottom of the gate electrode. The method of forming a semiconductor device according to claim 12 further includes forming a well region in the doping region. The method of forming a semiconductor device according to claim 14, wherein the first opening passes through the well region and extends into the doping region, and the second opening is formed across the doping region and the epitaxial layer. The method of forming a semiconductor device according to claim 12, wherein a first depth of the first opening is less than a second depth of the second opening. The method for forming a semiconductor device according to claim 12 further includes: depositing an interlayer dielectric layer on the epitaxial layer and the gate electrode; forming a source trench through the interlayer dielectric layer and extending into the doped region; and filling the source with a source electrode Extremely grooved. The method of forming a semiconductor device according to claim 17 further includes forming a doped contact region in the source trench before filling the source electrode, wherein the doped contact region is in direct contact with the doped region. The method of forming a semiconductor device according to claim 17, wherein a first mesa width between the second structure and the source electrode is smaller than a second mesa width between the first structure and the source electrode. . The method of forming a semiconductor device according to claim 12, further comprising forming a drain electrode on the other side of the substrate relative to the epitaxial layer.

Images