TW202201798A - Semiconductor structure and high-electron mobility transistor device having the same - Google Patents

Abstract

A semiconductor structure is provided, including a substrate, a seed layer on the substrate and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice part and a second superlattice part on the first superlattice part. The first superlattice part includes several first units repetitively stacked M1 times on the seed layer. Each first unit includes a first sub-layer and a second sub-layer on the first sub-layer. In one example, the first sub-layer is a layer of Al_y1 Ga_1-y1 N with a thickness of b1 nanometers (nm), and the second sub-layer is a layer of Al_x1 Ga_1-x1 N with a thickness of a1 nanometers (nm), wherein y1 is less than x1. The second superlattice part includes several second units repetitively stacked M2 times on the first superlattice part. Each second t unit includes a third sub-layer and a fourth sub-layer on the third sub-layer. In one example, the third sub-layer is a layer of Al_y2 Ga_1-y2 N with a thickness of b2 nanometers (nm), and the fourth sub-layer is a layer of Al_x2 Ga_1-x2 N with a thickness of a2 nanometers (nm), wherein y2 is less than x2. In some embodiments, M1 and M2 are positive integers, x1,y1 and y2 are greater than 0 and less than 1, x2 is greater than 0 and equal to or less than 1, and x1 is less than x2,or x1 is equal to x2 and y1 is less than y2.

Description

Semiconductor structure and high electron mobility transistor device having semiconductor structure

The present invention relates to a semiconductor structure, and more particularly, to a semiconductor structure that can reduce wafer warpage and a high electron mobility transistor device using the semiconductor structure, which can significantly improve the electrical properties of the device.

In recent years, semiconductor devices have developed rapidly in the fields of computers and consumer electronics. At present, semiconductor device technology has been widely accepted in the product market of MOS transistors and has a high market share. Semiconductor devices are used in various electronic applications such as high power devices, personal computers, cell phones, digital cameras, and other electronic devices. These semiconductor devices are generally fabricated by depositing insulating or dielectric layers, conductive layer materials, and semiconductor layer materials on a semiconductor substrate, followed by patterning the various layers of materials using a photolithography process. Thus, circuit devices and components are formed on semiconductor substrates.

Among these devices, high-electron mobility transistors (HEMTs) devices have advantages such as high output power and high breakdown voltage, so they are widely used in high-power applications. Although existing semiconductor structures and methods of forming them can cope with their original intended use, they still have problems to be overcome in various technical aspects of their structures and fabrications. For example, in a high electron mobility transistor device, a plurality of epitaxial material layers are formed by epitaxial growth on a substrate, but the lattice of the epitaxial material layers on the heterojunction (the lattice constants of the upper and lower layer materials are different) is not the same. The lattice mismatch and the thermal mismatch with the substrate will cause stress inside the material layer, and this stress will accumulate with the increase of the thickness of the epitaxial growth. When the thickness of the epitaxial material layer exceeds the critical thickness , the stress begins to release continuously, and even cracks the substrate.

Therefore, although existing semiconductor devices can cope with their original intended use, they still have structural problems that need to be overcome at present. How to improve the semiconductor device so as to effectively avoid the occurrence of the above-mentioned substrate cracking and improve the electrical properties of the semiconductor device is an important issue for the related industry.

Some embodiments of the present invention disclose a semiconductor structure including a substrate, a seed layer on the substrate, and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice portion and a second superlattice portion located on the first superlattice portion. The first superlattice portion includes a plurality of first cells that are repeatedly stacked M1 times, and the first cells respectively include a first sublayer and a second sublayer located on the first sublayer, wherein the first sublayer has a thickness b1 Nanometer Al _y1 Ga _1-y1 N, the second sublayer is Al _x1 Ga _1-x1 N with a thickness of a1 nanometer, wherein y1 is smaller than x1. The second superlattice portion includes a plurality of second cells stacked M2 times, each of the second cells includes a third sublayer and a fourth sublayer on the third sublayer, wherein the third sublayer has a thickness b2 Nanometer Al _y2 Ga _1-y2 N, the fourth sublayer is Al _x2 Ga _1-x2 N with a thickness of a2 nanometers, wherein y2 is smaller than x2. In some embodiments, M1 and M2 are positive integers, x1, y1, y2 are respectively greater than 0 and less than 1, x2 is greater than 0 and less than or equal to 1, and x1 is less than x2, or x1 is equal to x2 and y1 is less than y2.

In some embodiments, the substrate includes a ceramic material, and the insulating layer is a single or multiple layers of insulating material covering all surfaces of the substrate.

In some embodiments, y1 is less than y2.

In some embodiments, a1 is smaller than a2, and b1 is larger than b2.

In some embodiments, y2 is greater than y1 and b2 is greater than bl. In some embodiments, a1 is greater than or equal to a2.

In some embodiments, M1 is less than M2.

In some embodiments, the total thickness of the first superlattice portion is less than the total thickness of the second superlattice portion.

In some embodiments, the first superlattice portion further includes a first dopant having a first doping concentration, the second superlattice portion further includes a second dopant having a second doping concentration, wherein the second dopant is The impurity concentration is greater than the first doping concentration.

In some embodiments, the epitaxial stack further includes a third superlattice part located on the second superlattice part, and the third superlattice part includes a third unit that is repeatedly stacked M3 times. ), the third unit includes a fifth sublayer and a sixth sublayer on the fifth sublayer, wherein the fifth sublayer is _{Aly3Ga1 -} y3N with a thickness of b3 nm, and the sixth sublayer is a3 nm thick m Al _x3 Ga _1-x3 N, where y3 is less than x3, M3 is a positive integer, y3 is greater than 0 and less than 1, x3 is greater than 0 and less than or equal to 1, and x2 is less than x3, or x2 is equal to x3 and y2 is less than y3.

In some embodiments, a2 is smaller than a3 and b2 is larger than b3.

In some embodiments, y3 is greater than y2, y2 is greater than y1 (y3>y2>y1), and b3 is greater than b2, and b2 is greater than b1 (b3>b2>b1). Furthermore, in these embodiments, a1 is greater than or equal to a2, and a2 is greater than or equal to a3 (a1≥a2≥a3).

In some embodiments, the total thickness (S1) of the first superlattice portion is less than the total thickness (S2) of the second superlattice portion, and the total thickness (S2) of the second superlattice portion is less than the third superlattice portion the total thickness (S3).

According to some embodiments of the present invention, a high-electron mobility transistor (HEMT) device is disclosed, comprising the aforementioned semiconductor structure; a first insulating layer on the epitaxial stack; a gate A pole electrode is located on the first insulating layer; a second insulating layer is located on the first insulating layer, and the second insulating layer compliantly covers the gate electrode; the source electrode and the drain electrode are respectively located on the gate electrode The opposite sides of the electrode 112 pass through the second insulating layer and the first insulating layer; a third insulating layer is located on the second insulating layer, and the third insulating layer compliantly covers the source electrode and drain electrodes.

According to some embodiments of the present invention, a method for forming a semiconductor structure is disclosed, including providing a substrate; forming a seed layer on the substrate; and growing an epitaxial stack over the seed layer, the epitaxial stack comprising: A first superlattice portion and a second superlattice portion on the first superlattice portion. The first superlattice portion includes a plurality of first cells that are repeatedly stacked M1 times, and the first cells respectively include a first sublayer and a second sublayer located on the first sublayer, wherein the first sublayer has a thickness b1 Nanometer Al _y1 Ga _1-y1 N, the second sublayer is Al _x1 Ga _1-x1 N with a thickness of a1 nanometer, wherein y1 is smaller than x1. The second superlattice portion includes a plurality of second cells stacked M2 times, each of the second cells includes a third sublayer and a fourth sublayer on the third sublayer, wherein the third sublayer has a thickness b2 Nanometer Al _y2 Ga _1-y2 N, the fourth sublayer is Al _x2 Ga _1-x2 N with a thickness of a2 nanometers, wherein y2 is smaller than x2. In some embodiments, M1 and M2 are positive integers, x1, y1, y2 are respectively greater than 0 and less than 1, x2 is greater than 0 and less than or equal to 1, and x1 is less than x2, or x1 is equal to x2 and y1 is less than y2.

According to some embodiments of the present invention, after the epitaxial stack is grown, the structure including the substrate, the seed layer and the epitaxial stack is further cooled. After cooling, a center and an edge of one of the top surfaces of the formed semiconductor structures are formed The vertical height difference is in the range -10µm to +10µm.

The following is a detailed description of the semiconductor structure of the present disclosure and the method for forming the same. It should be appreciated that the following description provides different embodiments or examples for implementing different aspects of the present disclosure. The specific elements and arrangements described below are for the purpose of simply describing the present disclosure. Of course, these are only for examples and not for limiting the scope of the present disclosure. Furthermore, if it is mentioned in the description that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements, such that they are not in direct contact. Furthermore, embodiments of the present invention may repeat reference numerals and/or letters in different instances. This repetition is for brevity and clarity and is not intended to represent a relationship between the different embodiments and/or aspects discussed.

Furthermore, spatially relative terms such as "below", "below", "below", "above", "above" and the like may be used in the following description A term to simplify the presentation of the relationships between one element or component and other elements or other components as shown in the figures. In addition to the directions depicted in the figures, such spatially relative terms include different orientations of the device in use or operation. The device may be oriented in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

Some variations of the embodiments are described below. Similar reference numerals are used to designate similar elements in the different drawings and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, and after the method, and some of the recited steps may be replaced or deleted for other embodiments of the method.

Here, the terms "about" and "approximately" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, which means that the meanings of "about" and "approximately" can still be implied without a specific description.

Embodiments of the present disclosure provide semiconductor structures and methods of forming the same. In some embodiments, an epitaxial stack is disposed above the substrate of the semiconductor structure, and the epitaxial stack includes at least two superlattice parts. In some embodiments, each superlattice portion includes a plurality of cells that are repeatedly stacked, and each cell includes two sub-layers, and the sub-layers are alternately stacked above the substrate. The present disclosure proposes that the sub-layers included in the two superlattice portions include aluminum nitride and/or aluminum gallium nitride, and the molar ratio of aluminum in one of the sub-layers in the superlattice portion of the substrate is closer to the aluminum in aluminum gallium nitride. Fraction is less than the molar fraction of aluminum in aluminum nitride or aluminum gallium nitride in one of the sublayers of the superlattice portion further away from the substrate. For example, according to some embodiments of the present disclosure, the higher molar ratio of aluminum in the aluminum gallium nitride sub-layer (the second sub-layer described in the following embodiments) is closer to the first superlattice portion of the substrate. ) e.g. having a molar fraction x1 of aluminum, a sub-layer with a higher molar fraction of aluminum in aluminum gallium nitride than in a second superlattice portion further away from the substrate (the fourth as described in the examples below The sublayer) has, for example, a molar fraction x2 of aluminum, where x1 is smaller than x2.

According to the embodiments of the present disclosure, the warpage of the wafer (or the semiconductor structure) can be greatly reduced, and the occurrence of wafer breakage or cracks can be avoided, thereby improving the quality of the semiconductor structure fabricated on the wafer. The electrical performance of components (such as transistors) can significantly improve the electrical uniformity between components fabricated on the entire wafer and improve product yield. In some of the following embodiments, a high-electron mobility transistor (HEMT) device is used as an example of a semiconductor structure, but not limited to this, and some embodiments of the present disclosure can also be used for other types of semiconductor devices.

1A-1E are schematic cross-sectional views of various intermediate stages of a process for forming a semiconductor structure according to some embodiments of the present disclosure. Referring to Fig. 1A, a substrate 102 is provided. In one embodiment, the substrate 102 may be, for example, silicon-on-insulator (SOI). According to some embodiments, the substrate 102 includes a substrate 102C and an insulating layer _102M that encapsulates the substrate _{102C .} In some embodiments, the substrate _102C comprises a ceramic material. Ceramic materials include metallic inorganic materials. In some embodiments, the substrate _102C may comprise silicon carbide, aluminum nitride (AlN), sapphire, or other suitable materials. The above-mentioned sapphire substrate is alumina. In some embodiments, the insulating layer _102M is, for example, a single or multi _- layer insulating material layer covering all surfaces (including upper and lower surfaces and all sides) of the substrate 102C. The insulating material layer is, for example, oxide, nitride, oxynitride, or other suitable insulating materials. In some other embodiments, the insulating layer _102M covering the periphery of the substrate _102C may include other suitable material layers, such as semiconductor layers, in addition to multiple layers of insulating material. In some embodiments, the semiconductor layer, such as a polysilicon layer, is disposed between the insulating material layers. In order to simplify the drawings, only a single layer of the insulating material layer 102 _M is shown in FIGS. 1A-1E , so as to clearly illustrate the formation method of the semiconductor structure.

Next, referring to FIG. 1A again, a seed layer 104 is formed on the substrate 102 . In some embodiments, the seed layer 104 may be formed of silicon (Si), aluminum nitride (AlN), or other suitable materials. Furthermore, the seed layer 104 may comprise one or more layers of suitable materials. For example, the seed layer 104 may include an aluminum nitride layer grown at a low temperature and another aluminum nitride layer grown at a high temperature on the substrate 102 . In some embodiments, the low temperature grown aluminum nitride layer has a thickness of about 1 nm, followed by another high temperature grown aluminum nitride layer with a thickness of about 200 nm. In the related drawings of this example, only a single layer of the seed layer 104 is shown to clearly illustrate the method of forming the semiconductor structure.

In some embodiments, the method for forming the seed layer 104 may include a selective area growth (SAG) process, a chemical vapor deposition (CVD) process, and a molecular-beam epitaxy process (molecular-beam). epitaxy, MBE), a solid-phase epitaxial recrystallization (SPER) step after depositing a doped amorphous semiconductor (eg, Si), by direct seeding, or other suitable processes . The chemical vapor deposition process is, for example, a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and an ultra-high vacuum chemical vapor deposition (ultra-high vacuum chemical) process. vapor deposition, UHV-CVD) process, or other suitable processes.

After that, an epitaxial stacking layer is formed over the seed layer 104 . In some embodiments, the epitaxial stack of the high electron mobility transistor structure includes a buffer layer, a channel layer, and a barrier layer. The buffer layer can help alleviate strain caused by the stress of a channel layer subsequently formed above the buffer layer and prevent defects from forming in the channel layer above.

Referring to FIG. 1B , according to some embodiments of the present disclosure, the buffer layer 106 includes at least two superlattice portions to provide stress buffering. As shown in FIG. 1B, a first superlattice part SL1 is formed over the seed layer 104, and a second superlattice part SL2 is formed over the first superlattice part SL1 .

In some embodiments, the first superlattice portion SL1 includes a plurality of first units that are repeatedly stacked M1 times, and each first unit includes two sub-layers: a first sub-layer 1061 and a second sub-layer 1062 on top of the first sub-layer 1061 . In some embodiments, the first sub-layer 1061 is Al _y1 Ga _1-y1 N with a thickness of b1 nm, and the second sub-layer 1062 is Al _x1 Ga _1-x1 N with a thickness of a1 nm, where y1 is less than x1.

In some embodiments, the second superlattice portion SL2 includes a plurality of second units that are repeatedly stacked M2 times, and each second unit includes two sub-layers: a third sub-layer 1063 and a fourth sub-layer 1064 on top of the third sub-layer 1063 . In some embodiments, the third sub-layer 1063 is Al _y2 Ga _1-y2 N with a thickness of b2 nm, and the fourth sub-layer 1064 is Al _x2 Ga _1-x2 N with a thickness of a2 nm, where y2 is less than x2.

Wherein, the above M1 and M2 are positive integers, x1, y1, y2 are respectively greater than 0 and less than 1, x2 is greater than 0 and less than or equal to 1, and x1 is less than x2, or x1 is equal to x2 and y1 is less than y2. In order to simplify the drawing, M1=M2=3 is used as an example in the drawing. Of course, the number of stacking times of sub-layers in the unit neutron of the superlattice part of the present disclosure is not limited to this.

Furthermore, according to the embodiment, the first superlattice portion SL1 may be represented as: the number of times of repeated stacking x [superlattice structure of the second sublayer/superlattice structure of the first sublayer].

According to an embodiment, the second superlattice portion SL2 may be represented as: the number of times of repeated stacking x [superlattice structure of the fourth sublayer/superlattice structure of the third sublayer].

That is, in this example, the first superlattice portion SL1 can be represented as:

M1x[a1(nm) Al _x1 Ga _1-x1 N / b1(nm) Al _y1 Ga _1-y1 N], where a1 is the thickness (nm) of the single second sublayer 1062 and b1 is the single first sublayer The thickness (nm) of 1061, M1 is the number of times the first unit is repeatedly stacked. In one example, M1 is greater than 20.

In this example, the second superlattice portion SL2 can be represented as:

_M2x [a2(nm) _{Alx2Ga1 -x2N} /b2(nm) _Aly2Ga1 -y2N], where a2 is the thickness (nm) of the single fourth sublayer 1064 and b2 is the single third sublayer The thickness (nm) of 1063, M2 is the number of times the second unit is repeatedly stacked. In one example, M2 is greater than 20.

In some embodiments, x2 is greater than 0 and less than or equal to 1, and x1 is greater than 0 and less than 1. The molar fraction _x1 of aluminum in the aluminum gallium nitride (Alx1Ga1 _-x1N ) of the second sublayer 1062 of the first superlattice portion SL1 closer to the substrate 102 is smaller than that of the second sublayer 1062 that is farther from the substrate 102 Molar fraction x2 (ie, x1>x2) of aluminum in aluminum nitride or aluminum gallium nitride ( _{Alx2Ga1 -x2N} ) of the fourth sublayer 1064 of the superlattice portion SL2. In some other embodiments, x1 is equal to x2 and y1 is less than y2. According to the superlattice structure of the first superlattice portion SL1 and the second superlattice portion SL2 proposed in the embodiment of the present disclosure, the warpage of the wafer can be reduced, and crack-free of the wafer can be avoided.

Furthermore, the thickness of the sub-layer with a higher molar ratio of aluminum in the second superlattice portion SL2 farther from the substrate 102 is greater than that in the first superlattice portion SL1 closer to the substrate 102 with a higher molar ratio of aluminum The thickness of the sub-layer can increase the tensile stress of the second superlattice portion SL2. In some embodiments, a1 is less than a2. That is, the thickness a1 (nm) of the single second sub-layer 1062 is smaller than the thickness a2 (nm) of the single fourth sub-layer 1064 ( a1 > a2 ), and the tensile stress of the second superlattice portion SL2 is greater than that of the first superlattice SL2 Tensile stress of the lattice portion SL1.

In some embodiments, y1 and y2 are respectively greater than 0 and less than 1, and y1 is less than y2. That is, the molar fraction y1 of aluminum in the aluminum gallium nitride (Al _y1 Ga _1-y1 N) of the first sublayer 1061 of the first superlattice portion SL1 closer to the substrate 102 is smaller than that farther from the substrate 102 Molar fraction y2 (y1>y2) of aluminum in aluminum gallium nitride (Al _y2 Ga _1-y2 N) of the third sublayer 1063 of the second superlattice portion SL2.

Furthermore, in some embodiments where a1 is less than a2, b1 is greater than b2. That is, the thickness b1 (nm) of the single first sub-layer 1061 containing aluminum gallium nitride is greater than the thickness b2 (nm) of the single third sub-layer 1063 containing aluminum gallium nitride (b1>b2), which can increase the second Tensile stress of superlattice portion SL2.

In addition, in some other embodiments, a1 is greater than or equal to a2, and b2 is greater than b1, which can also increase the tensile stress of the second superlattice portion SL2.

In some embodiments, x1 is greater than y1 and x2 is greater than y2. That is, the molar fraction x1 of aluminum in the second sublayer 1062 belonging to the first superlattice portion SL1 in aluminum gallium nitride ( _{Alx1Ga1 -x1N} ) is larger than that of aluminum in the first sublayer 1061. Molar fraction y1 in aluminum gallium nitride (Al _y1 Ga _1-y1 N). The molar fraction x2 of aluminum belonging to the fourth sublayer 1064 of the second superlattice portion SL2 in aluminum nitride or aluminum gallium nitride ( _{Alx2Ga1 -x2N} ) is greater than that of the aluminum of the third sublayer 1063 Molar fraction y2 in aluminum gallium nitride (Al _y2 Ga _1-y2 N).

Furthermore, in some embodiments, x1 is in the range of 0.6-1, and x2 is in the range of 0.8-1. In some embodiments, y1 is in the range of 0.1-0.3, and y2 is in the range of 0.15-0.4. Please refer to Table 1, which lists the aluminum molar ratio ranges for the sub-layers of the superlattice portion of the four experiments in some embodiments according to the present disclosure containing 2 superlattice portions. Experiment 1 is that x1 is less than x2 and y1 is less than y2. In experiment 2, x1 is equal to x2, and y1 is less than y2. Experiment 3 is that x1 is less than x2, and y1 is less than y2. Experiment 4 is that x1 is less than x2 and y1 is equal to y2.

Table 1 x1 y1 x2 y2 Experiment 1 0.6~0.7 0.1~0.3 0.8~0.9 0.15~0.4 Experiment 2 0.8~1 0.1~0.3 0.8~1 0.15~0.4 Experiment 3 0.8~0.9 0.1~0.15 0.9~1 0.2~0.25 Experiment 4 0.8~0.9 0.15~0.25 0.9~1 0.15~0.25

In some embodiments, M1 is smaller than M2. That is, the number M1 of repeated stacking of the first cells included in the first superlattice portion SL1 is smaller than the number M2 of repeated stacking of the second cells included in the second superlattice portion SL2 .

Furthermore, in some embodiments, after the above-mentioned sub-layers are epitaxially grown to complete the buffer layer 106 as shown in FIG. 1B , the total thickness of the first superlattice portion SL1 formed is smaller than that of the second superlattice portion. Total thickness of SL2.

According to the above, the superlattice structures of the first superlattice portion SL1 and the second superlattice portion SL2 proposed by some embodiments of the present disclosure can greatly reduce the warpage of the wafer, for example, the center of the wafer surface and the A vertical height difference of the edge is in the range of ±10µm. The embodiment of the present disclosure avoids the generation of wafer fragments or cracks, thereby improving the electrical performance of each semiconductor device (such as a transistor) fabricated on the wafer, and significantly improving the fabrication of multiple semiconductor devices on the entire wafer. Electrical uniformity between components improves product yield.

In addition, dopants can also be added to the superlattice portion of the embodiment of the present disclosure, and the doping concentration of the superlattice portion farther from the substrate 102 is higher than that of the superlattice portion closer to the substrate 102 . In some embodiments, the first superlattice portion SL1 further includes a first dopant having a first doping concentration, the second superlattice portion SL2 further includes a second dopant having a second doping concentration, and the third The second doping concentration is greater than the first doping concentration. In some embodiments, the above-mentioned dopants, such as the first dopant and the second dopant, are independently selected from carbon or iron.

In some embodiments, the respective sub-layers of the first superlattice portion SL1 and the second superlattice portion SL2 may be formed by hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), organometallic chemistry It is formed by a vapor deposition method (metalorganic chemical vapor deposition, MOCVD), a combination of the aforementioned methods, or a similar method.

Although in the embodiment shown in FIG. 1B, the buffer layer 106 includes two superlattice portions, in some other embodiments, the buffer layer 106 includes three or more superlattice portions.

After that, referring to FIG. 1C , a channel layer 108 is epitaxially formed on the buffer layer 106 . In some embodiments, the channel layer 108 includes an undoped III-V semiconductor material. For example, the channel layer 108 may be formed of undoped gallium nitride (GaN), but the invention is not limited thereto. In some other embodiments, the channel layer 108 includes AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or combinations thereof. In some embodiments, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metal-organic chemical vapor deposition (MOCVD), other suitable methods, or a combination thereof may be used, while A channel layer 108 is formed. In this example, the channel layer 108 is, for example, a gallium nitride layer with a thickness of about 400 nm.

Next, a barrier layer 110 is epitaxially formed on the channel layer 108 . In some embodiments, barrier layer 110 includes undoped III-V semiconductor material. For example, the barrier layer 110 is formed of undoped aluminum gallium nitride (AlxGa1-xN, where 0>x>1), but the invention is not limited thereto. In some other embodiments, the barrier layer 110 may also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or a combination thereof. For example, the barrier layer 110 may be formed over the channel layer 108 using molecular beam epitaxy, metal organic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination thereof. In this example, the barrier layer 110 is, for example, a gallium aluminum nitride layer with a thickness of about 12.5 nm.

Therefore, in the high electron mobility transistor structure according to some of the above-mentioned embodiments, an epitaxial stack 111 above the seed layer 104 includes the buffer layer 106, the channel layer 108 and the barrier layer 110, such as the 1C layer as shown in the figure.

In addition, in some embodiments, in addition to the aforementioned buffer layer 106 , channel layer 108 and barrier layer 110 , the epitaxial stack 111 may also include other layers; for example, a carbon layer may be formed between the buffer layer 106 and the channel layer 108 A carbon-doped layer is used to increase the breakdown voltage of the semiconductor structure. As shown in FIG. 1C , a carbon-containing gallium nitride (C-GaN) layer 107 is epitaxially formed on the second superlattice portion SL2 to serve as an electrical buffer layer, and the channel layer 108 is located on the carbon-containing gallium nitride (C-GaN) layer 107 . on the gallium nitride layer 107.

According to the above, in some embodiments, the channel layer 108 and the barrier rib layer 110 include different materials, such as a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer, respectively, so that the channel layer 108 and the barrier rib layer are formed of different materials, respectively. A hetero interface is formed between the layers 110 . A two-dimensional electron gas (2DEG) (not shown) can be formed on the hetero interface through the band gap of the hetero materials. Semiconductor devices formed in accordance with some embodiments, such as high electron mobility transistor (HEMT) devices, utilize a two-dimensional electron gas as conductive carriers.

After the above-mentioned epitaxial material layers (eg, including the buffer layer 106 , the carbon-containing gallium nitride layer 107 , the channel layer 108 and the barrier layer 110 ) are grown, the material layers are cooled. After cooling, desired elements are formed on the epitaxial stack 111 .

In some embodiments, a semiconductor device, such as a high electron mobility transistor, is formed on the epitaxial stack 111, and an interlayer dielectric layer IL _M is formed to cover the semiconductor device (such as a semiconductor device _SD shown in FIG. 1E later). and an interlayer dielectric layer IL _M , wherein the interlayer dielectric layer IL _M includes multiple insulating layers).

In some embodiments, the semiconductor device _SD includes a gate electrode, and a source electrode 116 and a drain electrode 118 formed on opposite sides of the gate electrode, respectively. According to some embodiments of the present disclosure, a semiconductor device _SD is described by taking the fabrication of an enhanced mode (normally-off) high electron mobility transistor as an example. In some embodiments, a doped group III-V semiconductor material is formed on the barrier layer 110, and a patterning process is performed to form a doped group III-V semiconductor layer 112P under the corresponding gate electrode formed later .

As shown in FIG. 1D , a doped III-V semiconductor layer 112P is formed on the barrier layer 110 . In some embodiments, the doped III-V semiconductor layer 112P may include appropriate dopants, such as P-type doped gallium nitride. In some other embodiments, the doped III-V semiconductor layer 112P may include P-type doped aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs) ), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), deepened indium gallium arsenide (InGaAs), other suitable III-V materials, or the foregoing combination. In addition, the formation method of the doped III-V semiconductor layer 112P may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial process, ion implantation or in-situ doping process. In this example, the doped III-V semiconductor layer 112P is, for example, a p-type doped gallium nitride (p-GaN) layer with a thickness of about 80 nm.

Afterwards, as shown in FIG. 1D , according to some embodiments, a first insulating layer 114 is formed over the epitaxial stack 111 and conformably covers the doped III-V semiconductor layer 112P. In some embodiments, the first insulating layer 114 may be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Furthermore, the first insulating layer 114 can be produced by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a high-density plasma chemical vapor deposition (HDP-CVD) process. or a combination of the foregoing.

As shown in FIG. 1E, a gate electrode 112 is formed over the first insulating layer 114, and the gate electrode 112 is connected to the doped III-V semiconductor layer 112P. In some embodiments, the gate electrode 112 may include metal materials, metal silicides, polysilicon, other suitable conductive materials, or combinations thereof. A Schottky contact is formed between the gate electrode 112 and the doped III-V semiconductor layer 112P. In some embodiments, the gate electrode 112 may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (eg, sputtering), or the like.

In some embodiments, a second insulating layer 115 is formed over the first insulating layer 114 , and the second insulating layer 115 compliantly covers the gate electrode 112 , as shown in FIG. 1E . The manufacturing process and material of the second insulating layer 115 may be similar or the same as those of the first insulating layer 114 , which will not be repeated here.

After that, a source electrode 116 and a drain electrode 118 are respectively formed on opposite sides of the gate electrode 112 . In some embodiments, as shown in FIG. 1E , the source electrode 116 and the drain electrode 118 are located on the channel layer 108 and are in electrical contact with the channel layer 108 . In some embodiments, the source electrode 116 and the drain electrode 118 comprise conductive materials such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), tantalum nitride (TaN), titanium nitride (TiN), tungsten silicide (WSi ₂ ), combinations of the foregoing, or similar materials. In some embodiments, source electrode 116 and drain electrode 118 may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (eg, sputtering), electron beam evaporation, or the like. In some embodiments, after the material layers for forming the source electrode 116 and the drain electrode 118 are deposited, a high temperature thermal process such as a rapid thermal annealing process is further included to form the source-drain ohmic contact.

Next, in some embodiments, as shown in FIG. 1E , a third insulating layer 124 is formed over the second insulating layer 115 , and the third insulating layer 124 compliantly covers the source electrode 116 and the drain electrode 118 . The manufacturing process and material of the third insulating layer 124 may be similar or the same as those of the first insulating layer 114 , which will not be repeated here. The first insulating layer 114, the second insulating layer 115, and the third insulating layer 124 in FIG. 1E constitute an interlayer dielectric layer IL _M to cover the semiconductor element S _D .

FIG. 2 is a schematic cross-sectional view of another semiconductor structure according to some embodiments of the present disclosure. In some of the aforementioned embodiments shown in FIGS. 1A-1E, the buffer layer 106 includes two superlattice portions, while in some embodiments shown in FIG. 2, the buffer layer 106 includes three superlattice portions.

Referring to FIG. 2, the buffer layer 106 includes a first superlattice portion SL1 on the seed layer 104, a second superlattice portion SL2 on the first superlattice portion SL1, and a third superlattice portion (third The superlattice part) SL3 is on the second superlattice part SL2.

The first superlattice portion SL1 includes a plurality of first cells stacked M1 times repeatedly, and each of the first cells includes a first sublayer 1061 and a second sublayer 1062 on the first sublayer 1061 . The first sub-layer 1061 is Al _y1 Ga _1-y1 N with a thickness of b1 nm, and the second sub-layer 1062 is Al _x1 Ga _1-x1 N with a thickness of a1 nm, wherein y1 is smaller than x1.

The second superlattice portion SL2 includes a plurality of second cells stacked M2 times repeatedly, and each of the second cells includes a third sublayer 1063 and a fourth sublayer 1064 on the third sublayer 1063 . In some embodiments, the third sub-layer 1063 is Al _y2 Ga _1-y2 N with a thickness of b2 nm, and the fourth sub-layer 1064 is Al _x2 Ga _1-x2 N with a thickness of a2 nm, where y2 is less than x2.

The third superlattice portion SL3 includes a plurality of third cells stacked M3 times repeatedly, and each third cell includes a fifth sublayer 1065 and a sixth sublayer 1066 on the fifth sublayer 1065 . In some embodiments, the fifth sublayer 1065 is Aly3Ga1-y3N with a thickness of b3 nm, and the sixth sublayer 1066 is _{Alx3Ga1 - x3N} with a thickness of a3 nm, where _y3 is less than x3.

Similar to the above example, the third superlattice portion SL3 can also be expressed as:

M3x[a3(nm) _{Alx3Ga1 -} x3N/b3(nm) _{Aly3Ga1 -} y3N], where a3 is the thickness (nm) of the single fifth sublayer 1065 and b3 is the single sixth sublayer 1066 thickness (nm), M3 is the number of times the third unit is repeatedly stacked. In one example, M3 is greater than 20.

In some embodiments, M1, M2, and M3 are positive integers, x1, y1, y2, and y3 are respectively greater than 0 and less than 1, x2 and x3 are greater than 0 and less than or equal to 1, and x1>x2>x3. That is, the molar fraction _x3 of aluminum in the sixth sublayer 1066 of the third superlattice portion SL3 farther from the substrate 102 in Alx3Ga1 _-x3N is greater than that of the fourth sublayer SL2 of the second superlattice portion SL2 The molar fraction x2 of the aluminum of the layer 1064 in _{Alx2Ga1 -x2N} is greater than that of the second sublayer 1062 of the aluminum in the _{Alx1Ga1 -} x1N closer to the first superlattice portion SL1 of the substrate 102. Molar fraction x1 (ie 0>x1>x2>x3≤1). In some other embodiments, x1 is less than x2, x2 is equal to x3 and y1 is less than y2, and y2 is less than y3.

Furthermore, the thickness of the sub-layer with higher molar fraction of aluminum in the third superlattice portion SL3 farther from the substrate 102 is greater than the thickness of the sub-layer with higher molar fraction of aluminum in the second superlattice portion SL2, It is also larger than the sub-layer thickness with higher molar fraction of aluminum in the first superlattice portion SL1 closer to the substrate 102 , that is, a1>a2>a3. Furthermore, in some embodiments, b1>b2>b3. That is, the thickness b1 (nm) of the single first sublayer 1061 containing aluminum gallium nitride is greater than the thickness b2 (nm) of the single third sublayer 1063 containing aluminum gallium nitride, and the single first sublayer 1063 containing aluminum gallium nitride The thickness b3 (nm) of the five sublayers 1065 . In this way, the tensile stress of the third superlattice portion SL3 is greater than that of the second superlattice portion SL2, and the tensile stress of the second superlattice portion SL2 is greater than that of the first superlattice portion Tensile stress of SL1.

Additionally, in some other embodiments, furthermore, in some embodiments, b1>b2>b3. That is, the thickness b1 (nm) of the single first sublayer 1061 containing aluminum gallium nitride is greater than the thickness b2 (nm) of the single third sublayer 1063 containing aluminum gallium nitride, and the single first sublayer 1063 containing aluminum gallium nitride The thickness b3 (nm) of the five sublayers 1065 . In this way, the tensile stress of the first superlattice portion SL1 , the second superlattice portion SL2 and the third superlattice portion SL3 can be gradually increased in sequence.

In some other embodiments, a1 is greater than or equal to a2, a2 is greater than or equal to a3 (a1≥a2≥a3), and b3 is greater than b2, and b2 is greater than b1 (b3>b2>b1), so that the first superlattice portion can also be The tensile stress of SL1 , the second superlattice portion SL2 and the third superlattice portion SL3 gradually increases sequentially.

In some embodiments, y1, y2, and y3 are respectively greater than 0 and less than 1, and y1>y2>y3. That is, the molar fraction y1 of aluminum in the first sublayer 1061 of the first superlattice portion SL1 closer to the substrate 102 in Al _y1 Ga _1-y1 N is smaller than that of the third superlattice portion SL2 of the second superlattice portion SL2 Molar fraction _y2 of aluminum of sublayer 1063 in Aly2Ga1 _- y2N, and molar fraction of aluminum of third sublayer 1063 of second superlattice portion SL2 in _{Aly2Ga1 -} y2N The ratio y2 is also smaller than the molar ratio y3 of aluminum in the Al _y3 Ga _1-y3 N of the fifth sublayer 1065 of the third superlattice portion SL3 further away from the substrate 102 .

Furthermore, in some embodiments, x1 is in the range of 0.6-1, x2 is in the range of 0.8-1, and x3 is in the range of 0.9-1. In some embodiments, y1 is in the range of 0.1-0.3, y2 is in the range of 0.15-0.4, and y3 is in the range of 0.2-0.5.

Please refer to Table 2, which lists the aluminum molar ratio ranges for the sublayers of the superlattice portions of the four experiments according to some embodiments containing 3 superlattice portions according to the present disclosure. Experiment 1 is that x1 is less than x2, x2 is less than x3; y1 is less than y2, and y2 is less than y3. In experiment 2, x1 is equal to x2, and x2 is less than x3; y1 is less than y2, and y2 is less than y3. In experiment 3, x1 is less than x2, x2 is less than x3, and y1 is less than y2, and y2 is less than y3. Experiment 4 is that x1 is less than x2, x2 is less than x3, y1 is equal to y2, and y2 is less than y3.

Table 2 x1 y1 x2 y2 x3 y3 Experiment 1 0.6~0.7 0.1~0.3 0.8~0.9 0.15~0.4 0.9~1 0.2~0.5 Experiment 2 0.8~1 0.1~0.3 0.8~1 0.15~0.4 0.95~1 0.2~0.5 Experiment 3 0.8~0.9 0.1~0.15 0.9~1 0.2~0.25 0.95~1 0.3~0.35 Experiment 4 0.8~0.9 0.15~0.25 0.9~1 0.15~0.25 0.95~1 0.35~0.4

In some embodiments, M1>M2>M3. That is, the number M1 of repeated stacking of the first cells included in the first superlattice portion SL1 is smaller than the number M2 of repeated stacking of the second cells included in the second superlattice portion SL2, and the second superlattice portion SL2 The number M2 of repeated stacking of the included second cells is smaller than the number M3 of repeated stacking of the third cells included in the third superlattice portion SL3 .

Furthermore, in some embodiments, after the above-mentioned sub-layers are epitaxially grown to complete the buffer layer 106 as shown in FIG. 2 , the total thickness of the first superlattice portion SL1 formed is smaller than that of the second superlattice portion. The total thickness of SL2 and the total thickness of the second superlattice portion SL2 are smaller than the total thickness of the third superlattice portion SL3.

In addition, dopants can also be added to the superlattice portion of the embodiment of the present disclosure, and the doping concentration of the superlattice portion farther from the substrate 102 is higher than that of the superlattice portion closer to the substrate 102 . In some embodiments, the first superlattice portion SL1 further includes a first dopant having a first doping concentration, the second superlattice portion SL2 further includes a second dopant having a second doping concentration, and the third The superlattice portion SL3 further includes a third dopant having a third doping concentration, the second doping concentration is greater than the first doping concentration, and the third doping concentration is greater than the second doping concentration. In some embodiments, the above-mentioned dopants, such as the first dopant, the second dopant, and the third dopant, are independently selected from carbon or iron.

The other material layers, the processes performed or the materials used in the structure shown in Figure 2 are the same or similar to the processes and materials used in the other material layers in the structure shown in Figures 1A-1E, It is not repeated here. According to the first superlattice portion SL1, the second superlattice portion SL2 and the third superlattice portion SL3 proposed in some embodiments as shown in FIG. 2, the warpage of the wafer can be greatly reduced (for example, making The vertical height difference between the center and edge of the wafer surface is within the range of ±10µm or less), and can avoid wafer breakage or cracks (cracks), thereby enhancing the individual semiconductor components fabricated on the wafer. (eg transistors), and significantly improve the electrical uniformity between multiple semiconductor devices fabricated on the entire wafer. Therefore, the proposed superlattice structure according to some embodiments of the present disclosure can significantly improve product yield.

FIG. 3 is a graph showing in-situ wafer curvature of a semiconductor structure during and after epitaxial growth of a semiconductor structure according to some embodiments of the present disclosure. The horizontal axis is the epitaxial growth time (seconds), and the vertical axis is the in-situ wafer warpage value.

In the semiconductor structure of some embodiments, the substrate 102 includes a substrate 102C having a ceramic material and an insulating layer _102M encapsulating the substrate _{102C .} As shown in FIG. 3 , after the first superlattice portion SL1 and the second superlattice portion SL2 are epitaxially grown on the substrate 102 , they have the aluminum content configuration of the sublayers of the superlattice portion in the above-mentioned embodiment. , before the cooling step, the sub-layers of the superlattice have tensile stress, the in-situ wafer warpage curve decreases, and the wafer warpage value is negative at this time, That is, the wafer has a concave cross-section. Then, the cooling step is performed, the sub-layers of the superlattice part generate compressive stress, and the compressive stress and the previous tensile stress compensate each other, and the in-situ wafer warpage curve climbs upward, that is, The warpage value is increased. When the warpage value is positive, the wafer has a convex cross-section.

Therefore, according to the superlattice structures of the sublayers proposed by the first superlattice portion SL1 and the second superlattice portion SL2 according to some embodiments of the present disclosure, due to the difference between the aluminum contents in the sublayers of the aforementioned superlattice portions With this arrangement, the tensile stress generated during the epitaxial growth of these sub-layers can be compensated by the compressive stress generated during cooling, so that the original concave cross-section gradually becomes a flat surface. Therefore, the surfaces of the cooled substrate 102 and the epitaxial stack 111 will be more flat, greatly reducing the degree of wafer bow, thereby improving the subsequent fabrication of components on the wafer (such as high electron mobility batteries). crystal) electrical performance.

FIG. 4 is a schematic diagram of a warped semiconductor structure. The figure simply illustrates a semiconductor structure according to some embodiments of the present disclosure, including the substrate 102 , the seed layer 104 , and the epitaxial stack 111 described above. According to some embodiments, the wafer bow of a semiconductor structure may be defined as the height of the center of the wafer surface, eg, in the Z-direction (or vertical), and the edge of the wafer surface, eg, in the Z-direction height, the height difference between the two. In some examples, a reference surface of the epitaxial stack 111 (eg, the upper surface of the barrier layer 110 ) can be used as the wafer surface in the definition to measure the height difference between the center and the edge to obtain the wafer warpage. Curve value. In some other examples, a reference surface of the substrate 102 (such as the bottom surface of the substrate 102 ) can also be used as the wafer surface in the definition to measure the height difference between the center and the edge to obtain the wafer warpage numerical value. There are no restrictions here.

As shown in FIG. 4, according to some embodiments of the present disclosure, a top surface 111a of the epitaxial stack 111 formed after the cooling step, such as the top surface of the barrier layer 110, has a vertical height of the center O and the edge E thereof The difference H (along the Z direction) is in the range -10µm to +10µm.

Compared with the existing superlattice structures, the superlattice structures proposed by the semiconductor structures of some embodiments of the present disclosure can produce wafers with less warpage. When the degree of wafer warpage is controlled, the electrical uniformity of all components fabricated on the entire wafer can also be significantly improved, thereby improving product yield. In the embodiment, several simulation experiments are also performed on the degree of wafer warpage to measure the initial bow value and the final bow value of the wafer. The following is a description of the data results of several simulation experiments.

Figures 5A, 5B, and 5C respectively show cross-sectional schematic views of the semiconductor structures of the control group 1, the control group 2, and the experiment 1 in the simulation experiment. Among them, the control group 1 (Fig. 5A) is a semiconductor structure using a single superlattice portion SL _S , and the control group 2 (Fig. 5B) is a semiconductor structure using two superlattice portions SL _C2 and SL _C1 . 1 (FIG. 5C) uses the semiconductor structure shown in FIG. 1C according to an embodiment of the present disclosure.

The difference between the three groups of semiconductor structures in this simulation experiment lies in the superlattice layer. The other material layers that are the same as those in the above-mentioned embodiment use the same labels. For example, there is a carbon-containing gallium nitride layer 107 above the superlattice layer in sequence. (about 1 µm of C-GaN), a channel layer 108 (about 400 nm of GaN), a barrier layer 110 (about 12.5 nm of Al _0.25 GaN) and a P-type doped gallium nitride material layer 1120 (about 80 nm of p-type GaN, which is subsequently fabricated to form a doped III-V semiconductor layer 112P as shown in FIG. 1D ). For details such as relative positions and materials of these material layers, please refer to the above description, and will not be repeated here.

The superlattice layer systems of the three groups of semiconductor structures are represented as follows:

The superlattice portion SLS of the control group 1: 180×[8 nm AlN/10 nm Al _0.1 Ga _{0.9 N} ].

In control group 1 (Fig. 5A), the superlattice portion SLS includes a cell repeated for 180 times of stacking, and the cell includes Al _0.1 Ga _0.9 N with a thickness of 10 nm and AlN with a thickness of 8 nm above Al _{0.1 Ga0.9N} .

Superlattice portion SL _C1 of control group 2 (Fig. 5B): 25×[5 nm AlN/28 nm Al _0.2 Ga _0.8 N]; and

The superlattice portion SL _C2 of the control group 2: 168×[8 nm AlN/10 nm Al _0.1 Ga _0.9 N]. The superlattice portion SL _C2 is located above the superlattice portion SL _C1 .

The first superlattice portion SL1 of Experiment 1 (Fig. 5C): 25x[12nm Al _0.74 Ga _0.26 N /26 nm Al _0.17 Ga _0.83 N]; and

The second superlattice portion SL2 of Experiment 1: 80×[20 nm Al _1.00 Ga _0.0 N /18 nm Al _0.23 Ga _0.77 N].

Fig. 6 shows the wafer warpage results of control group 1, control group 2 and experiment 1 in the simulation experiment. The horizontal axis is the initial bow value of the wafer, and the vertical axis is the final bow value of the wafer. ▲ is the wafer warpage result of control group 1, ▓ is the wafer warpage result of control group 2, and ● is the wafer warpage result of experiment 1.

In the simulation experiments, the semiconductor structure of the control group 1 using a single superlattice _SLS , the measured final warpage value is in the range of 10µm~60µm, and the final warpage value is above about 50µm, and The final warpage value increases with the initial warpage value. Using the semiconductor structure of control 2 with two superlattice parts SL _C2 and SL _C1 , the measured final warpage values are in the range of about 50 µm to about 80 µm, with the initial warpage in the range of 10 µm to 60 µm. . However, using the semiconductor structure of Experiment 1 of an embodiment of the present disclosure, the measured final warpage value does not exceed about 40 μm when the initial warpage is in the range of 10 μm to 60 μm, and in some experiments the final warpage value does not exceed about 40 μm. More than about 20µm, and in some experiments the final warpage value did not exceed about 10µm. Therefore, the superlattice structure proposed in some embodiments of the present disclosure does greatly reduce the final warpage state of the wafer. Generally speaking, the final warpage value is about 50µm or more, and the wafer will be chipped or cracked. Therefore, if the final warpage value of 50 μm is set as a critical value of the wafer bow yield rate, the superlattice structure proposed in some embodiments of the present disclosure can improve the wafer warpage yield rate to 100% .

To sum up, in the semiconductor device provided by some embodiments of the present disclosure, the superlattice structures of the first superlattice portion SL1 and the second superlattice portion SL2 included in the semiconductor device can reduce the warpage of the wafer (for example, , a vertical height difference between the center and the edge of the final wafer surface is in the range of -10µm~+10µm), and the generation of wafer fragments or cracks can be avoided. Therefore, applying the semiconductor device provided by the embodiments of the present disclosure can also improve the electrical performance of each semiconductor device (eg, transistor) fabricated on the wafer, and significantly improve the performance of semiconductor devices fabricated on the entire wafer. The electrical uniformity between the two, thereby improving the product yield. In addition, the method for forming the semiconductor device proposed in the embodiment is also compatible with the existing process, and the manufacturing cost is not increased, and the wafer warpage can be greatly improved.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the appended patent application.

102: substrate 102 _C : substrate 102 _M : insulating layer 104: seed layer 106: buffer layer SL1: first superlattice portion 1061: first sublayer 1062: second sublayer SL2: second superlattice portion 1063: Third sublayer 1064: Fourth sublayer SL3: Third superlattice portion 1065: Fifth sublayer 1066: Sixth sublayer 107: Carbon-containing gallium nitride layer 108: Channel layer 110: Barrier layer 111 : epitaxial stack _SD : semiconductor element ILM : interlayer dielectric layer _112P : doped III-V semiconductor layer 112 : gate electrode 116 : source electrode 118 : drain electrode 114 : first insulating layer 115 : first insulating layer 115 Second insulating layer 124: Third insulating layer

1A-1E are schematic cross-sectional views of various intermediate stages of a process for forming a semiconductor structure according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view of another semiconductor structure according to some embodiments of the present disclosure. FIG. 3 is a graph showing in-situ wafer curvature of a semiconductor structure during and after epitaxial growth of a semiconductor structure according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram of a warped semiconductor structure. Figures 5A, 5B, and 5C respectively show cross-sectional schematic views of the semiconductor structures of the control group 1, the control group 2, and the experiment 1 in the simulation experiment. Among them, the control group 1 (Fig. 5A) is a semiconductor structure using a single superlattice portion SL _S , and the control group 2 (Fig. 5B) is a semiconductor structure using two superlattice portions SL _C2 and SL _C1 . 1 (FIG. 5C) is a semiconductor structure using an embodiment of the present disclosure. Fig. 6 shows the wafer warpage results of control group 1, control group 2 and experiment 1 in the simulation experiment. The horizontal axis is the initial bow value of the wafer, and the vertical axis is the final bow value of the wafer.

102: Substrate

102 _C : Substrate

102 _M : insulating layer

104: seed layer

106: Buffer layer

SL1: The first superlattice part

1061: First sublayer

1062: Second sublayer

SL2: Second Superlattice Section

1063: Third sublayer

1064: Fourth sublayer

Claims (29)

A semiconductor structure, comprising: a substrate; a seed layer on the substrate; and an epitaxial stack on the seed layer, the epitaxial stack comprising: a first superlattice portion ( first superlattice part), located on the seed layer, the first superlattice part includes a plurality of first units stacked M1 times repeatedly, and each of the first units includes: a first sublayer, which is Al _y1 Ga _1-y1 N with a thickness of b1 nm; and a second sublayer on the first sublayer, and the second sublayer is Al _x1 Ga1 _-x1 N with a thickness of a1 nm, where y1 less than x1; a second superlattice part, located on the first superlattice part, the second superlattice part includes a plurality of second units stacked M2 times, the Each of the second units includes: a third sub-layer of Al _y2 Ga _1-y2 N with a thickness of b2 nm; and a fourth sub-layer on the third sub-layer, and the fourth sub-layer has a thickness of a2 Nanometer Al _x2 Ga _1-x2 N, where y2 is less than x2; where M1 and M2 are positive integers, x1, y1, y2 are respectively greater than 0 and less than 1, x2 is greater than 0 and less than or equal to 1, and x1 is less than x2, or x1 is equal to x2 and y1 is less than y2. The semiconductor structure of claim 1, wherein a vertical height difference between a center and an edge of a top surface of the semiconductor structure is in the range of -10µm to +10µm. The semiconductor structure of claim 1, wherein y1 is less than y2. The semiconductor structure of claim 3, wherein x1 is greater than y1 and x2 is greater than y2. The semiconductor structure of claim 1, wherein a1 is less than a2. The semiconductor structure of claim 5, wherein b1 is greater than b2. The semiconductor structure of claim 1, wherein y2 is greater than y1, and b2 is greater than b1. The semiconductor structure of claim 1, wherein a1 is greater than or equal to a2. The semiconductor structure of claim 1, wherein M1 is smaller than M2. The semiconductor structure of claim 1, wherein a total thickness of the first superlattice portion is less than a total thickness of the second superlattice portion. The semiconductor structure of claim 1, wherein x1 is in the range of 0.6~1, and x2 is in the range of 0.8~1. The semiconductor structure of claim 1, wherein y1 is in the range of 0.1-0.3, and y2 is in the range of 0.15-0.4. The semiconductor structure of claim 1, wherein the substrate comprises a base material and at least one insulating material layer. The semiconductor structure of claim 13, wherein the substrate comprises a ceramic material, the at least one insulating material layer covers the substrate, and the at least one insulating material layer is oxide, nitride, oxynitride or the foregoing combination. The semiconductor structure of claim 1, wherein the first superlattice portion further comprises a first dopant having a first doping concentration, and the second superlattice portion further comprises a second dopant having a second doping concentration a dopant, wherein the second doping concentration is greater than the first doping concentration. The semiconductor structure of claim 15, wherein the first dopant and the second dopant are independently selected from carbon or iron. The semiconductor structure of claim 1, wherein the epitaxial stack further comprises: a third superlattice part located on the second superlattice part, the third superlattice part comprising repeated stacks A plurality of third units of order M3, the third units each include: a fifth sublayer, which is Al _y3 Ga _1-y3 N with a thickness of b3 nm; and a sixth sublayer, located in the On the fifth sublayer, and the sixth sublayer is Al _x3 Ga _1-x3 N with a thickness of a3 nanometers, where y3 is less than x3; wherein, M3 is a positive integer, y3 is greater than 0 and less than 1, and x3 is greater than 0 and less than or equal to 1, and x2 is less than x3, or x2 is equal to x3 and y2 is less than y3. The semiconductor structure of claim 17, wherein when x2 is less than x3, y2 is less than y3. The semiconductor structure of claim 17, wherein a2 is less than a3. The semiconductor structure of claim 19, wherein b2 is greater than b3. The semiconductor structure of claim 17, wherein y3 is greater than y2, y2 is greater than y1, b3 is greater than b2, and b2 is greater than b1. The semiconductor structure of claim 21, wherein a1 is greater than or equal to a2, and a2 is greater than or equal to a3. The semiconductor structure of claim 17, wherein a total thickness of the first superlattice portion is less than a total thickness of the second superlattice portion, and a total thickness of the second superlattice portion is less than the third superlattice the total thickness of the part. The semiconductor structure of claim 17, wherein M2 is less than M3. The semiconductor structure of claim 17, wherein x3 is in the range of 0.9 to 1, and y3 is in the range of 0.2 to 0.5. The semiconductor structure of claim 17, wherein the first superlattice portion further comprises a first dopant having a first dopant concentration, and the second superlattice portion further comprises a second dopant having a second dopant concentration a dopant, the third superlattice portion further includes a third dopant having a third doping concentration, wherein the second doping concentration is greater than the first doping concentration, and the third doping concentration is greater than the second doping concentration impurity concentration. The semiconductor structure of claim 1, wherein the epitaxial stack further comprises: a channel layer over the second superlattice portion; and A barrier layer is located on the channel layer. The semiconductor structure of claim 27, wherein the epitaxial stack further comprises: a carbon-containing gallium nitride (C-GaN) layer on the second superlattice portion, and the channel layer on the carbon-containing gallium nitride layer; and A P-type doped gallium nitride layer is located on the barrier layer. A high-electron mobility transistor (HEMT) device, comprising: The semiconductor structure according to any one of the preceding claims 1 to 28; a first insulating layer on the epitaxial stack; a gate electrode, located on the first insulating layer; a second insulating layer on the first insulating layer, and the second insulating layer compliantly covers the gate electrode; The source electrode and the drain electrode are respectively located on opposite sides of the gate electrode and pass through the second insulating layer and the first insulating layer; A third insulating layer is located on the second insulating layer, and the third insulating layer compliantly covers the source electrode and the drain electrode.

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