CN110034171B - High electron mobility transistor - Google Patents
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- CN110034171B CN110034171B CN201810026948.2A CN201810026948A CN110034171B CN 110034171 B CN110034171 B CN 110034171B CN 201810026948 A CN201810026948 A CN 201810026948A CN 110034171 B CN110034171 B CN 110034171B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Abstract
The present invention provides a high electron mobility transistor, comprising: the buffer layer is positioned on the substrate; the critical voltage adjusting layer is positioned on the buffer layer; the channel region is positioned in the buffer layer and is adjacent to the interface of the buffer layer and the critical voltage adjusting layer; an energy band adjusting layer located on the critical voltage adjusting layer; the first enhancement layer is covered on the critical voltage adjusting layer and the energy band adjusting layer in a compliance manner; a gate electrode on the first enhancement layer; and source/drain electrodes respectively positioned on two opposite sides of the gate electrode, penetrating through the critical voltage adjusting layer and the first enhancement layer, and disposed on the buffer layer; wherein the threshold voltage adjusting layer and the first enhancement layer are III-V group semiconductors.
Description
Technical Field
Embodiments of the present invention relate to semiconductor technology, and more particularly, to a high electron mobility transistor.
Background
A High Electron Mobility Transistor (HEMT) has advantages of a High breakdown voltage, a High output voltage, and the like, and thus is widely used in a High power semiconductor device.
Due to Miller Effect, the voltage of the gate is increased by the surge caused by the parasitic capacitance and the parasitic inductance, which is likely to cause abnormal conduction of the device and burn out of the device. Therefore, the high electron mobility transistor needs to raise a threshold voltage (Vt) to reduce the damage of the circuit.
In order to form an enhancement mode (E-mode) high electron mobility transistor, a gate access (recess) method may be used, but the recess gate is prone to cause a problem of difficulty in controlling process uniformity, which further affects uniformity of electrical parameters.
Although conventional high electron mobility transistors are generally satisfactory in many respects, it is desirable to improve the threshold voltage and reduce the on-resistance of the high electron mobility transistor.
Disclosure of Invention
According to an embodiment, the present invention provides a high electron mobility transistor including: the buffer layer is positioned on the substrate; the critical voltage adjusting layer is positioned on the buffer layer; the channel region is positioned in the buffer layer and is adjacent to the interface of the buffer layer and the critical voltage adjusting layer; the energy band adjusting layer is positioned on the critical voltage adjusting layer; the first enhancement layer is covered on the critical voltage adjustment layer and the energy band adjustment layer in a compliance manner; a gate electrode on the first enhancement layer; and source/drain electrodes respectively located at opposite sides of the gate electrode, penetrating through the critical voltage adjustment layer and the first enhancement layer, and disposed on the buffer layer; wherein the threshold voltage adjustment layer and the first enhancement layer are group III-V semiconductors, and wherein the first enhancement layer separates the gate electrode and the energy band adjustment layer.
According to another embodiment, the present invention provides a high electron mobility transistor including: the buffer layer is positioned on a substrate; a critical voltage adjusting layer on the buffer layer; a channel region in the buffer layer, adjacent to an interface between the buffer layer and the threshold voltage adjusting layer; a first enhancement layer on the threshold voltage adjustment layer; a gate electrode on the first enhancement layer; source/drain electrodes respectively located on two opposite sides of the gate electrode, penetrating through the critical voltage adjusting layer and the first enhancement layer, and disposed on the buffer layer; and a doped region in the threshold voltage adjustment layer and the first enhancement layer under the gate electrode; wherein the doped region comprises fluorine (F), and the threshold voltage adjusting layer and the enhancement layer are III-V semiconductors.
The high electron mobility transistor structure has the technical effects that the critical voltage adjusting layer and the enhancement layer are formed above the buffer layer, the intensity of the piezoelectric effect can be adjusted by adjusting the individual thickness and the molar concentration of III-V group elements, the critical voltage of the high electron mobility transistor is accurately controlled and improved, good uniformity is maintained, two-dimensional electron gas is enhanced, and the on-resistance is reduced.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, several embodiments accompanied with figures are described in detail below.
Drawings
The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.
Fig. 1 is a schematic cross-sectional view of a high electron mobility transistor according to some embodiments.
Fig. 2 is a schematic cross-sectional view of a high electron mobility transistor according to some embodiments.
Fig. 3 is a schematic cross-sectional view of a high electron mobility transistor according to still other embodiments.
Reference numerals:
100. 200, 300, 400 to high electron mobility transistors;
102-a substrate;
104-a buffer layer;
106-threshold voltage adjusting layer;
108-channel region;
110-energy band adjusting layer;
112 to a first enhancement layer;
114-gate electrode;
116 source/drain electrodes;
212-a second enhancement layer;
310-doped layer.
Detailed Description
While various embodiments or examples are disclosed below to practice various features of embodiments of the invention, embodiments of specific components and arrangements thereof are described below to illustrate embodiments of the invention. These examples are merely illustrative and should not be construed as limiting the scope of the embodiments of the present invention. For example, references in the specification to a first feature being formed over a second feature include embodiments in which the first feature is in direct contact with the second feature, and embodiments in which there are additional features between the first and second features, i.e., the first and second features are not in direct contact. Moreover, where specific reference numerals or designations are used in various embodiments, these have been repeated among the various embodiments and/or structures in order to provide a clear and concise description of the embodiments as well as a concise description of the various embodiments.
Furthermore, spatially relative terms, such as "under 823030hire", "below", "lower", "above", "upper" and the like, may be used herein to facilitate description of the relationship of element(s) or feature(s) to other element(s) or feature(s) in the drawings and include different orientations of the device in use or operation and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.
As used herein, the term "about", "approximately", "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate amounts, i.e., the meanings of "about", "about" and "about" may be implied without specific recitation of "about", "about" and "about".
Embodiments of the present invention provide a High Electron Mobility Transistor (HEMT), which can effectively control and increase a threshold voltage (threshold voltage) while maintaining good uniformity, increase a two-dimensional electron gas (2 DEG) concentration in a channel region, and reduce on-resistance by adjusting individual thicknesses of two or more layers of group III-V semiconductors and molar concentrations of group III-V elements to change a piezoelectric effect (piezo electric effect).
FIG. 1 illustrates a cross-sectional view of a high electron mobility transistor 100 in accordance with some embodiments of the present invention. As shown in fig. 1, a substrate 102 is provided. The substrate 102 may include Si, siC, or Al 2 O 3 (sapphire) may be a single layer substrate, a multilayer substrate, a gradient substrate, other suitable substrates, or combinations thereof. In some embodiments, the substrate 102 may also include a Semiconductor On Insulator (SOI) substrate, which may include a base plate, a buried oxide layer disposed on the base plate, or a semiconductor layer disposed on the buried oxide layer.
Next, a buffer layer 104 is formed on the substrate 102. In some embodiments, the buffer layer 104 includes a group III-V semiconductor, such as GaN. In some embodiments, the buffer layer 104 is between 0.5um to 10um thick. In some embodiments, the buffer layer 104 may be formed on the substrate 102 using molecular-beam epitaxy (MBE), metal Organic Chemical Vapor Deposition (MOCVD), chemical Vapor Deposition (CVD), hydride Vapor Phase Epitaxy (HVPE), other suitable methods, or a combination thereof.
Next, a threshold voltage adjustment layer (threshold voltage adjustment layer) 106 is formed on the buffer layer 104, and in some embodiments, the threshold voltage adjustment layer 106 comprises a III-V semiconductor, such as Al x Ga 1-x N, wherein 0<x<1. In some embodiments, the threshold voltage adjustment layer 106 has a thickness of 1nm to 5nm and a molar concentration of Al of 0.05M to 0.4M. In some embodiments, the threshold voltage adjustment layer 106 may be formed on the buffer layer 104 by molecular-beam epitaxy (MBE), metal Organic Chemical Vapor Deposition (MOCVD), chemical Vapor Deposition (CVD), hydride Vapor Phase Epitaxy (HVPE), other suitable methods, or a combination thereof.
Due to the different band gap of the buffer layer 104 and the threshold voltage adjustment layer 106, a heterojunction (heterojunction) is formed at the interface of the buffer layer 104 and the threshold voltage adjustment layer 106. The energy band at the heterojunction bends, and a quantum well (quantum well) is formed deep in the bending of the conduction band (conduction band), and electrons generated by the piezoelectric effect (piezo electric) are confined in the quantum well, so that a two-dimensional electron gas (2 DEG) is formed at the interface between the buffer layer 104 and the threshold voltage adjustment layer 106, and thus an on-current is formed. As shown in FIG. 1, a channel region 108 is formed at the interface between the buffer layer 104 and the threshold voltage adjusting layer 106, and the channel region 108 is the place where the two-dimensional electron gas forms the conducting current. In some embodiments, channel region 108 is between 0.1um to 5um thick.
The degree of piezo-electric effect (piezo-electric) can be varied by adjusting the thickness of the threshold voltage adjusting layer 106 and the molar concentration of the III-V element therein, and in the case of AlGaN, the more the thickness of the threshold voltage adjusting layer 106 is thinner and the molar concentration of Al is smaller, the more the piezo-electric effect is slight, and the less the two-dimensional electron gas is generated in the channel region 108.
To avoid the spike-induced device burn-out in the circuit caused by the Miller effect, the threshold voltage of the hemt needs to be increased. Taking AlGaN as an example, by reducing the thickness of the threshold voltage adjustment layer 106 and the molar concentration of Al element, the on-current can be reduced, and the threshold voltage can be increased.
Next, a band adjustment layer (band adjustment layer) 110 is formed on the threshold voltage adjustment layer 106. The band adjusting layer 110 is a P-type doped III-V semiconductor comprising P-type doped GaN, alGaN, alN, gaAs, alGaAs, inP, inAlAs, or InGaAs, and has a P-type doping concentration of 1e17/cm 3 To 1e20/cm 3 In between. The energy band adjusting layer 110 has a thickness of 50nm to 200 nm. The band adjusting layer 110 may be formed by depositing a P-type doped iii-v semiconductor by molecular-beam epitaxy (MBE), metal Organic Chemical Vapor Deposition (MOCVD), chemical Vapor Deposition (CVD), or hydride vapor epitaxy (HVPE), and patterning the P-type doped iii-v semiconductor. In some embodiments, the band adjustment layer 110 is located below a subsequently formed gate electrode.
Since the band adjustment layer 110 is a P-type doped iii-v semiconductor, the P-type doping increases the band, so that the conduction band at the interface between the buffer layer 104 and the threshold voltage adjustment layer 106 is higher than the fermi level (fermi level), and no two-dimensional electron gas is generated in the channel region 108, thereby resulting in no conduction current.
Since the band adjustment layer 110 pulls the high band and the high electron mobility transistor 100 is in an off state when no gate voltage is applied, the high electron mobility transistor 100 is an enhancement mode (E-mode) high electron mobility transistor.
Compared with depletion mode (D-mode) high electron mobility transistors, enhancement mode (E-mode) high electron mobility transistors are safer, have lower standby power dissipation, and reduce circuit complexity and manufacturing cost because they do not need to supply negative bias. In this embodiment, the problem of poor uniformity due to the recessed gate can be avoided since an enhancement mode (E-mode) high electron mobility transistor can be formed without the need to recess the gate. In conjunction with the threshold voltage adjustment layer 106, the threshold voltage of an enhancement mode (E-mode) high electron mobility transistor can be raised while maintaining good uniformity. In some embodiments, the threshold voltage of the high electron mobility transistor may be greater than 2V.
Next, a first enhancement layer (enhancement layer) 112 is formed, and in some embodiments, the first enhancement layer 112 includes a III-V semiconductor, such as Al x Ga 1-x N, wherein 0<x<1. In some embodiments, the first enhancement layer 112 is between 15nm and 25nm thick and the Al molarity is between 0.05M and 0.4M. In some embodiments, the first enhancement layer 112 may be conformally (conformally) coated over the threshold voltage adjustment layer 106 and the band adjustment layer 110 using molecular-beam epitaxy (MBE), metal Organic Chemical Vapor Deposition (MOCVD), chemical Vapor Deposition (CVD), hydride Vapor Phase Epitaxy (HVPE), other suitable methods, or a combination thereof.
The degree of piezoelectric effect (piezoconductivity) can be varied by adjusting the thickness of the first enhancement layer 112 and the molar concentration of the group III-V element therein. Taking AlGaN as an example, the thicker the thickness of the first enhancement layer 112 and the larger the molar concentration of Al, the more significant the piezoelectric effect and the more two-dimensional electron gas is generated in the channel region 108. By increasing the thickness of the first enhancement layer 112 and the Al molar concentration, the on-resistance can be reduced.
In the embodiment shown in fig. 1, since the threshold adjustment layer 106 mainly increases the threshold voltage and the first enhancement layer 112 mainly decreases the on-resistance, in the case of AlGaN, the Al molar concentration of the threshold adjustment layer 106 is smaller than that of the first enhancement layer 112, and the thickness of the threshold adjustment layer 106 is smaller than that of the first enhancement layer 112.
Next, a gate electrode 114 is formed on the first enhancement layer 112, and in some embodiments, the gate electrode 114 may include a metal material, polysilicon, a metal silicide, other suitable conductive materials, or a combination thereof. In some embodiments, the gate electrode 114 is formed by forming an electrode material on the first enhancement layer 112 by electroplating, sputtering, resistive heating evaporation, electron beam evaporation, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), other suitable methods, or a combination thereof, and then patterning the electrode material by photolithography and etching processes.
Then, source/drain electrodes 116 are formed on two opposite sides of the gate electrode 114, respectively, through the threshold voltage adjustment layer 106 and the first enhancement layer 112, and disposed on the buffer layer 108. Thus, the resistance of the Ohmic contact (Ohmic contact) of the source/drain electrode can be reduced. In some embodiments, the source/drain electrodes 116 may each comprise Ti, al, W, au, pd, other suitable metallic materials, alloys thereof, or combinations thereof. In some embodiments, the holes are etched by an etching process, and an electrode material is formed in the holes by an electroplating method, a sputtering method, a resistance heating evaporation method, an electron beam evaporation method, a Physical Vapor Deposition (PVD) method, a Chemical Vapor Deposition (CVD) method, an Atomic Layer Deposition (ALD) method, other suitable methods, or a combination thereof, and then patterned by a photolithography and etching process to form the source/drain electrodes 116.
It is noted that, in the foregoing description, the gate electrode 114 is formed first, and then the source/drain electrode 116 is formed, however, the forming sequence is not limited in this embodiment, and the source/drain electrode 116 may be formed first, and then the gate electrode 114 may be formed.
In the embodiment shown in fig. 1, in addition to the threshold voltage adjustment layer 106 and the first enhancement layer 112, the band adjustment layer 110 is disposed under the gate electrode 114 to form an enhancement mode (E-mode) high electron mobility transistor. The threshold voltage adjusting layer 106 and the first enhancement layer 112 are used together to adjust the strength of the overall piezoelectric effect, precisely control and improve the threshold voltage, maintain good uniformity, and enhance the two-dimensional electron gas and reduce the on-resistance when the enhancement mode (E-mode) high electron mobility transistor 100 is turned on.
As shown in fig. 1, in some embodiments, taking AlGaN as an example, the thickness and Al molar concentration of each of the threshold voltage adjustment layer 106 and the first enhancement layer 112 can be adjusted, so that the high electron mobility transistor 100 is a depletion (D-mode) high electron mobility transistor when the band adjustment layer 110 is not formed, and is an enhancement (E-mode) high electron mobility transistor when the band adjustment layer 110 is formed. In some embodiments, for example, the AlGaN, the threshold voltage adjustment layer 106 has a thickness of 1nm to 5nm, a molar concentration of al of 0.05M to 0.4M, the first enhancement layer 112 has a thickness of 15nm to 25nm, and a molar concentration of al of 0.05M to 0.4M. Thus, the same adjustment of the threshold voltage adjustment layer 106 and the first enhancement layer 112 can be used to form a composite high electron mobility transistor having both depletion and enhancement high electron mobility transistors, thereby saving the production cost and time.
FIG. 2 illustrates a cross-sectional view of a high electron mobility transistor 200 in accordance with another embodiment of the present invention. Wherein, the same or similar processes or elements as those in the previous embodiments will be followed by the same reference numerals, and the detailed description thereof will not be repeated. The difference from the previous embodiment is that the second reinforcement layer 212 is formed thereon after the first reinforcement layer 112 is formed. In some embodiments, the second enhancement layer 212 includes a group III-V semiconductor, such as Al x Ga 1-x N, wherein 0<x<1. In some embodiments, the second enhancement layer 212 is between 1nm and 10nm thick and the Al molarity is between 0.05M and 0.4M. In some embodiments, molecular-beam epitaxy (MBE), metal Organic Chemical Vapor Deposition (MOCVD), chemical vapor deposition (chemical vapor deposition) may be usedposition, CVD), hydride Vapor Phase Epitaxy (HVPE), other suitable methods, or combinations thereof conformally cover the second enhancement layer 212 over the first enhancement layer 112.
It is noted that although FIG. 2 only illustrates the second enhancement layer 212, the present invention is not limited thereto, and depending on the product requirements, a plurality of enhancement layers, each including a group III-V semiconductor, such as Al, may be formed on the first enhancement layer 112 x Ga 1-x N, wherein 0<x<1。
In the embodiment shown in fig. 2, each of the multiple enhancement layers may have the same or different thickness and Al molar concentration, taking AlGaN as an example. Therefore, the multiple enhancement layers can increase the degree of freedom of the process, and the overall piezoelectric effect and the energy band structure are changed by adjusting the combination of different thicknesses and Al molar concentrations of the multiple enhancement layers. The threshold voltage can be effectively raised and accurately controlled, and when the enhanced high electron mobility transistor 200 is turned on, the two-dimensional electron gas is enhanced, and the on-resistance is reduced.
FIG. 3 illustrates a cross-sectional view of a high electron mobility transistor 300 in accordance with still other embodiments of the present invention. Wherein the same or similar processes or elements as those in the previous embodiments will be followed by the same reference numerals, and the detailed description thereof will not be repeated. The difference with the previous embodiment is that the band adjustment layer 110 is not disposed under the gate electrode 114, but a doped layer 310 is disposed in the threshold voltage adjustment layer 106 and the first enhancement layer 112. In some embodiments, doped layer 310 may be formed by an ion implantation step. For example, the F implant may be performed in the Vt adjustment layer 106 and the first enhancement layer 112 under predetermined regions of the gate electrode 114 using a patterned mask (not shown) prior to forming the gate electrode 114 2 、CF 4 Or other fluorine-based ions to form doped layer 310, doped layer 310 having a doping concentration of 1e18/cm 3 To 1e20/cm 3 In the meantime.
As shown in fig. 3, the doping layer 310 disposed in the threshold voltage adjusting layer 106 and the first enhancement layer 112 can improve the band structure of the heterojunction (heterojunction) between the buffer layer 104 and the threshold voltage adjusting layer 106, thereby reducing the two-dimensional electron gas in the channel region 108. In some embodiments, the high electron mobility transistor 300 is in an off state when no gate voltage is applied, and thus the high electron mobility transistor 300 is an enhancement mode (E-mode) high electron mobility transistor.
In the embodiment shown in fig. 3, since the threshold voltage adjusting layer 106 mainly increases the threshold voltage and the first enhancement layer 112 mainly decreases the on-resistance, taking AlGaN as an example, the Al molar concentration of the threshold voltage adjusting layer 106 is smaller than the Al molar concentration of the first enhancement layer 112, and the thickness of the threshold voltage adjusting layer 106 is smaller than the thickness of the first enhancement layer 112. In some embodiments, the threshold voltage adjustment layer 106 has a thickness of between 1nm and 5nm and a molar concentration of Al of between 0.05M and 0.4M. In some embodiments, the first enhancement layer 112 has a thickness of between 15nm and 25nm and a molar concentration of al of between 0.05M and 0.4M.
In the embodiment shown in fig. 3, in addition to the threshold voltage adjustment layer 106 and the first enhancement layer 112, doped layers 310 are disposed in the threshold voltage adjustment layer 106 and the first enhancement layer 112 under the gate electrode 114 to form an enhancement mode (E-mode) high electron mobility transistor. The threshold voltage adjustment layer 106 and the first enhancement layer 112 are used together to adjust the strength of the piezoelectric effect, precisely control and increase the threshold voltage, and enhance the two-dimensional electron gas and reduce the on-resistance when the enhancement mode (E-mode) high electron mobility transistor 300 is turned on.
In summary, embodiments of the present invention provide a High Electron Mobility Transistor (HEMT) structure, in which a threshold voltage adjusting layer and an enhancement layer are formed above a buffer layer, and the respective thicknesses and molar concentrations of III-V elements are adjusted to adjust the intensity of a piezoelectric effect, precisely control and improve the threshold voltage of the HEMT, maintain good uniformity, enhance two-dimensional electron gas, and reduce on-resistance.
The foregoing outlines features of many embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art may readily devise many other varied processes and structures that are designed to achieve the same purposes and/or achieve the same advantages of the embodiments of the invention. Those skilled in the art should also realize that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the invention and that such equivalents are not to be construed as exceeding the spirit and scope of the embodiments of the invention.
Claims (11)
1. A high electron mobility transistor, comprising:
a buffer layer on a substrate;
a critical voltage adjusting layer on the buffer layer;
a channel region in the buffer layer adjacent to an interface of the buffer layer and the threshold voltage adjustment layer;
an energy band adjusting layer located on the critical voltage adjusting layer;
a first enhancement layer conformally covering the threshold voltage adjustment layer and the energy band adjustment layer;
a gate electrode on the first enhancement layer; and
a source/drain electrode respectively located at two opposite sides of the gate electrode, penetrating through the critical voltage adjusting layer and the first enhancement layer, and disposed on the buffer layer;
wherein the threshold voltage adjustment layer and the first enhancement layer are group III-V semiconductors, and wherein the first enhancement layer separates the gate electrode and the band adjustment layer.
2. The hemt of claim 1, wherein said threshold voltage adjusting layer and said first enhancement layer each comprise Al x Ga 1-x N, wherein 0<x<1。
3. The hemt of claim 2, wherein said threshold voltage adjusting layer has a molar concentration of Al that is less than the molar concentration of Al of said first enhancement layer.
4. The HTT of claim 2, wherein the molar concentration of Al in the Vt adjusting layer is in the range of 0.05M to 0.4M, and the molar concentration of Al in the first enhancement layer is in the range of 0.05M to 0.4M.
5. The hemt of claim 1, wherein said threshold voltage adjusting layer has a thickness less than that of said first enhancement layer.
6. The hemt of claim 1, wherein said threshold voltage adjusting layer has a thickness of from 1nm to 5nm and said first enhancement layer has a thickness of from 15nm to 25nm.
7. The hemt of claim 1, further comprising:
and the second enhancement layer is covered on the first enhancement layer in a compliance way.
8. The HTT of claim 7, wherein said second enhancement layer is a group III-V semiconductor.
9. The hemt of claim 1, wherein said band-adjusting layer is a P-type doped iii-v semiconductor.
10. The high electron mobility transistor of claim 1, wherein the band adjustment layer comprises P-doped GaN, alGaN, alN, gaAs, alGaAs, inP, inAlAs, or InGaAs.
11. The hemt of claim 1, wherein said band-adjusting layer has a P-type doping concentration of between 1e17/cm 3 To 1e20/cm 3 In the meantime.
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| CN110034171B true CN110034171B (en) | 2022-11-22 |
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