TWI732593B - Semiconductor structure and high-electron mobility transistor device having the same - Google Patents
Semiconductor structure and high-electron mobility transistor device having the same Download PDFInfo
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本發明係有關於一種半導體結構,且特別係有關於一種可減少晶圓翹曲的半導體結構及應用此半導體結構的高電子遷移率電晶體裝置,可明顯改善裝置之電性。The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure capable of reducing wafer warpage and a high electron mobility transistor device using the semiconductor structure, which can significantly improve the electrical properties of the device.
近年來,半導體裝置在電腦、消費電子等領域中發展快速。目前,半導體裝置技術在金屬氧化物半導體場效電晶體的產品市場中已被廣泛接受,具有很高的市場佔有率。半導體裝置被用於各種電子應用中,例如高功率裝置、個人電腦、手機、數位相機及其他電子裝置。這些半導體裝置一般藉由在半導體基底上沉積絕緣層或介電層、導電層材料和半導體層材料,隨後藉由使用微影(photolithography)製程將各種材料層圖案化以製造而成。因此,在半導體基底上形成電路裝置和組件。In recent years, semiconductor devices have developed rapidly in fields such as computers and consumer electronics. At present, semiconductor device technology has been widely accepted in the metal oxide semiconductor field effect transistor product market and has a high market share. Semiconductor devices are used in various electronic applications, such as high-power devices, personal computers, mobile phones, digital cameras, and other electronic devices. These semiconductor devices are generally manufactured by depositing insulating or dielectric layers, conductive layer materials, and semiconductor layer materials on a semiconductor substrate, and then patterning various material layers using a photolithography process. Therefore, circuit devices and components are formed on the semiconductor substrate.
在這些裝置中,高電子遷移率電晶體(high-electron mobility transistors,HEMTs)裝置具有例如高輸出功率和高崩潰電壓的優勢,因此它們被廣泛地使用於高功率的應用中。雖然現存的半導體結構及其形成方法可以應付它們原先預定的用途,但目前它們在結構和製法各個技術方面上仍有需要克服的問題。例如,高電子遷移率電晶體裝置中係在基板上磊晶成長而形成多個磊晶材料層,但磊晶材料層在異質接面(上下層材料的晶格常數不同)上的晶格不匹配(lattice mismatch)以及與基板之間熱不匹配(thermal mismatch)會使材料層內部產生應力,且此應力隨著磊晶成長的厚度增加而累積,當磊晶材料層成長的厚度超過臨界厚度,應力開始持續釋放,甚至使基板破裂(cracks)。Among these devices, high-electron mobility transistors (HEMTs) devices have advantages such as high output power and high breakdown voltage, so they are widely used in high-power applications. Although the existing semiconductor structures and their forming methods can cope with their original intended use, they still have problems that need to be overcome in various technical aspects of their structures and manufacturing methods. For example, in a high electron mobility transistor device, multiple epitaxial material layers are formed by epitaxial growth on the substrate, but the epitaxial material layer has a different crystal lattice on the heterojunction (the upper and lower materials have different lattice constants). Lattice mismatch and thermal mismatch with the substrate will cause stress in the material layer, and this stress will accumulate as the thickness of the epitaxial growth increases, when the thickness of the epitaxial material layer exceeds the critical thickness , The stress began to release continuously, and even cracked the substrate.
因此,雖然現有的半導體裝置可以應付它們原先預定的用途,但目前它們在結構上仍有需要克服的問題。如何改良半導體裝置,以有效避免上述例如基板破裂的發生,改善半導體裝置的電性,對於相關業者而言實為一重要議題。Therefore, although existing semiconductor devices can cope with their original intended use, they still have structural problems that need to be overcome at present. How to improve the semiconductor device to effectively avoid the occurrence of the above-mentioned substrate cracks and improve the electrical properties of the semiconductor device is indeed an important issue for the related industry.
本發明的一些實施例係揭示一種半導體結構,包括一基板、位於基板上的一晶種層、位於晶種層的磊晶堆疊。其中磊晶堆疊包括第一超晶格部和位於第一超晶格部上的第二超晶格部。第一超晶格部包括重複堆疊M1次的複數個第一單元,此些第一單元分別包括第一子層和位於第一子層上的第二子層,其中第一子層為厚度b1奈米的Al y1Ga 1-y1N,第二子層為厚度a1奈米的Al x1Ga 1-x1N,其中y1小於x1。第二超晶格部包括重複堆疊M2次的複數個第二單元,此些第二單元各包括第三子層和位於第三子層上的第四子層,其中第三子層為厚度b2奈米的Al y2Ga 1-y2N,第四子層為厚度a2奈米的Al x2Ga 1-x2N,其中y2小於x2。在一些實施例中,M1和M2為正整數,x1、y1、y2分別係大於0小於1,x2大於0小於等於1,且x1小於x2,或x1等於x2且y1小於y2。 Some embodiments of the present invention disclose a semiconductor structure including a substrate, a seed layer on the substrate, and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice portion and a second superlattice portion located on the first superlattice portion. The first superlattice portion includes a plurality of first units repeatedly stacked M1 times, and these first units respectively include a first sublayer and a second sublayer located on the first sublayer, wherein the first sublayer has a thickness b1 Nano Al y1 Ga 1-y1 N, the second sub-layer is Al x1 Ga 1-x1 N with a thickness of a1 nanometers, where y1 is smaller than x1. The second superlattice portion includes a plurality of second units repeatedly stacked M2 times, each of these second units includes a third sublayer and a fourth sublayer located on the third sublayer, wherein the third sublayer has a thickness b2 Nano Al y2 Ga 1-y2 N, the fourth sub-layer is Al x2 Ga 1-x2 N with a thickness of a2 nanometers, where y2 is smaller than x2. In some embodiments, M1 and M2 are positive integers, x1, y1, and y2 are respectively greater than 0 and less than 1, x2 is greater than 0 and less than or equal to 1, and x1 is less than x2, or x1 is equal to x2 and y1 is less than y2.
一些實施例中,基材包括一陶瓷材料,且絕緣層為單一或多層的絕緣材料層包覆住基材的所有表面。In some embodiments, the substrate includes a ceramic material, and the insulating layer is a single or multiple layers of insulating material covering all surfaces of the substrate.
一些實施例中,y1小於y2。In some embodiments, y1 is less than y2.
一些實施例中,a1小於a2,b1大於b2。In some embodiments, a1 is smaller than a2, and b1 is larger than b2.
一些實施例中,y2大於y1,b2大於b1。一些實施例中,a1大於等於a2。In some embodiments, y2 is greater than y1, and b2 is greater than b1. In some embodiments, a1 is greater than or equal to a2.
一些實施例中,M1小於M2。In some embodiments, M1 is smaller than M2.
一些實施例中,第一超晶格部的總厚度小於該第二超晶格部的總厚度。In some embodiments, the total thickness of the first superlattice portion is less than the total thickness of the second superlattice portion.
一些實施例中,第一超晶格部更包含具有第一摻雜濃度的第一摻質,該第二超晶格部更包含具有第二摻雜濃度的第二摻質,其中第二摻雜濃度大於第一摻雜濃度。In some embodiments, the first superlattice portion further includes a first dopant having a first doping concentration, and the second superlattice portion further includes a second dopant having a second doping concentration, wherein the second dopant The impurity concentration is greater than the first doping concentration.
一些實施例中,磊晶堆疊更包括一第三超晶格部(third superlattice part)位於第二超晶格部上,且第三超晶格部包括重複堆疊M3次的第三單元(third unit),第三單元包括第五子層和位於第五子層上的第六子層,其中第五子層為厚度b3奈米的Al y3Ga 1-y3N,第六子層為厚度a3奈米的Al x3Ga 1-x3N,其中y3小於x3,M3為正整數, y3係大於0小於1,x3大於0小於等於1,且x2小於x3,或x2等於x3且y2小於y3。 In some embodiments, the epitaxial stack further includes a third superlattice part located on the second superlattice part, and the third superlattice part includes a third unit repeatedly stacked M3 times. ), the third unit includes a fifth sub-layer and a sixth sub-layer located on the fifth sub-layer, wherein the fifth sub-layer is Al y3 Ga 1-y3 N with a thickness of b3 nanometers, and the sixth sub-layer has a thickness of a3 nanometers. Rice Al x3 Ga 1-x3 N, where y3 is less than x3, M3 is a positive integer, y3 is greater than 0 and less than 1, x3 is greater than 0 and less than 1, and x2 is less than x3, or x2 is equal to x3 and y2 is less than y3.
一些實施例中,a2小於a3,b2大於b3。In some embodiments, a2 is smaller than a3, and b2 is larger than b3.
一些實施例中,y3大於y2,y2大於y1(y3>y2>y1),且b3大於b2,b2大於b1(b3>b2>b1)。再者,於此些實施例中,a1大於等於a2,a2大於等於a3(a1≥a2≥a3)。In some embodiments, y3 is greater than y2, y2 is greater than y1 (y3>y2>y1), and b3 is greater than b2, and b2 is greater than b1 (b3>b2>b1). Furthermore, in these embodiments, a1 is greater than or equal to a2, and a2 is greater than or equal to a3 (a1≥a2≥a3).
一些實施例中,第一超晶格部的總厚度(S1)小於第二超晶格部的總厚度(S2),第二超晶格部的總厚度(S2)小於第三超晶格部的總厚度(S3)。In some embodiments, the total thickness (S1) of the first superlattice portion is less than the total thickness (S2) of the second superlattice portion, and the total thickness (S2) of the second superlattice portion is less than that of the third superlattice portion The total thickness (S3).
根據本發明的一些實施例,係揭示一種高電子遷移率電晶體(high-electron mobility transistor,HEMT)裝置,包括如前述之半導體結構;一第一絕緣層,位於該磊晶堆疊上;一閘極電極,位於該第一絕緣層上;一第二絕緣層,位於該第一絕緣層上,且該第二絕緣層順應性地覆蓋閘極電極;源極電極和汲極電極,分別位於閘極電極112的相對兩側,且穿過該第二絕緣層和該第一絕緣層;一第三絕緣層,位於該第二絕緣層上,且該第三絕緣層順應性地覆蓋源極電極和汲極電極。According to some embodiments of the present invention, a high-electron mobility transistor (HEMT) device is disclosed, including the aforementioned semiconductor structure; a first insulating layer on the epitaxial stack; and a gate The electrode electrode is located on the first insulating layer; a second insulating layer is located on the first insulating layer, and the second insulating layer compliantly covers the gate electrode; the source electrode and the drain electrode are respectively located on the gate Opposite sides of the
根據本發明的一些實施例,係揭示一種半導體結構的形成方法,包括提供一基板;形成一晶種層於該基板上;以及成長一磊晶堆疊於晶種層之上方,磊晶堆疊包括:第一超晶格部和位於第一超晶格部上的第二超晶格部。第一超晶格部包括重複堆疊M1次的複數個第一單元,此些第一單元分別包括第一子層和位於第一子層上的第二子層,其中第一子層為厚度b1奈米的Al y1Ga 1-y1N,第二子層為厚度a1奈米的Al x1Ga 1-x1N,其中y1小於x1。第二超晶格部包括重複堆疊M2次的複數個第二單元,此些第二單元各包括第三子層和位於第三子層上的第四子層,其中第三子層為厚度b2奈米的Al y2Ga 1-y2N,第四子層為厚度a2奈米的Al x2Ga 1-x2N,其中y2小於x2。在一些實施例中,M1和M2為正整數,x1、y1、y2分別係大於0小於1,x2大於0小於等於1,且x1小於x2,或x1等於x2且y1小於y2。 According to some embodiments of the present invention, a method for forming a semiconductor structure is disclosed, including providing a substrate; forming a seed layer on the substrate; and growing an epitaxial stack above the seed layer, the epitaxial stack including: A first superlattice part and a second superlattice part located on the first superlattice part. The first superlattice portion includes a plurality of first units repeatedly stacked M1 times, and these first units respectively include a first sublayer and a second sublayer located on the first sublayer, wherein the first sublayer has a thickness b1 Nano Al y1 Ga 1-y1 N, the second sub-layer is Al x1 Ga 1-x1 N with a thickness of a1 nanometers, where y1 is smaller than x1. The second superlattice portion includes a plurality of second units repeatedly stacked M2 times, each of these second units includes a third sublayer and a fourth sublayer located on the third sublayer, wherein the third sublayer has a thickness b2 Nano Al y2 Ga 1-y2 N, the fourth sub-layer is Al x2 Ga 1-x2 N with a thickness of a2 nanometers, where y2 is smaller than x2. In some embodiments, M1 and M2 are positive integers, x1, y1, and y2 are respectively greater than 0 and less than 1, x2 is greater than 0 and less than or equal to 1, and x1 is less than x2, or x1 is equal to x2 and y1 is less than y2.
根據本發明的一些實施例,在成長磊晶堆疊後,更冷卻(cooling)包括基板、晶種層和磊晶堆疊之結構,冷卻後,構成的半導體結構之一頂面的中心和邊緣的一垂直高度差值係在-10µm至+10µm範圍之間。According to some embodiments of the present invention, after the epitaxial stack is grown, the structure including the substrate, the seed layer, and the epitaxial stack is further cooled. After cooling, one of the center and edge of the top surface of one of the semiconductor structures is formed. The vertical height difference is in the range of -10µm to +10µm.
以下針對本揭露之半導體結構及其形成方法作詳細說明。應了解的是,以下之敘述提供了不同的實施例或例子,用於實施本揭露之不同樣態。以下所述特定的元件及排列方式僅為簡單描述本揭露。當然,這些僅用以舉例而非用以限定本揭露之範圍。再者,敘述中若提及第一元件形成在第二元件之上,可能包含第一和第二元件直接接觸的實施例,也可能包含額外的元件形成在第一和第二元件之間,使得它們不直接接觸的實施例。此外,本發明實施例可能在不同的範例中重複參考數字及/或字母。如此重複是為了簡明和清楚,而非用以表示所討論的不同實施例及/或形態之間的關係。The following is a detailed description of the semiconductor structure and the method of forming the disclosed semiconductor structure. It should be understood that the following description provides different embodiments or examples for implementing different aspects of the present disclosure. The specific elements and arrangements described below are only a brief description of the present disclosure. Of course, these are merely examples and not to limit the scope of the disclosure. Furthermore, if it is mentioned in the description that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. The embodiment so that they do not directly touch. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, and is not used to indicate the relationship between the different embodiments and/or forms discussed.
再者,在以下敘述中可使用空間上相關措辭,例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」和其他類似的用語,以簡化一元件或部件與其他元件或其他部件之間如圖所示之關係的陳述。此空間相關措辭除了包含圖式所描繪之方向,還包含裝置在使用或操作中的不同方位。裝置可以朝其他方向定位(旋轉90度或在其他方向),且在此使用的空間相關描述可依此相應地解讀。Furthermore, spatially relevant terms can be used in the following descriptions, such as "below", "below", "below", "above", "above" and other similar The terms are used to simplify the statement of the relationship between one element or component and other elements or other components as shown in the figure. This space-related wording includes not only the directions depicted in the diagrams, but also the different orientations of the device in use or operation. The device can be positioned in other directions (rotated by 90 degrees or in other directions), and the spatial description used here can be interpreted accordingly.
以下描述實施例的一些變化。在不同圖式和說明的實施例中,相似的元件符號被用來標明相似的元件。可以理解的是,在方法的前、中、後可以提供額外的步驟,且一些敘述的步驟可為了該方法的其他實施例被取代或刪除。Some changes of the embodiment are described below. In the different drawings and illustrated embodiments, similar component symbols are used to designate similar components. It can be understood that additional steps may be provided before, during, and after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.
在此,「約」、「大約」之用語通常表示在一給定值或範圍的20%之內,較佳是10%之內,且更佳是5%之內。在此給定的數量為大約的數量,意即在沒有特定說明的情況下,仍可隱含「約」、「大約」之含義。Here, the terms "about" and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, which means that the meaning of "about" and "approximately" can still be implied in the absence of specific instructions.
本揭露內容的實施例提供了半導體結構及其形成方法。一些實施例中,半導體結構的基板上方具有一磊晶堆疊(epitaxial stack),磊晶堆疊包含至少兩個超晶格部(superlattice parts)。一些實施例中,各個超晶格部包含重複堆疊的複數個單元,各單元包含兩個子層(sub-layer),且此些子層交替地堆疊於基板的上方。本揭露提出兩個超晶格部所包含的子層中具有氮化鋁以及/或氮化鋁鎵,較接近基板的超晶格部其中一子層的鋁在氮化鋁鎵中的莫耳分率係小於較遠離基板的超晶格部其中一子層的鋁在氮化鋁或氮化鋁鎵中的莫耳分率。例如,根據本揭露之一些實施例,較接近基板的第一超晶格部之在氮化鋁鎵中鋁的莫耳分率更高的子層(如下實施例中所述之第二子層)例如具有鋁的莫耳分率x1,較遠離基板的第二超晶格部中之在氮化鋁鎵中鋁的莫耳分率更高的子層(如下實施例中所述之第四子層)例如具有鋁的莫耳分率x2,其中x1係小於x2。The embodiments of the present disclosure provide a semiconductor structure and a method of forming the same. In some embodiments, there is an epitaxial stack above the substrate of the semiconductor structure, and the epitaxial stack includes at least two superlattice parts. In some embodiments, each superlattice portion includes a plurality of units stacked repeatedly, each unit includes two sub-layers, and these sub-layers are alternately stacked on the substrate. This disclosure proposes that the sub-layers included in the two superlattice portions have aluminum nitride and/or aluminum gallium nitride, and the aluminum in one of the sub-layers of the superlattice portion closer to the substrate has a molar ratio of aluminum in the aluminum gallium nitride. The fraction is smaller than the molar fraction of aluminum in one of the sub-layers of the superlattice part farther from the substrate in aluminum nitride or aluminum gallium nitride. For example, according to some embodiments of the present disclosure, a sublayer with a higher molar fraction of aluminum in aluminum gallium nitride in the first superlattice portion closer to the substrate (the second sublayer described in the following embodiments ) For example, a sublayer with a molar fraction of aluminum x1, and a sublayer with a higher molar fraction of aluminum in aluminum gallium nitride in the second superlattice part farther from the substrate (the fourth as described in the following embodiment The sublayer) has, for example, a molar fraction x2 of aluminum, where x1 is smaller than x2.
根據本揭露之實施例,可以大幅降低晶圓(或稱半導體結構)的翹曲度,並可避免晶圓破片或有裂縫(cracks)產生,進而提升在晶圓上所製作的包含半導體結構之元件(例如電晶體)的電性表現,明顯改善整面晶圓上製得元件之間的電性均勻度,提高產品良率。在以下的一些實施例中,係以高電子遷移率電晶體(high-electron mobility transistor,HEMT)裝置作為一種半導體結構的示例說明,但並非以此為限,本揭露的一些實施例亦可用於其他類型的半導體裝置。According to the embodiments of the present disclosure, the warpage of the wafer (or semiconductor structure) can be greatly reduced, and the generation of wafer fragments or cracks can be avoided, thereby improving the quality of the semiconductor structure fabricated on the wafer. The electrical performance of components (such as transistors) can significantly improve the electrical uniformity between the components manufactured on the entire wafer and increase the product yield. In the following embodiments, a high-electron mobility transistor (HEMT) device is taken as an example of a semiconductor structure, but it is not limited to this. Some embodiments of the present disclosure can also be used Other types of semiconductor devices.
第1A-1E圖是根據本揭露的一些實施例之形成半導體結構的製程各個中間階段的剖面示意圖。參照第1A圖,提供基板102。在一實施例中,基板102,舉例而言,可以為絕緣層上覆矽(SOI)。根據一些實施例,基板102包含一基材102
C和密封(encapsulate)基材102
C的一絕緣層102
M。在一些實施例中,基材102
C包含陶瓷材料。陶瓷材料包含金屬無機材料。在一些實施例,基材102
C可以是包含碳化矽、氮化鋁(AlN)、藍寶石或其他適合的材料。上述藍寶石基材為氧化鋁。在一些實施例中,絕緣層102
M例如為單一或多層的絕緣材料層包覆住基材102
C的所有表面(包含上下表面和所有側面)。絕緣材料層例如是氧化物、氮化物、氮氧化物、或其他合適的絕緣材料。在一些其他實施例中,包覆住基材102
C的四周的絕緣層102
M除了多層的絕緣材料層,還可包含其他合適的材料層,如半導體層。一些實施例中,半導體層例如是多晶矽層,設置於該些絕緣材料層之間。為簡化圖式,第1A-1E圖中僅繪示單層的絕緣材料層102
M,以利清楚說明半導體結構之形成方法。
FIGS. 1A-1E are schematic cross-sectional views of various intermediate stages of the process of forming a semiconductor structure according to some embodiments of the present disclosure. Referring to Figure 1A, a
接著,再參照第1A圖,在基板102上方形成晶種層104。一些實施例中,晶種層104可由矽(Si)、氮化鋁(AlN)、或其他合適之材料所形成。再者,晶種層104可包含一或多層合適的材料層。例如,晶種層104可包含在基板102上低溫成長的一氮化鋁層以及高溫成長的另一氮化鋁層。一些實施例中,低溫成長的氮化鋁層具有約1nm的厚度,接著高溫成長的另一氮化鋁層具有約200nm的厚度。在此示例的相關圖式中,僅繪示單層的晶種層104,以利清楚說明半導體結構之形成方法。Next, referring to FIG. 1A again, a
一些實施例中,晶種層104的形成方法可包含選擇性磊晶成長(selective area growth, SAG)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、分子束磊晶製程(molecular-beam epitaxy, MBE)、沉積經摻雜的非晶半導體(例如,Si)之後固相磊晶再結晶(solid-phase epitaxial recrystallization, SPER)步驟、藉由直接轉貼晶種的方式、或其他合適的製程。化學氣相沉積製程例如是氣相磊晶(vapor-phase epitaxy, VPE)製程、低壓化學氣相沉積(low pressure chemical vapor deposition, LPCVD)製程、超高真空化學氣相沉積(ultra-high vacuum chemical vapor deposition, UHV-CVD)製程、或其他合適的製程。In some embodiments, the method for forming the
之後,在晶種層104上方形成一磊晶疊層(epitaxial stacking layer)。在一些實施例中,高電子遷移率電晶體結構的磊晶疊層包含緩衝層、通道層以及障壁層。緩衝層可幫助減緩後續形成於緩衝層上方的一通道層的應力所產生的形變(strain),且防止缺陷形成於上方的通道層中。After that, an epitaxial stacking layer is formed on the
請參照第1B圖,根據本揭露之一些實施例,緩衝層106包含至少兩個超晶格部,以提供應力緩衝。如第1B圖所示,在晶種層104上方形成第一超晶格部(first superlattice part)SL1,以及在第一超晶格部SL1上方形成第二超晶格部(second superlattice part)SL2。Please refer to FIG. 1B. According to some embodiments of the present disclosure, the
一些實施例中,第一超晶格部SL1包括重複堆疊M1次的複數個第一單元(first unit),且各個第一單元包含兩個子層:第一子層(first sub-layer)1061以及位於第一子層1061上的第二子層(second sub-layer)1062。一些實施例中,第一子層1061為厚度b1奈米的Al
y1Ga
1-y1N,第二子層1062為厚度a1奈米的Al
x1Ga
1-x1N,其中y1小於x1。
In some embodiments, the first superlattice portion SL1 includes a plurality of first units repeatedly stacked M1 times, and each first unit includes two sub-layers: a
一些實施例中,第二超晶格部SL2包括重複堆疊M2次的複數個第二單元(second unit),且各個第二單元包含兩個子層:第三子層(third sub-layer)1063以及位於第三子層1063上的第四子層(fourth sub-layer)1064。一些實施例中,第三子層1063為厚度b2奈米的Al
y2Ga
1-y2N,第四子層1064為厚度a2奈米的Al
x2Ga
1-x2N,其中y2小於x2。
In some embodiments, the second superlattice portion SL2 includes a plurality of second units repeatedly stacked M2 times, and each second unit includes two sub-layers: a
其中,上述M1和M2為正整數,x1、y1、y2分別係大於0小於1,x2大於0小於等於1,且x1小於x2,或x1等於x2且y1小於y2。為簡化圖式,圖中僅以M1=M2=3為示例之用,當然本揭露之超晶格部的單元中子層堆疊次數並不僅限於此。Wherein, the above M1 and M2 are positive integers, x1, y1, and y2 are respectively greater than 0 and less than 1, x2 is greater than 0 and less than or equal to 1, and x1 is less than x2, or x1 is equal to x2 and y1 is less than y2. To simplify the diagram, the figure only uses M1=M2=3 as an example. Of course, the number of stacking times of the sub-layers in the unit cell of the superlattice portion of the present disclosure is not limited to this.
再者,根據實施例,第一超晶格部SL1可表示為:重複堆疊次數x[第二子層的超晶格結構/第一子層的超晶格結構]。Furthermore, according to an embodiment, the first superlattice portion SL1 may be expressed as: the number of repeated stacking times x [superlattice structure of the second sublayer/superlattice structure of the first sublayer].
根據實施例,第二超晶格部SL2可表示為:重複堆疊次數x[第四子層的超晶格結構/第三子層的超晶格結構]。According to an embodiment, the second superlattice part SL2 may be expressed as: the number of repeated stacking times x [superlattice structure of the fourth sublayer/superlattice structure of the third sublayer].
亦即,在此示例中,第一超晶格部SL1可表示為:That is, in this example, the first superlattice part SL1 can be expressed as:
M1x[a1(nm) Al
x1Ga
1-x1N / b1(nm) Al
y1Ga
1-y1N],其中,a1是單一第二子層1062的厚度(nm),b1是單一第一子層1061的厚度(nm),M1為第一單元重複堆疊的次數。在一示例中,M1大於20。
M1x[a1(nm) Al x1 Ga 1-x1 N / b1(nm) Al y1 Ga 1-y1 N], where a1 is the thickness (nm) of the single
在此示例中,第二超晶格部SL2可表示為:In this example, the second superlattice part SL2 can be expressed as:
M2x[a2(nm) Al
x2Ga
1-x2N / b2(nm) Al
y2Ga
1-y2N],其中,a2是單一第四子層1064的厚度(nm),b2是單一第三子層1063的厚度(nm),M2為第二單元重複堆疊的次數。在一示例中,M2大於20。
M2x[a2(nm) Al x2 Ga 1-x2 N / b2(nm) Al y2 Ga 1-y2 N], where a2 is the thickness (nm) of a single
在一些實施例中,x2大於0小於等於1,x1大於0小於1。較接近基板102的第一超晶格部SL1的第二子層1062的鋁在氮化鋁鎵(Al
x1Ga
1-x1N)中的莫耳分率x1係小於較遠離基板102的第二超晶格部SL2的第四子層1064的鋁在氮化鋁或氮化鋁鎵(Al
x2Ga
1-x2N)中的莫耳分率x2(亦即,x1>x2)。在一些其他實施例中,x1等於x2且y1小於y2。根據本揭露實施例所提出的第一超晶格部SL1和第二超晶格部SL2的超晶格結構,可降低晶圓的翹曲度,並避免晶圓破裂(crack-free)。
In some embodiments, x2 is greater than 0 and less than or equal to 1, and x1 is greater than 0 and less than 1. The
再者,較遠離基板102的第二超晶格部SL2中鋁的莫耳分率較高的子層厚度大於較接近基板102的第一超晶格部SL1中鋁的莫耳分率較高的子層厚度,可增加第二超晶格部SL2的拉伸應力(tensile stress)。於一些實施例中,a1小於a2。亦即,單一第二子層1062的厚度a1(nm)係小於單一第四子層1064的厚度a2(nm)(a1>a2),第二超晶格部SL2的拉伸應力大於第一超晶格部SL1的拉伸應力。Furthermore, the thickness of the sublayer with a higher molar fraction of aluminum in the second superlattice portion SL2 farther from the
在一些實施例中,y1和y2分別係大於0小於1,且y1小於y2。亦即,較接近基板102的第一超晶格部SL1的第一子層1061的鋁在氮化鋁鎵(Al
y1Ga
1-y1N)中的莫耳分率y1係小於較遠離基板102的第二超晶格部SL2的第三子層1063的鋁在氮化鋁鎵(Al
y2Ga
1-y2N)中的莫耳分率y2(y1>y2)。
In some embodiments, y1 and y2 are respectively greater than 0 and less than 1, and y1 is less than y2. That is, the molar fraction y1 of aluminum in the aluminum gallium nitride (Al y1 Ga 1-y1 N) of the
再者,於a1小於a2的一些實施例中,b1大於b2。亦即,含氮化鋁鎵的單一第一子層1061的厚度b1(nm)大於含氮化鋁鎵的單一第三子層1063的厚度b2(nm)(b1>b2),可增加第二超晶格部SL2的拉伸應力。Furthermore, in some embodiments where a1 is less than a2, b1 is greater than b2. That is, the thickness b1 (nm) of the single
另外,於一些其它實施例中,a1大於等於a2,b2大於b1,此亦可增加第二超晶格部SL2的拉伸應力。In addition, in some other embodiments, a1 is greater than or equal to a2, and b2 is greater than b1, which can also increase the tensile stress of the second superlattice portion SL2.
在一些實施例中,x1大於y1,x2大於y2。亦即,屬於第一超晶格部SL1的第二子層1062的鋁在氮化鋁鎵(Al
x1Ga
1-x1N)中的莫耳分率x1係大於第一子層1061的鋁在氮化鋁鎵(Al
y1Ga
1-y1N)中的莫耳分率y1。屬於第二超晶格部SL2的第四子層1064的鋁在氮化鋁或氮化鋁鎵(Al
x2Ga
1-x2N)中的莫耳分率x2係大於第三子層1063的鋁在氮化鋁鎵(Al
y2Ga
1-y2N)中的莫耳分率y2。
In some embodiments, x1 is greater than y1, and x2 is greater than y2. That is, the molar fraction x1 of aluminum in the
再者,於一些實施例中,x1在0.6~1的範圍之間,x2在0.8~1的範圍之間。一些實施例中,y1在0.1~0.3的範圍之間,y2在0.15~0.4的範圍之間。請參照表1,其列出根據本揭露含有2個超晶格部的一些實施例中,四個實驗的超晶格部之子層的鋁莫耳分率的範圍。實驗1為x1小於x2,y1小於y2。實驗2為x1等於x2,y1小於y2。實驗3為x1小於x2,且y1小於y2。實驗4為x1小於x2,y1等於y2。Furthermore, in some embodiments, x1 is in the range of 0.6 to 1, and x2 is in the range of 0.8 to 1. In some embodiments, y1 is in the range of 0.1 to 0.3, and y2 is in the range of 0.15 to 0.4. Please refer to Table 1, which lists the aluminum molar fraction ranges of the sub-layers of the superlattice part of the four experiments in some embodiments containing two superlattice parts according to the present disclosure.
表1
在一些實施例中,M1小於M2。亦即,第一超晶格部SL1所包含的第一單元所重複堆疊的次數M1係小於第二超晶格部SL2所包含的第二單元所重複堆疊的次數M2。In some embodiments, M1 is less than M2. That is, the number M1 of repeated stacking of the first unit included in the first superlattice portion SL1 is smaller than the number M2 of repeated stacking of the second unit included in the second superlattice portion SL2.
再者,在一些實施例中,磊晶成長上述子層而完成如第1B圖所示之緩衝層106後,所形成的第一超晶格部SL1的總厚度係小於第二超晶格部SL2的總厚度。Furthermore, in some embodiments, after epitaxial growth of the aforementioned sub-layers to complete the
根據上述,本揭露一些實施例所提出的第一超晶格部SL1和第二超晶格部SL2的超晶格結構,可大幅降低晶圓的翹曲度,例如使晶圓表面的中心和邊緣的一垂直高度差值在±10µm範圍之間。本揭露實施例並避免晶圓破片或裂縫(cracks)產生,進而提升在晶圓上所製作的各個半導體元件(例如電晶體)的電性表現,且明顯改善整面晶圓上製得多個半導體元件之間的電性均勻度,提高產品良率。Based on the above, the superlattice structure of the first superlattice portion SL1 and the second superlattice portion SL2 proposed in some embodiments of the present disclosure can greatly reduce the warpage of the wafer, for example, make the center of the wafer surface and A vertical height difference of the edge is in the range of ±10µm. The disclosed embodiments avoid the generation of wafer fragments or cracks, thereby improving the electrical performance of each semiconductor element (such as a transistor) fabricated on the wafer, and significantly improving the fabrication of multiple semiconductors on the entire wafer The electrical uniformity between components improves the product yield.
另外,本揭露之實施例的超晶格部還可加入摻質,且較遠離基板102的超晶格部的摻雜濃度係大於較接近基板102的超晶格部的摻雜濃度。在一些實施例中,第一超晶格部SL1更包含具有第一摻雜濃度的第一摻質,第二超晶格部SL2更包含具有第二摻雜濃度的第二摻質,且第二摻雜濃度大於第一摻雜濃度。一些實施例中,上述摻質,例如第一摻質和第二摻質,係獨立的選自碳或鐵。In addition, the superlattice part of the embodiment of the present disclosure can also be added with dopants, and the doping concentration of the superlattice part farther away from the
在一些實施例中,上述第一超晶格部SL1和第二超晶格部SL2的各個子層可由氫化物氣相磊晶法(HVPE)、分子束磊晶法(MBE)、有機金屬化學氣相沉積法(metalorganic chemical vapor deposition, MOCVD)、前述方法之組合或類似方法而形成。In some embodiments, the respective sub-layers of the first superlattice portion SL1 and the second superlattice portion SL2 may be hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), organometallic chemistry It is formed by metalorganic chemical vapor deposition (MOCVD), a combination of the foregoing methods, or similar methods.
雖然在如第1B圖所示的實施例中,緩衝層106包含兩個超晶格部,但在其他一些實施例中,緩衝層106包含三個甚至更多個超晶格部。Although in the embodiment shown in FIG. 1B, the
之後,參照第1C圖,在緩衝層106的上方磊晶形成通道層108。在一些實施例中,通道層108包括未摻雜的III-V族半導體材料。舉例而言,通道層108可以是由未摻雜的氮化鎵(GaN)所形成,但本發明並非以此為限。在一些其他的實施例中,通道層108包括AlGaN、AlN、GaAs、GaInP、AlGaAs、InP、InAlAs、InGaAs、其他適當的III-V族材料或上述之組合。在一些實施例中,可使用分子束磊晶法(MBE)、氫化物氣相磊晶法(HVPE)、有機金屬化學氣相沉積法(MOCVD)、其他適當之方法或上述方法之組合,而形成通道層108。於此示例中,通道層108例如是厚度約400nm的一氮化鎵層。After that, referring to FIG. 1C, the
接著,在通道層108上磊晶形成障壁層110。在一些實施例中,障壁層110包括未摻雜的III-V族半導體材料。舉例而言,障壁層110是由未摻雜的氮化鎵鋁(AlxGa1-xN,其中0>x>1)所形成,但本發明並不以此為限。在一些其他的實施例中,障壁層110亦可包括GaN、AlN、GaAs、GaInP、AlGaAs、InP、InAlAs、InGaAs、其他適當的III-V族材料或上述之組合。舉例而言,可使用分子束磊晶法、有機金屬化學氣相沉積法、氫化物氣相磊晶法、其他適當之方法或上述方法之組合形成障壁層110於通道層108之上。於此示例中,障壁層110例如是厚度約12.5nm的一氮化鎵鋁層。Next, the
因此,根據上述一些實施例的高電子遷移率電晶體結構中,在晶種層104上方的一磊晶堆疊(epitaxial stack)111係包含緩衝層106、通道層108以及障壁層110,如第1C圖所示。Therefore, in the high electron mobility transistor structure according to some of the above embodiments, an
另外,在一些實施例中,除了前述的緩衝層106、通道層108以及障壁層110,磊晶堆疊111亦可包含其他層膜;例如,在緩衝層106和通道層108之間可形成一碳摻雜層(carbon-doped layer),以提升半導體結構的崩潰電壓。如第1C圖所示,磊晶形成一含碳之氮化鎵(C-GaN)層107於第二超晶格部SL2上,以作為電性緩衝層,而通道層108則位於此含碳之氮化鎵層107上。In addition, in some embodiments, in addition to the
根據上述,在一些實施例中的通道層108與障壁層110係包括相異的材料,例如分別為氮化鎵(GaN)層和氮化鎵鋁(AlGaN)層,以於通道層108與障壁層110之間形成一異質界面。藉由異質材料的能隙差(band gap),可使二維電子氣(two-dimensional electron gas,2DEG)(未顯示)形成於此異質界面上。根據一些實施例所形成的半導體裝置,例如高電子遷移率電晶體(HEMT)裝置,則利用二維電子氣作為導電載子。According to the above, in some embodiments, the
在成長上述的磊晶材料層(例如包括緩衝層106、含碳之氮化鎵層107、通道層108以及障壁層110)後,係冷卻(cooling)此些材料層。冷卻後,再於磊晶堆疊111上形成所需元件。After the above-mentioned epitaxial material layers (including the
在一些實施例中,在磊晶堆疊111上形成一半導體元件,例如高電子遷移率電晶體,以及形成層間介電層IL
M覆蓋半導體元件(如後續第1E圖所示之一種半導體元件S
D以及層間介電層IL
M,其中層間介電層IL
M包含多層絕緣層)。
In some embodiments, a semiconductor element is formed on the
在一些實施例中,半導體元件S
D包含閘極電極,和分別形成於閘極電極之相對兩側的源極電極116和汲極電極118。根據本揭露之一些實施例,以製作一種增強型(enhanced mode,即normally-off)高電子遷移率電晶體為示例做一種半導體元件S
D的說明。在一些實施例中,在障壁層110上形成一摻雜III-V族半導體材料,並且進行圖案化製程,以於對應之後形成的閘極電極的下方形成一摻雜III-V族半導體層112P。
In some embodiments, the semiconductor element S D comprises a gate electrode, and the
如第1D圖所示,形成一摻雜III-V族半導體層112P於障壁層110上。一些實施例中,摻雜III-V族半導體層112P可包括適當的摻質,例如P型摻雜之氮化鎵所製成。一些其他的實施例中,摻雜III-V族半導體層112P可包含P型摻雜之氮化鋁鎵(AlGaN)、氮化鎵(GaN)、氮化鋁(AlN)、砷化鎵(GaAs)、磷化銦鎵(GaInP)、砷化鋁鎵(AlGaAs)、磷化銦(InP)、砷化銦鋁(InAlAs)、深化銦鎵(InGaAs)、其他合適的III-V族材料或前述之組合。此外,摻雜III-V族半導體層112P的形成方法可包含原子層沉積、化學氣相沉積、物理氣相沉積、磊晶製程、離子植入或原位(in-situ)摻雜製程。於此示例中,摻雜III-V族半導體層112P例如是厚度約80nm的一P型摻雜之氮化鎵(p-GaN)層。As shown in FIG. 1D, a doped III-
之後,如第1D圖所示,根據一些實施例,形成第一絕緣層114於磊晶堆疊111的上方且順應性地覆蓋摻雜III-V族半導體層112P。一些實施例中,第一絕緣層114可由氧化矽、氮化矽、氮氧化矽或其他合適的介電材料製成。再者,第一絕緣層114可藉由化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition,HDP-CVD)製程或前述之組合以形成。Thereafter, as shown in FIG. 1D, according to some embodiments, a first insulating
如第1E圖所示,在第一絕緣層114上方形成閘極電極112,且閘極電極112連接摻雜III-V族半導體層112P。一些實施例中,閘極電極112可包括金屬材料、金屬矽化物、多晶矽、其他適當之導電材料或上述之組合。閘極電極112與摻雜III-V族半導體層112P之間形成蕭特基接觸(Schottky contact)。一些實施例中,閘極電極112可由原子層沉積、化學氣相沉積、物理氣相沉積(如濺鍍)或類似製程形成。As shown in FIG. 1E, a
在一些實施例中,在第一絕緣層114的上方形成第二絕緣層115,且第二絕緣層115順應性地覆蓋閘極電極112,如第1E圖所示。第二絕緣層115的製程和材料可相似或相同於第一絕緣層114的製程和材料,在此不重複敘述。In some embodiments, a second insulating
之後,於閘極電極112的相對兩側分別形成源極電極116和汲極電極118。一些實施例中,如第1E圖所示,源極電極116和汲極電極118位於通道層108上且與通道層108電性接觸。一些實施例中,源極電極116和汲極電極118包含導電材料,例如金(Au)、鎳(Ni)、鉑(Pt)、鈀(Pd)、銥(Ir)、鈦(Ti)、鉻(Cr)、鎢(W)、鋁(Al)、銅(Cu)、氮化鉭(TaN)、氮化鈦(TiN)、矽化鎢(WSi
2)、前述之組合或類似材料。一些實施例中,源極電極116和汲極電極118可由原子層沉積、化學氣相沉積、物理氣相沉積(如濺鍍)、電子束蒸鍍(electron beam evaporation)、或類似製程形成。在一些實施例中,沉積形成源極電極116和汲極電極118的材料層後,更包含進行高溫熱製程例如快速熱退火(rapid thermal annealing)製程,以形成源極汲極歐姆接觸。
Thereafter, a
接著,在一些實施例中,如第1E圖所示,在第二絕緣層115的上方形成第三絕緣層124,且第三絕緣層124順應性地覆蓋源極電極116和汲極電極118。第三絕緣層124的製程和材料可相似或相同於第一絕緣層114的製程和材料,在此不重複敘述。第1E圖中的第一絕緣層114、第二絕緣層115和第三絕緣層124係構成層間介電層IL
M,以覆蓋半導體元件S
D。
Next, in some embodiments, as shown in FIG. 1E, a third
第2圖是根據本揭露的一些實施例之另一種半導體結構的剖面示意圖。前述如第1A-1E圖所示的一些實施例中,緩衝層106包含兩個超晶格部,而如第2圖所示的一些實施例中,緩衝層106包含三個超晶格部。FIG. 2 is a schematic cross-sectional view of another semiconductor structure according to some embodiments of the disclosure. In the foregoing embodiments as shown in FIGS. 1A-1E, the
參照第2圖,緩衝層106包含第一超晶格部SL1於晶種層104之上、第二超晶格部SL2於第一超晶格部SL1之上以及第三超晶格部(third superlattice part)SL3於第二超晶格部SL2之上。2, the
第一超晶格部SL1包括重複堆疊M1次的多個第一單元,且各個第一單元包含第一子層1061以及位於第一子層1061上的第二子層1062。第一子層1061為厚度b1奈米的Al
y1Ga
1-y1N,第二子層1062為厚度a1奈米的Al
x1Ga
1-x1N,其中y1小於x1。
The first superlattice portion SL1 includes a plurality of first cells repeatedly stacked M1 times, and each of the first cells includes a
第二超晶格部SL2包括重複堆疊M2次的複數個第二單元,且各個第二單元包含第三子層1063以及位於第三子層1063上的第四子層1064。一些實施例中,第三子層1063為厚度b2奈米的Al
y2Ga
1-y2N,第四子層1064為厚度a2奈米的Al
x2Ga
1-x2N,其中y2小於x2。
The second superlattice portion SL2 includes a plurality of second cells repeatedly stacked M2 times, and each second cell includes a
第三超晶格部SL3包括重複堆疊M3次的複數個第三單元,且各個第三單元包含第五子層1065以及位於第五子層1065上的第六子層1066。一些實施例中,第五子層1065為厚度b3奈米的Al
y3Ga
1-y3N,第六子層1066為厚度a3奈米的Al
x3Ga
1-x3N,其中y3小於x3。
The third superlattice portion SL3 includes a plurality of third cells repeatedly stacked M3 times, and each third cell includes a
類似上述示例,第三超晶格部SL3亦可表示為:Similar to the above example, the third superlattice part SL3 can also be expressed as:
M3x[a3(nm) Al
x3Ga
1-x3N / b3(nm) Al
y3Ga
1-y3N],其中,a3是單一第五子層1065的厚度(nm),b3是單一第六子層1066的厚度(nm),M3為第三單元重複堆疊的次數。在一示例中,M3大於20。
M3x[a3(nm) Al x3 Ga 1-x3 N / b3(nm) Al y3 Ga 1-y3 N], where a3 is the thickness (nm) of a single
在一些實施例中,M1、M2和M3為正整數,x1、y1、y2、y3分別係大於0小於1,x2和x3大於0小於等於1,且x1>x2> x3。亦即,較遠離基板102的第三超晶格部SL3的第六子層1066的鋁在Al
x3Ga
1-x3N中的莫耳分率x3大於第二超晶格部SL2的第四子層1064的鋁在Al
x2Ga
1-x2N的莫耳分率x2,大於較接近基板102的第一超晶格部SL1的第二子層1062的鋁在Al
x1Ga
1-x1N中的莫耳分率x1(即0> x1>x2>x3≤1)。在一些其他實施例中,x1小於x2,x2等於x3且y1小於y2,y2小於y3。
In some embodiments, M1, M2, and M3 are positive integers, x1, y1, y2, and y3 are respectively greater than 0 and less than 1, x2 and x3 are greater than 0 and less than or equal to 1, and x1>x2>x3. That is, the molar fraction x3 of aluminum in the
再者,較遠離基板102的第三超晶格部SL3中鋁的莫耳分率較高的子層厚度大於第二超晶格部SL2中鋁的莫耳分率較高的子層厚度,亦大於較接近基板102的第一超晶格部SL1中鋁的莫耳分率較高的子層厚度,亦即,a1>a2>a3。再者,於一些實施例中,b1>b2>b3。亦即,含氮化鋁鎵的單一第一子層1061的厚度b1(nm)大於含氮化鋁鎵的單一第三子層1063的厚度b2(nm),且含氮化鋁鎵的單一第五子層1065的厚度b3(nm)。如此,使得第三超晶格部SL3的拉伸應力(tensile stress)大於第二超晶格部SL2的拉伸應力,且第二超晶格部SL2的拉伸應力大於第一超晶格部SL1的拉伸應力。Furthermore, the thickness of the sublayer with a higher molar fraction of aluminum in the third superlattice portion SL3 farther from the
另外,於一些其它實施例中,再者,於一些實施例中,b1>b2>b3。亦即,含氮化鋁鎵的單一第一子層1061的厚度b1(nm)大於含氮化鋁鎵的單一第三子層1063的厚度b2(nm),且含氮化鋁鎵的單一第五子層1065的厚度b3(nm)。如此亦可使第一超晶格部SL1、第二超晶格部SL2和第三超晶格部SL3的拉伸應力依序逐漸增加。In addition, in some other embodiments, further, in some embodiments, b1>b2>b3. That is, the thickness b1 (nm) of the single
在一些另外實施例中,a1大於等於a2,a2大於等於a3(a1≥a2≥a3),且b3大於b2,b2大於b1(b3>b2>b1),如此亦可使第一超晶格部SL1、第二超晶格部SL2和第三超晶格部SL3的拉伸應力依序逐漸增加。In some other embodiments, a1 is greater than or equal to a2, a2 is greater than or equal to a3 (a1≥a2≥a3), and b3 is greater than b2, and b2 is greater than b1 (b3>b2>b1). This can also make the first superlattice part The tensile stresses of SL1, the second superlattice portion SL2, and the third superlattice portion SL3 gradually increase in order.
在一些實施例中,y1、y2、y3分別係大於0小於1,且y1>y2>y3。亦即,較接近基板102的第一超晶格部SL1的第一子層1061的鋁在Al
y1Ga
1-y1N中的莫耳分率y1係小於第二超晶格部SL2的第三子層1063的鋁在Al
y2Ga
1-y2N中的莫耳分率y2,且第二超晶格部SL2的第三子層1063的鋁在Al
y2Ga
1-y2N中的莫耳分率y2亦小於較遠離基板102的第三超晶格部SL3的第五子層1065的鋁在Al
y3Ga
1-y3N中的莫耳分率y3。
In some embodiments, y1, y2, and y3 are respectively greater than 0 and less than 1, and y1>y2>y3. That is, the molar fraction y1 of the
再者,於一些實施例中,x1在0.6~1的範圍之間,x2在0.8~1的範圍之間,x3在0.9~1的範圍之間。一些實施例中,y1在0.1~0.3的範圍之間,y2在0.15~0.4的範圍之間,y3在0.2~0.5的範圍之間。Furthermore, in some embodiments, x1 is in the range of 0.6 to 1, x2 is in the range of 0.8 to 1, and x3 is in the range of 0.9 to 1. In some embodiments, y1 is in the range of 0.1 to 0.3, y2 is in the range of 0.15 to 0.4, and y3 is in the range of 0.2 to 0.5.
請參照表2,其列出根據本揭露含有3個超晶格部的一些實施例中,四個實驗的超晶格部之子層的鋁莫耳分率的範圍。實驗1為x1小於x2,x2小於x3;y1小於y2,y2小於y3。實驗2為x1等於x2,,x2小於x3;y1小於y2,y2小於y3。實驗3為x1小於x2,x2小於x3,且y1小於y2,y2小於y3。實驗4為x1小於x2,x2小於x3,y1等於y2,y2小於y3。Please refer to Table 2, which lists the aluminum molar fraction ranges of the sub-layers of the superlattice part of the four experiments in some embodiments containing 3 superlattice parts according to the present disclosure.
表2
在一些實施例中,M1>M2>M3。亦即,第一超晶格部SL1所包含的第一單元所重複堆疊的次數M1小於第二超晶格部SL2所包含的第二單元所重複堆疊的次數M2,第二超晶格部SL2所包含的第二單元所重複堆疊的次數M2小於第三超晶格部SL3所包含的第三單元所重複堆疊的次數M3。In some embodiments, M1>M2>M3. That is, the number M1 of repeated stacking of the first unit included in the first superlattice portion SL1 is smaller than the number M2 of repeated stacking of the second unit included in the second superlattice portion SL2, and the second superlattice portion SL2 The number M2 of repeated stacking of the included second unit is less than the number M3 of repeated stacking of the third unit included in the third superlattice portion SL3.
再者,在一些實施例中,磊晶成長上述子層而完成如第2圖所示之緩衝層106後,所形成的第一超晶格部SL1的總厚度係小於第二超晶格部SL2的總厚度,第二超晶格部SL2的總厚度係小於第三超晶格部SL3的總厚度。Furthermore, in some embodiments, after epitaxial growth of the aforementioned sub-layers to complete the
另外,本揭露之實施例的超晶格部還可加入摻質,且較遠離基板102的超晶格部的摻雜濃度係大於較接近基板102的超晶格部的摻雜濃度。在一些實施例中,第一超晶格部SL1更包含具有第一摻雜濃度的第一摻質,第二超晶格部SL2更包含具有第二摻雜濃度的第二摻質,第三超晶格部SL3更包含具有第三摻雜濃度的第三摻質,且第二摻雜濃度大於第一摻雜濃度,第三摻雜濃度大於第二摻雜濃度。一些實施例中,上述摻質,例如第一摻質、第二摻質和第三摻質,係獨立的選自碳或鐵。In addition, the superlattice part of the embodiment of the present disclosure can also be added with dopants, and the doping concentration of the superlattice part farther away from the
第2圖所示的結構中其他各材料層、所進行的製程或使用的材料係與第1A-1E圖所示的結構中其他各材料層至所實施的製程和使用的材料相同或相似,在此不再贅述。根據如第2圖所示之一些實施例所提出的第一超晶格部SL1、第二超晶格部SL2和第三超晶格部SL3,可大幅降低晶圓的翹曲度(例如使晶圓表面的中心和邊緣的一垂直高度差值在±10µm範圍之間,甚至更少),並可避免晶圓破片或裂縫(cracks)產生,進而提升在晶圓上所製作的各個半導體元件(例如電晶體)的電性表現,以及明顯改善整面晶圓上製得多個半導體元件之間的電性均勻度。因此,根據本揭露的一些實施例所提出的超晶格結構可以明顯提高產品良率。The other material layers in the structure shown in Figure 2 and the processes or materials used are the same or similar to those of the other material layers in the structure shown in Figures 1A-1E. I won't repeat them here. The first superlattice portion SL1, the second superlattice portion SL2, and the third superlattice portion SL3 proposed according to some embodiments as shown in FIG. 2 can greatly reduce the warpage of the wafer (for example, make A vertical height difference between the center and the edge of the wafer surface is within ±10µm, or even less), which can avoid wafer chipping or cracks, thereby improving the various semiconductor components made on the wafer (Such as transistors) electrical performance, and significantly improve the electrical uniformity between multiple semiconductor components fabricated on the entire wafer. Therefore, the superlattice structure proposed according to some embodiments of the present disclosure can significantly improve the product yield.
第3圖顯示根據本揭露的一些實施例之一種半導體結構在磊晶成長時以及磊晶成長後的原位晶圓翹曲(in-situ wafer curvature)之曲線圖。橫軸為磊晶成長時間(秒),縱軸為原位晶圓翹曲值。FIG. 3 shows a graph of in-situ wafer curvature during and after epitaxial growth of a semiconductor structure according to some embodiments of the present disclosure. The horizontal axis is the epitaxial growth time (seconds), and the vertical axis is the in-situ wafer warpage value.
在一些實施例的半導體結構中,基板102包含具有陶瓷材料的基材102
C和密封基材102
C的絕緣層102
M。如第3圖所示,當在此基板102上磊晶成長第一超晶格部SL1和第二超晶格部SL2後,其具有如上述實施例之超晶格部之子層的鋁含量配置,在進行冷卻步驟前,超晶格部的子層具有拉伸應力(tensile stress),其原位晶圓翹曲之曲線下降,此時其晶圓的翹曲數值呈現負值(negative),亦即,晶圓具有一凹形剖面(concave cross-section)。接著進行冷卻降溫步驟,超晶格部的子層產生壓縮應力(compressive stress),而此壓縮應力與之前的拉伸應力相互補償(compensate),其原位晶圓翹曲之曲線向上攀升,即翹曲數值提高,當翹曲數值呈現正值(positive),晶圓即具有一凸形剖面(convex cross-section)。
In the semiconductor structure of some embodiments, the
因此,根據上述本揭露一些實施例之第一超晶格部SL1和第二超晶格部SL2所提出的子層的超晶格結構,由於前述超晶格部的子層中的鋁含量之配置,此些子層於磊晶成長時產生的拉伸應力可以被冷卻降溫中產生的壓縮應力所補償,使原本的凹形剖面漸漸變成平面。因此,降溫後的基板102和磊晶堆疊111的表面將更為平整,大幅減少晶圓翹曲(wafer bow)的程度,進而提升後續在晶圓上所製作的元件(例如高電子遷移率電晶體)的電性表現。Therefore, the superlattice structure of the sub-layers proposed in the first superlattice portion SL1 and the second superlattice portion SL2 according to some embodiments of the present disclosure described above is due to the lower aluminum content in the sub-layers of the aforementioned superlattice portion With the configuration, the tensile stress generated during the epitaxial growth of these sub-layers can be compensated by the compressive stress generated during cooling down, so that the original concave profile gradually becomes flat. Therefore, the surface of the
第4圖繪示一種翹曲的半導體結構的示意圖。圖中係簡單繪示根據本揭露之一些實施例的半導體結構,包含上述之基板102、晶種層104以及磊晶堆疊111。根據一些實施例,半導體結構的 晶圓翹曲(wafer bow)可定義為晶圓表面的中心例如在Z方向(或稱垂直方向)上的高度,以及晶圓表面的邊緣例如在Z方向上的高度,兩者之間的高度差。在一些示例中,可根據磊晶堆疊111的一參考表面(例如障壁層110的上表面)作為定義中所述之晶圓表面,以量測其中心和邊緣的高度差,而得到晶圓翹曲數值。在一些其他示例中,亦可根據基板102的一參考表面(例如基板102的底表面)作為定義中所述之晶圓表面,以量測其中心和邊緣的高度差,而得到晶圓翹曲數值。在此並不多做限制。FIG. 4 shows a schematic diagram of a warped semiconductor structure. The figure simply shows a semiconductor structure according to some embodiments of the present disclosure, including the
如第4圖所示,根據本揭露之一些實施例,在冷卻步驟後所形成的磊晶堆疊111之一頂面111a,例如障壁層110的上表面,其中心O和邊緣E的一垂直高度差值H(沿著Z方向)係在-10µm至+10µm範圍之間。As shown in FIG. 4, according to some embodiments of the present disclosure, a
相較於現有的超晶格結構,本揭露一些實施例的半導體結構所提出的超晶格結構,可以製得翹曲程度小的晶圓。當晶圓翹曲程度得以控制,在整面晶圓上製得的所有元件的電性均勻度亦可明顯改善,進而提高產品良率。實施例中亦對晶圓翹曲程度進行多次模擬實驗,以量測晶圓的起始翹曲(initial bow)數值和最終翹曲(final bow)數值。以下係提出其中幾次模擬實驗的數據結果做說明。Compared with the existing superlattice structure, the superlattice structure proposed in the semiconductor structure of some embodiments of the present disclosure can produce a wafer with a small degree of warpage. When the degree of wafer warpage is controlled, the electrical uniformity of all components fabricated on the entire wafer can also be significantly improved, thereby increasing the product yield. In the embodiment, multiple simulation experiments are also performed on the degree of wafer warpage to measure the initial bow value and final bow value of the wafer. The following is a description of the data results of several simulation experiments.
第5A、5B、5C圖分別繪示模擬實驗中對照組1、對照組2和實驗1的半導體結構的剖面示意圖。其中,對照組1(第5A圖)是使用單一種超晶格部SL
S的半導體結構,對照組2(第5B圖)是使用兩種超晶格部SL
C2和SL
C1的半導體結構,實驗1(第5C圖)是使用根據本揭露一實施例中例如第1C圖所示的半導體結構。
Figures 5A, 5B, and 5C respectively show schematic cross-sectional views of the semiconductor structures of the
此模擬實驗中三組半導體結構的區別在於超晶格層,與上述實施例相同的其餘材料層係沿用相同標號,例如在超晶格層上方係依序具有一含碳之氮化鎵層107(約1µm之C-GaN)、一通道層108(約400nm之GaN)、一障壁層110(約12.5nm之Al
0.25GaN)和一P型摻雜之氮化鎵材料層1120(約80nm之p型GaN,此於後續製成將形成如第1D圖所示之摻雜III-V族半導體層112P)。而這些材料層的相對位置和材料等細節,請參照上述說明,在此亦不贅述。
The difference between the three groups of semiconductor structures in this simulation experiment lies in the superlattice layer. The remaining material layers that are the same as those in the above embodiment use the same reference numerals. For example, there is a carbon-containing
三組半導體結構的超晶格層係表示如下:The superlattice layers of the three groups of semiconductor structures are expressed as follows:
對照組1之超晶格部SL S:180x[8nm AlN /10nm Al 0.1Ga 0.9N]。 The superlattice part SL S of the control group 1: 180x[8nm AlN/10nm Al 0.1 Ga 0.9 N].
對照組1(第5A圖)中,超晶格部SL S包括重複堆疊次數180次的單元,此單元包含厚度10nm之Al 0.1Ga 0.9N,以及位於Al 0.1Ga0.9N上方的厚度8nm之AlN。 Control group 1 (Fig. 5A), a superlattice SL S unit 180 comprises a number of stacked repeating units, the unit comprising 0.1 Ga 0.9 N, and Al 0.1 Ga0.9N positioned above the AlN thickness of 8nm thickness 10nm of Al .
對照組2(第5B圖)之超晶格部SL C1:25x[5nm AlN /28nm Al 0.2Ga 0.8N];以及 The superlattice part SL C1 of the control group 2 (Figure 5B): 25x[5nm AlN /28nm Al 0.2 Ga 0.8 N]; and
對照組2之超晶格部SL C2:168x[8nm AlN /10nm Al 0.1Ga 0.9N]。其中超晶格部SL C2位於超晶格部SL C1之上。 The superlattice part SL C2 of the control group 2: 168x [8nm AlN/10nm Al 0.1 Ga 0.9 N]. The superlattice part SL C2 is located above the superlattice part SL C1.
實驗1(第5C圖)之第一超晶格部SL1:25x[12nm Al 0.74Ga 0.26N /26nm Al 0.17Ga 0.83N];以及 The first superlattice part SL1 of Experiment 1 (Figure 5C): 25x [12nm Al 0.74 Ga 0.26 N /26nm Al 0.17 Ga 0.83 N]; and
實驗1之第二超晶格部SL2:80x[20nm Al 1.00Ga 0.0N /18nm Al 0.23Ga 0.77N]。 The second superlattice part SL2 of Experiment 1: 80x[20nm Al 1.00 Ga 0.0 N /18nm Al 0.23 Ga 0.77 N].
第6圖係為模擬實驗中對照組1、對照組2和實驗1的晶圓翹曲結果。其中,橫軸為晶圓的起始翹曲(initial bow)數值,縱軸為晶圓的最終翹曲(final bow)數值。▲為對照組1的晶圓翹曲結果,▓為對照組2的晶圓翹曲結果,●為實驗1的晶圓翹曲結果。Figure 6 shows the results of wafer warpage in the
在模擬實驗中,使用單一種超晶格部SL
S的對照組1的半導體結構,在起始翹曲值10µm~60µm範圍之間,所量測到的最終翹曲值在約50µm以上,且最終翹曲值隨著起始翹曲值的增加而增加。使用兩種超晶格部SL
C2和SL
C1的對照組2的半導體結構,在起始翹曲10µm~60µm範圍之間,所量測到的最終翹曲值在約50µm~約80µm範圍之間。而使用本揭露一實施例的實驗1的半導體結構,在起始翹曲10µm~60µm範圍之間,所量測到的最終翹曲值都不超過約40µm,且一些實驗中最終翹曲值不超過約20µm,又一些實驗中最終翹曲值不超過約10µm。因此本揭露一些實施例所提出的超晶格結構確實大幅降低晶圓的最終翹曲狀態。一般而言,最終翹曲值達約50µm或50µm以上,晶圓會破片或產生裂縫。因此若以最終翹曲值50µm設為晶圓翹曲良率(bow yield rate)的一臨界值,則本揭露一些實施例所提出的超晶格結構可改善晶圓翹曲良率達到100%。
In the simulation experiment, the semiconductor structure of the
綜上所述,本揭露一些實施例所提出的半導體裝置,所包含的第一超晶格部SL1和第二超晶格部SL2的超晶格結構,可降低晶圓的翹曲度(例如,最終晶圓表面的中心和邊緣的一垂直高度差值係在-10µm~+10µm的範圍之間),並可避免晶圓破片或裂縫(cracks)產生。因此,應用本揭露之實施例所提出的半導體裝置亦可以提升在晶圓上所製作的各個半導體元件(例如電晶體)的電性表現,並且明顯改善整面晶圓上製得多個半導體元件之間的電性均勻度,進而提高產品良率。另外,實施例提出的半導體裝置的形成方法,亦與現有製程相容,也不會增加製造成本,即可大幅改善晶圓翹曲。In summary, the semiconductor devices proposed in some embodiments of the present disclosure include the superlattice structure of the first superlattice portion SL1 and the second superlattice portion SL2, which can reduce the warpage of the wafer (for example, , The vertical height difference between the center and the edge of the final wafer surface is within the range of -10μm~+10μm), and the generation of wafer fragments or cracks (cracks) can be avoided. Therefore, applying the semiconductor device proposed in the embodiment of the present disclosure can also improve the electrical performance of each semiconductor device (such as a transistor) fabricated on a wafer, and significantly improve the overall performance of multiple semiconductor devices fabricated on the entire wafer. The uniformity of electrical properties between time, and then improve the product yield. In addition, the method for forming the semiconductor device proposed in the embodiment is also compatible with the existing manufacturing process and does not increase the manufacturing cost, which can greatly improve the wafer warpage.
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in several preferred embodiments as described above, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make any changes and modifications without departing from the spirit and scope of the present invention. Retouching, therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.
102:基板
102
C:基材
102
M:絕緣層
104:晶種層
106:緩衝層
SL1:第一超晶格部
1061:第一子層
1062:第二子層
SL2:第二超晶格部
1063:第三子層
1064:第四子層
SL3:第三超晶格部
1065:第五子層
1066:第六子層
107:含碳之氮化鎵層
108:通道層
110:障壁層
111:磊晶堆疊
S
D:半導體元件
IL
M:層間介電層
112P:摻雜III-V族半導體層
112:閘極電極
116:源極電極
118:汲極電極
114:第一絕緣層
115:第二絕緣層
124:第三絕緣層
102: substrate 102 C : base material 102 M : insulating layer 104: seed layer 106: buffer layer SL1: first superlattice portion 1061: first sublayer 1062: second sublayer SL2: second superlattice portion 1063: third sublayer 1064: fourth sublayer SL3: third superlattice portion 1065: fifth sublayer 1066: sixth sublayer 107: carbon-containing gallium nitride layer 108: channel layer 110: barrier layer 111 : epitaxial stack S D: a semiconductor element IL M: an
第1A-1E圖是根據本揭露的一些實施例之形成半導體結構的製程各個中間階段的剖面示意圖。
第2圖是根據本揭露的一些實施例之另一種半導體結構的剖面示意圖。
第3圖顯示根據本揭露的一些實施例之一種半導體結構在磊晶成長時以及磊晶成長後的原位晶圓翹曲(in-situ wafer curvature)之曲線圖。
第4圖繪示一種翹曲的半導體結構的示意圖。
第5A、5B、5C圖分別繪示模擬實驗中對照組1、對照組2和實驗1的半導體結構的剖面示意圖。其中,對照組1(第5A圖)是使用單一種超晶格部SL
S的半導體結構,對照組2(第5B圖)是使用兩種超晶格部SL
C2和SL
C1的半導體結構,實驗1(第5C圖)是使用本揭露一實施例的半導體結構。
第6圖係為模擬實驗中對照組1、對照組2和實驗1的晶圓翹曲結果。其中,橫軸為晶圓的起始翹曲(initial bow)數值,縱軸為晶圓的最終翹曲(final bow)數值。
FIGS. 1A-1E are schematic cross-sectional views of various intermediate stages of the process of forming a semiconductor structure according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view of another semiconductor structure according to some embodiments of the disclosure. FIG. 3 shows a graph of in-situ wafer curvature during and after epitaxial growth of a semiconductor structure according to some embodiments of the present disclosure. FIG. 4 shows a schematic diagram of a warped semiconductor structure. Figures 5A, 5B, and 5C respectively show schematic cross-sectional views of the semiconductor structure of the
102:基板 102: substrate
102C:基材 102 C : Base material
102M:絕緣層 102 M : Insulation layer
104:晶種層 104: Seed layer
106:緩衝層 106: buffer layer
SL1:第一超晶格部 SL1: The first superlattice part
1061:第一子層 1061: first sublayer
1062:第二子層 1062: second sublayer
SL2:第二超晶格部 SL2: The second superlattice part
1063:第三子層 1063: third sublayer
1064:第四子層 1064: fourth sublayer
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