TWI658588B - High hole mobility transistor - Google Patents

Abstract

An embodiment of the present invention provides a high hole mobility transistor including a back barrier layer on a substrate, a conduction layer on the back barrier layer, and a channel region in the conduction layer, which is adjacent to the conduction layer and the back barrier. Interface of the layer; doped layer on the conduction layer; gate electrode on the doped layer; source / drain electrode on two opposite sides of the gate electrode; and band adjustment layer on the doped layer And is electrically connected to the gate electrode; wherein the band adjustment layer is an N-type doped III-V semiconductor.

Description

High hole mobility transistor

Embodiments of the present invention relate to a semiconductor technology, and more particularly to a high hole mobility transistor.

GaN materials are widely used in high-power semiconductor devices due to their wide band gaps and high-speed mobile electronics, especially in RF and power applications.

Traditionally, High Electron Mobility Transistors (HEMT) use three or five semiconductor stacks to form heterojunctions at their interfaces. Due to the band bending at the heterojunction, a potential well is formed deep in the conduction band and a two-dimensional electron gas (2DEG) is formed in the potential band. Since electrons move in the channel, the high electron mobility transistor is an N-type element.

Traditionally, a three-five semiconductor stack can also be used to form a two-dimensional hold gas (2DHG) at its interface, and the band structure can be changed by using a gate recess. Reducing the two-dimensional hole gas to form an enhancement mode (E-mode) high hole mobility transistor (HHMT). However, because the depth and uniformity of the etched gate are not easy to control, it is easy to cause abnormal values of electrical parameters. In addition, the recessed area of the gate will also cause high resistance of the channel.

Although existing high hole mobility transistors are generally in demand, But not all aspects are satisfactory, especially the uniformity and channel resistance of enhanced high hole mobility transistors need to be further improved.

An embodiment of the present invention provides a high hole mobility transistor including a back barrier layer on a substrate, a conduction layer on the back barrier layer, and a channel region in the conduction layer, which is adjacent to the conduction layer and the back barrier. Interface of the layer; doped layer on the conduction layer; gate electrode on the doped layer; source / drain electrode on two opposite sides of the gate electrode; and band adjustment layer on the doped layer And is electrically connected to the gate electrode; wherein the band adjustment layer is an N-type doped III-V semiconductor.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, several embodiments are described below in detail, in conjunction with the accompanying drawings, as follows.

100, 200, 300, 400‧‧‧ high hole mobility transistor

102‧‧‧ substrate

104‧‧‧back barrier

106‧‧‧Conducting layer

108‧‧‧ doped layer

110‧‧‧passage zone

112‧‧‧ Band adjustment layer

114‧‧‧ passivation layer

116‧‧‧Gate electrode

118‧‧‧source / drain electrode

120C, 122C‧‧‧Guide band

120V, 122V‧‧‧valence band

120F‧‧‧ Fermi Level

224, 324, 424‧‧‧ dielectric layers

AA’‧‧‧ Segment

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention.

FIG. 1 is a schematic cross-sectional view of a high hole mobility transistor according to some embodiments.

FIG. 2 is a band diagram of a high hole mobility transistor according to some embodiments.

FIG. 3 is a schematic cross-sectional view of a high hole mobility transistor according to other embodiments.

FIG. 4 is a diagram illustrating a high hole mobility transistor according to still other embodiments. Schematic cross-section.

FIG. 5 is a schematic cross-sectional view of a high hole mobility transistor according to still other embodiments.

Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes specific embodiments of the elements and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present invention should not be limited by this. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and also includes the other between the first feature and the second feature. An embodiment of a feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.

In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. These space-related terms Words are used to facilitate the description of the relationship between one or more elements or features and other elements or features in the illustration. These spatially related terms include different positions of the device in use or operation, as well as in the drawings. The described orientation. When the device is turned to a different orientation (rotated 90 degrees or other orientation), the spatially related adjectives used in it will also be interpreted in terms of the orientation after turning.

Here, the terms "about", "approximately", and "mostly" generally indicate within a given value or range within 20%, preferably within 10%, and more preferably within 5%, or 3 Within%, or within 2%, or within 1%, or within 0.5%. Should pay attention It is said that the quantity provided in the description is an approximate quantity, that is, without approximation "about", "approximately", and "probably", "approximately", "approximately", and "probably" may still be implied Meaning.

An embodiment of the present invention provides a high hole mobility transistor (HHMT). A band adjustment layer is formed on a channel region to reduce the energy band and enable two-dimensional hole gas (two- Dimensional hold gas (2DHG) disappears, forming an enhancement mode (E-mode) high hole mobility transistor. This element has better uniformity than traditional processes, and can maintain the channel with a low resistance value.

FIG. 1 is a cross-sectional view of a high hole mobility transistor 100 according to some embodiments of the present invention. As shown in FIG. 1, a substrate 102 is provided. In some embodiments, the substrate 102 may include Si, SiC, or Al ₂ O ₃ (sapphire), and may be a single-layer substrate, a multilayer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In some embodiments, the substrate 102 may be a single crystal substrate. In some embodiments, the substrate 102 may also include a semiconductor on insulator (SOI) substrate. The insulating semiconductor substrate may include a base plate, a buried oxide layer provided on the base plate, or a buried oxide layer. Of the semiconductor layer. In some embodiments, the substrate 102 may include a single layer or multiple buffer layers to avoid a lattice mismatch between the silicon substrate and a device formed thereon. In some embodiments, the substrate 102 may also include a III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the substrate is a substrate material that can withstand high voltages.

Next, a back barrier layer 104 is formed on the substrate 102. In some embodiments, the back barrier layer 104 includes a III-V semiconductor, such as Al _x Ga _1-x N or Al _x In _y Ga _1-xy N, where 0 <x <1, and 0 <y <1 . In some embodiments, the thickness of the back barrier layer 104 is between 0.1um and 5um. In some embodiments, molecular-beam epitaxy (MBE), metal organic vapor deposition (MOCVD), chemical vapor deposition (CVD), A hydride vapor phase epitaxy (HVPE) method, other suitable methods, or a combination of the above is used to form the back barrier layer 104 on the substrate 102.

Next, a conductive layer 106 is formed on the back barrier layer 104. In some embodiments, the conductive layer 106 includes an undoped III-V semiconductor, such as undoped GaN. In some embodiments, the thickness of the conductive layer 106 is between 0.1um and 5um. In some embodiments, molecular-beam epitaxy (MBE), metal organic vapor deposition (MOCVD), chemical vapor deposition (CVD), The hydride vapor phase epitaxy (HVPE), other appropriate methods, or a combination thereof may form a conductive layer 106 on the back barrier layer 104.

Next, a doped layer 108 is formed on the conductive layer 106. In some embodiments, the doped layer 108 includes a P-type doped III-V semiconductor, such as P-type doped GaN. In some embodiments, the doping layer 108 may be doped with Mg, Zn, Ca, Be, Sr, Ba, Ra, or C, and its P-type doping concentration is between 1E15 / cm ³ and 1E20 / cm ³ . . The thickness of the doped layer 108 is between 0.1um and 5um. In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), A doped layer 108 is formed on the conductive layer 106 by a hydride vapor phase epitaxy (HVPE), other suitable methods, or a combination thereof. In some embodiments, the doping layer 108 may be formed using in-situ doping, or by ion implantation.

Because the band gaps of the materials of the doped layer 108 / the conductive layer 106 and the back barrier layer 104 are different, a heterojunction is formed at the interface between the doped layer 108 / the conductive layer 106 and the back barrier layer 104 ( heterojunction), and the doped layer 108 is doped with a P-type dopant, which raises the energy band, bends the band at the heterojunction, and forms a quantum well at the bend of the valence band. The hole is confined in the quantum well, so a two-dimensional hole gas (2DHG) is formed at the interface between the conducting layer 106 and the back barrier layer 104, and then a conducting current is formed. As shown in FIG. 1, a channel region 110 is formed at an interface between the conductive layer 106 and the back barrier layer 104. The channel region 110 is a place where a two-dimensional hole gas forms a conduction current. The thickness of the channel region 110 is between 1 nm and 100 nm.

Next, a band adjustment layer 112 is formed on the doped layer 108. In some embodiments, the band adjustment layer 112 is an N-type doped III-V semiconductor, including N-type doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs, and its N-type doping concentration. Between 1E15 / cm ³ and 1E20 / cm ³ . The band adjustment layer 112 has a thickness between 10 nm and 5000 nm. In some embodiments, molecular-beam epitaxy (MBE), metal organic vapor deposition (MOCVD), chemical vapor deposition (CVD), Hydrogen vapor phase epitaxy (HVPE), other appropriate methods, or a combination of the above to deposit N-type doped III-V semiconductors, and then pattern them by, for example, a lithography process and an etching process A band adjustment layer 112 is formed. In some embodiments, the band adjustment layer 112 is located below the gate electrode formed later.

The band adjustment layer 112 is doped with an N-type dopant, which can reduce the energy band and make the high hole mobility transistor 100 an enhancement mode (E-mode) high hole mobility transistor (to be described in detail below). As described). Compared with the depletion mode (D-mode) high hole mobility transistor, the enhanced (E-mode) high hole mobility transistor is safer and has lower standby power dissipation , Can also reduce circuit complexity and production costs.

Next, a passivation layer 114 is formed on the doped layer 108 and the band adjustment layer 112. The passivation layer 114 may include SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) , Other insulating materials, or a combination of the above. The thickness of the passivation layer 114 is between 0.1um and 1um. In some embodiments, organic metal vapor deposition (MOCVD), chemical vapor deposition (CVD), spin-coating, and other suitable methods may be used. Or a combination thereof to form the passivation layer 114. In some embodiments, the passivation layer 114 may be conformally formed on the doped layer 108 and the energy band adjustment layer 112. In some embodiments, the passivation layer 114 has a flat upper surface by chemical mechanical polishing (CMP). The passivation layer 114 can protect the underlying film layer and provide physical isolation and structural support.

Next, a gate electrode 116 is formed on the band adjustment layer 112, and a source / drain electrode 118 is formed on both sides of the gate electrode 116. In some embodiments, the gate electrode 116 may include a metal material, polycrystalline silicon, metal silicide, other suitable conductive materials, or a combination thereof. In some embodiments, the source / drain electrode 118 may include Ti, Al, Au, Pd, other suitable metal materials, alloys thereof, or a combination thereof. In some embodiments, an opening may be formed in the passivation layer 114 by a lithography and etching process, so that a part of the band adjustment layer 112 and the doped layer 108 are exposed. Electroplating, sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition An atomic layer deposition (ALD), other suitable method, or a combination thereof is used to fill the electrode material at the opening of the passivation layer 114 to form the gate electrode 116 and the source / drain electrode 118.

The embodiment in FIG. 1 is only an example, and the embodiment of the present invention is not limited thereto. For example, another doping layer (not shown) may be formed on the doping layer 108, and the dopant and doping concentration may be the same as or different from the doping layer 108. In this way, by adjusting the composition and concentration of different doped layers, it can have a higher degree of freedom to adjust the band structure of the high hole mobility transistor.

Fig. 2 is an energy band diagram along the section direction of line AA 'in Fig. 1. A comparative example is an energy band structure of a high hole mobility transistor without an energy band adjustment layer 112, including a conduction band 120C and a valence band. 120V. The embodiment is an energy band structure of a high hole mobility transistor provided with an energy band adjustment layer 112, including a conduction band 122C and a valence band 122V. In the comparative example of FIG. 2, the P-type doped layer 108 connects the conductive layer 106 and the back resistor. The quantum well energy at the interface of the barrier layer 104 is higher than the Fermi level 120F. Therefore, a two-dimensional hole gas is formed above the Fermi level in the conduction layer 106, thereby forming a conduction current.

In the embodiment shown in FIG. 2, the energy band adjustment layer 112 is an N-type doped Group III semiconductor. The N-type doping causes the energy band to decrease, and the valence band at the interface between the conduction layer 106 and the back barrier layer 104 is 122V The energy is lower than the Fermi level 120F, which results in that no two-dimensional hole gas is generated in the conducting layer 106, and therefore there is no conducting current.

In the above embodiment, since the energy band adjustment layer 112 lowers the energy band, the high hole mobility transistor 100 is in an off state when the gate voltage is not applied. Therefore, the high hole mobility transistor 100 is in an enhancement mode. E-mode) high hole mobility transistor.

As described above, the present invention provides an energy band adjustment layer on a channel region of a high hole mobility transistor, and uses N-type doping to change the energy band to form an enhanced high hole mobility transistor. Since it is not formed by using the traditional etched gate, the problem of poor uniformity caused by the etched gate can be avoided, while maintaining a low channel resistance value.

FIG. 3 is a cross-sectional view of a high hole mobility transistor 200 according to another embodiment of the present invention. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the foregoing embodiment is that a dielectric layer 224 is further provided between the band adjustment layer 112 and the gate electrode 116 to form a metal-insulator-semiconductor (MIS) structure. The dielectric layer 224 includes SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , MgO, Sc ₂ O ₃ , HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO ₂ , ZnO ₂ , ZrO ₂ , AlSiN ₃ , SiC, or Ta ₂ O ₅ , similar materials, or a combination thereof. In some embodiments, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), high density plasma chemical vapor deposition (CVD), (HDPCVD), atomic layer deposition (ALD), spin-coating, and / or other suitable techniques to deposit the dielectric material, and then pattern it by, for example, a lithography process and an etching process. A dielectric layer 224 is formed. The dielectric layer 224 can reduce the gate leakage current, increase the voltage range that the gate can withstand, and further reduce the channel resistance. The thickness of the dielectric layer 224 is between 1 nm and 100 nm. If the thickness of the dielectric layer 224 is too thick, it may affect the device speed. If the thickness of the dielectric layer 224 is too thin, the gate leakage current may be increased.

In the embodiment shown in FIG. 3, a dielectric layer is provided between the band adjustment layer of the enhanced high hole mobility transistor and the gate electrode, which can reduce the gate leakage current, and improve the gate withstand voltage. voltage range.

FIG. 4 is a cross-sectional view of a high hole mobility transistor 300 according to another embodiment of the present invention. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that the dielectric layer 324 extends to the upper surface of the doped layer 108.

Compared with the process of the enhanced high hole mobility transistor 200, the process of the enhanced high hole mobility transistor 300 is formed conformally with the dielectric layer 324 after doping the band adjustment layer 112. A passivation layer 114 is formed on the impurity layer 108 and the band adjustment layer 112.

The dielectric layer 324 can reduce the gate leakage current, increase the voltage range that the gate can withstand, and further reduce the channel resistance. At the same time, since the dielectric layer is not 324 performs an etching process, and the enhanced high hole mobility transistor 300 process can save production time and costs.

FIG. 5 is a cross-sectional view of a high hole mobility transistor 400 according to another embodiment of the present invention. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that the dielectric layer 424 extends to the upper surface of the passivation layer 114.

Compared with the process of the enhanced high hole mobility transistor 200, the enhanced high hole mobility transistor 400 process, after forming the passivation layer 114, forms an opening in the passivation layer 114 through, for example, a lithography process and an etching process. A part of the band adjustment layer 112 is exposed. Next, a dielectric layer 424 is conformally formed on the band adjustment layer 112 and the passivation layer 114, and then a gate electrode 116 is formed.

The dielectric layer 424 can reduce the gate leakage current, increase the voltage range that the gate can withstand, and further reduce the channel resistance. The process of the enhanced high hole mobility transistor 400 provides another way to form the dielectric layer 424, which can be selected according to process requirements.

In summary, an embodiment of the present invention provides a high hole mobility transistor (HHMT) structure. An energy band adjustment layer is formed above the channel region, and the local two-dimensional electricity is changed by the energy band structure change. Two-dimensional hole gas (2DHG) disappears, forming an enhanced high hole mobility transistor while maintaining good uniformity and low resistance of the channel. In addition, a dielectric layer can be provided between the band adjustment layer and the gate electrode to reduce the gate leakage current, increase the voltage range that the gate can withstand, and further reduce the channel resistance.

The foregoing outlines the features of many embodiments, so anyone with ordinary knowledge in the technical field can better understand the aspects of the embodiments of the present invention to. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the embodiments of the present invention without difficulty to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such equivalent creations do not exceed the spirit and scope of the embodiments of the present invention.

Claims (11)

A high hole mobility transistor (HHMT) includes a back barrier layer on a substrate, a conduction layer on the back barrier layer, and a channel region. Is located in the conductive layer, adjacent to an interface between the conductive layer and the back barrier layer; a doped layer on the conductive layer; a gate electrode on the doped layer; a source / drain Electrodes are respectively located on two opposite sides of the gate electrode; a band adjustment layer is located on the doping layer and is electrically connected to the gate electrode; a passivation layer covers the doping Layer and the energy band adjustment layer; and a dielectric layer between the energy band adjustment layer and the gate electrode; wherein the energy band adjustment layer is an N-type doped Group III semiconductor, and the passivation layer A part is located between the band adjustment layer and the source / drain electrode, wherein the N-type doping concentration of the band adjustment layer is between 1E15 / cm ³ and 1E20 / cm ³ . The high hole mobility transistor according to item 1 of the patent application scope, wherein the band adjustment layer includes N-type doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs. The high hole mobility transistor described in item 1 of the patent application scope, wherein the back barrier layer includes Al _x Ga _1-x N or Al _x In _y Ga _1-xy N, where 0 <x <1 and 0 <y <1. The high hole mobility transistor described in item 1 of the patent application scope, wherein the conductive layer includes GaN. The high hole mobility transistor described in item 1 of the patent application scope, wherein the doped layer includes P-type doped GaN. The high hole mobility transistor according to item 5 of the patent application scope, wherein the doped layer is doped with Mg, Zn, Ca, Be, Sr, Ba, Ra, or C. The high hole mobility transistor described in item 1 of the scope of the patent application, wherein the substrate includes a Group III or III semiconductor. The high hole mobility transistor described in item 1 of the patent application scope, wherein the passivation layer includes SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzene ring Butene (BCB), or polybenzoxazole (PBO). The high hole mobility transistor described in item 1 of the patent application scope, wherein the dielectric layer includes SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , MgO, Sc ₂ O ₃ , HfO ₂ , HfSiO, HfSiON , HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO ₂ , ZnO ₂ , ZrO ₂ , AlSiN ₃ , SiC, or Ta ₂ O ₅ . The high hole mobility transistor described in item 1 of the patent application scope, wherein the dielectric layer extends to an upper surface of the doped layer. The high hole mobility transistor as described in item 1 of the patent application scope, wherein the dielectric layer extends to an upper surface of the passivation layer.