TWI676290B - High electron mobility transistor and method for forming the same - Google Patents

Abstract

An embodiment of the present invention provides a high electron mobility transistor, including: a buffer layer is located on the substrate; a barrier layer is located on the buffer layer; a channel region is located in the buffer layer; the interface between the buffer layer and the barrier layer is adjacent; Located on the barrier layer, including the first band adjustment layer, the second band adjustment layer, and the third band adjustment layer from top to bottom; the passivation layer is located on the barrier layer and adjacent to the band adjustment layer; the gate electrode It is located on the energy band adjustment layer and is electrically connected to the energy band adjustment layer; and the source / drain electrodes are respectively located on two opposite sides of the gate electrode, pass through the passivation layer, and are disposed on the barrier layer; The band adjustment layer, the second energy band adjustment layer, and the third energy band adjustment layer include an N-type doped, undoped, and P-type doped Group III semiconductor or Group II semiconductor.

Description

High electron mobility transistor and its forming method

Embodiments of the present invention relate to a semiconductor technology, and more particularly to a high electron mobility transistor.

High Electron Mobility Transistor (HEMT) is widely used in high-power semiconductor devices due to its advantages such as high breakdown voltage and high output voltage to meet consumer electronics, communications hardware, electric vehicles, or home appliances. Market demand.

Enhancement mode (E-mode) high electron mobility transistor is in the off state when no gate voltage is applied. Traditionally, P-type semiconductors are used to be electrically connected to the gate as a band adjustment layer. With the requirements of ultra-high voltage applications, higher threshold voltages (Vt) of high electron mobility transistors are required. However, the resulting gate leakage is also greater, which can easily cause component damage.

Although the existing high electron mobility transistors are generally in line with the requirements, they are not satisfactory in all aspects. In particular, improving the threshold voltage and reducing the gate leakage of high electron mobility transistors still needs to be further improved.

According to an embodiment, the present invention provides a high electron mobility transistor including: a buffer layer on a substrate; a barrier layer on the buffer layer; The track area is located in the buffer layer, adjacent to the interface between the buffer layer and the barrier layer; the band adjustment layer is located on the barrier layer, and includes a first band adjustment layer, a second band adjustment layer, and a third layer from top to bottom. Band adjustment layer; passivation layer, located on the barrier layer, adjacent to the band adjustment layer; gate electrode, located on the band adjustment layer, and electrically connected to the band adjustment layer; and source / drain electrodes, respectively It is located on two opposite sides of the gate electrode, passes through the passivation layer, and is disposed on the barrier layer; the first energy band adjustment layer includes an N-type doped group III semiconductor or an N-type doped group II semiconductor, and a second energy band The adjustment layer includes an undoped III-V semiconductor or an undoped II-VI semiconductor, and the third band adjustment layer includes a P-type doped III-V semiconductor or a P-type doped II-VI semiconductor.

According to other embodiments, the present invention provides a method for forming a high electron mobility transistor, including: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; a channel region is located in the buffer layer; Interface of barrier layer; forming a band adjustment layer on the barrier layer, including a first band adjustment layer, a second band adjustment layer, and a third band adjustment layer from top to bottom; forming a passivation layer on the barrier On the layer, adjacent to the band adjustment layer; forming a gate electrode on the band adjustment layer and electrically connecting with the band adjustment layer; and forming a source / drain electrode on two opposite sides of the gate electrode, passing through A passivation layer is provided on the barrier layer; the first energy band adjustment layer includes an N-type doped Group III semiconductor or an N-type doped Group II or Six semiconductor, and the second energy band adjustment layer includes an undoped Group III or Five semiconductor or The undoped group two and six semiconductors, and the third band adjustment layer include a p-type doped group three or five semiconductor or a p-type doped group six or six semiconductor.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, several embodiments are described below in detail, in conjunction with the accompanying drawings, as follows.

100‧‧‧High Electron Mobility Transistor

102‧‧‧ substrate

104‧‧‧Buffer layer

106‧‧‧ barrier layer

108‧‧‧ passage area

110‧‧‧ band adjustment layer

110a‧‧‧First band adjustment layer

110b‧‧‧Second band adjustment layer

110c‧‧‧Third band adjustment layer

110P‧‧‧band adjustment layer

110NP‧‧‧ Band Adjustment Layer

112‧‧‧first passivation layer

112a‧‧‧Second passivation layer

114‧‧‧source / drain electrode

116‧‧‧Gate electrode

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention.

Figures 1 to 3, 4A, 4B, 4C, and 5 to 8 are schematic cross-sectional views illustrating different stages of forming a high electron mobility transistor according to some embodiments.

FIG. 9 is a diagram of a drain current-gate voltage of a high electron mobility transistor according to some embodiments.

FIG. 10 is a gate current-gate voltage diagram of a high electron mobility transistor according to some embodiments.

Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes specific embodiments of the elements and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present invention should not be limited by this. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and also includes the other between the first feature and the second feature. An embodiment of a feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.

In addition, space-relative terms may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spaces are relatively relative Words are used to facilitate the description of one or more elements or features in the illustration. In relation to another element (s) or feature, these spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used in it will also be interpreted according to the orientation after turning.

Here, the terms "about", "approximately", and "mostly" generally indicate within a given value or range within 20%, preferably within 10%, and more preferably within 5%, or 3 Within%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the description is an approximate quantity, that is, the "about", "approximately", "approximately", "approximately", " "Maybe."

Although the steps in some of the embodiments described are performed in a particular order, these steps may also be performed in other logical orders. In different embodiments, some of the steps described may be replaced or omitted, and some other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. The high electron mobility transistor in the embodiment of the present invention may add other features. In different embodiments, some features may be replaced or omitted.

An embodiment of the present invention provides a high electron mobility transistor (HEMT). An energy band adjustment layer is formed under a gate electrode, and the band adjustment layer is N-type doped, undoped, and P in order from top to bottom. The band adjustment layer structure of the type-doped III-V semiconductor or II-V semiconductor can effectively increase the threshold voltage and reduce gate leakage.

1 to 8 are schematic cross-sectional views illustrating different stages of forming the high electron mobility transistor 100 according to some embodiments. As shown in FIG. 1, a substrate 102 is provided. In some embodiments, the substrate 102 may be an Al ₂ O ₃ (sapphire) substrate. In addition, the above semiconductor substrate may also be an element semiconductor, including silicon or germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide, and gallium arsenide Gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium alloy (SiGe), phosphorous arsenic alloy (GaAsP), AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or any of the above materials combination. In some embodiments, the substrate 102 may be a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In addition, the substrate 102 may also be a semiconductor on insulator substrate. The insulating semiconductor substrate may include a base plate, a buried oxide layer provided on the base plate, or a semiconductor layer provided on the buried oxide layer.

Next, as shown in FIG. 2, a buffer layer 104 is formed on the substrate 102. In some embodiments, the buffer layer 104 includes a III-V semiconductor, such as GaN. The buffer layer 104 may also include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other appropriate III-V semiconductor materials, or a combination thereof. In some embodiments, the thickness of the buffer layer 104 is less than 20 μm. In some embodiments, molecular-beam epitaxy (MBE), organic metal vapor deposition (MOCVD), hydride vapor phase epitaxy, (HVPE), other appropriate methods, or a combination thereof to form a buffer layer 104 on the substrate 102.

Next, as shown in FIG. 3, a barrier layer 106 is formed on the buffer layer 104. In some embodiments, the barrier layer 106 includes a material different from the buffer layer 104. The barrier layer 106 may include a III-V semiconductor, such as Al _x Ga _1-x N, where 0 <x <1. The barrier layer 106 may also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or a combination thereof. In some embodiments, the thickness of the barrier layer 106 is less than 100 nm. In some embodiments, the barrier layer 106 may be formed on the buffer layer 104 using a molecular beam epitaxy method, an organic metal vapor deposition method, a hydride vapor epitaxy method, other suitable methods, or a combination thereof.

Because the materials of the buffer layer 104 and the barrier layer 106 are different, and their band gaps are different, a heterojunction is formed at the interface between the buffer layer 104 and the barrier layer 106. The energy band at the heterojunction is bent, and the quantum well is formed deep in the conduction band. The electrons generated by the piezoelectric effect are confined in the quantum well. Therefore, the buffer layer 104 and the barrier A two-dimensional electron gas (2DEG) is formed at the interface of the layer 106 to form an on-current. As shown in FIG. 3, a channel region 108 is formed at the interface between the buffer layer 104 and the barrier layer 106, and the channel region 108 is where the two-dimensional electron gas forms a conduction current.

Next, as shown in FIG. 4A, a band adjustment layer 110 is formed on the barrier layer 106. In some embodiments, the energy band adjustment layer 110 includes a first energy band adjustment layer 110a, a second energy band adjustment layer 110b, and a third energy band adjustment layer 110c from top to bottom. In some embodiments, the first band adjustment layer 110a is in direct contact with the second band adjustment layer 110b, and the second band adjustment layer 110b is in direct contact with the third band adjustment layer 110c.

In some embodiments, the third band adjustment layer 110c includes a P-type doped III-V semiconductor or a P-type doped II-VI semiconductor. For example, the third band adjustment layer 110c includes P-doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe, SiGe, SiC, or ZnS. In some embodiments, the third band adjustment layer 110c is P-type doped with Mg, Zn, Ca, Be, Sr, Ba, Ra, C, Ag, Au, Li, or Na, and the P-type doped The concentration is between 1E15 / cm ³ and 1E25 / cm ³ . In some embodiments, the thickness of the third band adjustment layer 110c is 1% to 99% of the thickness of the band adjustment layer 110, and preferably 50% to 90% of the thickness of the band adjustment layer 110. The thickness of the band adjustment layer 110c is between 1 nm and 1000 nm. In some embodiments, the P-type doping concentration of the third band adjustment layer 110 c and the height of the band can be adjusted by adjusting the P-type doping concentration of the third band adjustment layer 110 c. For example, when the P-type doping concentration of the third band adjustment layer 110c is higher and the thickness is thicker, the band may be higher, so that two-dimensional electron gas generated in the channel region 108 may be less. Conversely, when the P-type doping concentration of the third energy band adjustment layer 110c is low and the thickness is thin, the energy band may be lower, so more two-dimensional electron gas may be generated in the channel region 108. In some embodiments, molecular beam epitaxy, organic metal vapor deposition, chemical vapor deposition, and hydride vapor epitaxy can be used to deposit P-type doped Group III semiconductors on the barrier layer 106. Material or P-type doped two or six semiconductor materials to form the third band adjustment layer 110c.

In some embodiments, the second band adjustment layer 110b includes an undoped III-V semiconductor or an undoped II-VI semiconductor. For example, the second band adjustment layer 110b includes undoped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe, SiGe, SiC, or ZnS. In some embodiments, the thickness of the second band adjustment layer 110 b is the band adjustment layer 110. 1% to 99% of the thickness, preferably 10% to 50% of the thickness of the band adjustment layer 110. In some embodiments, the thickness of the second band adjustment layer 110b is between 10 nm and 1000 nm. If the thickness of the second energy band adjustment layer 110b is too thick, the gate resistance is too high. If the thickness of the second energy band adjustment layer 110b is too thin, the empty space is too small when a reverse bias is applied to the energy band adjustment layer 110. , Can not effectively reduce the gate leakage. In some embodiments, molecular beam epitaxy, organic metal vapor deposition, chemical vapor deposition, and hydride vapor epitaxy can be used to deposit undoped quintile on the third band adjustment layer 110c. Group semiconductor material or undoped group two or six semiconductor material to form the second band adjustment layer 110b.

In some embodiments, the first band adjustment layer 110a includes an N-type doped III-V semiconductor or an N-type doped II-VI semiconductor. For example, the first band adjustment layer 110a includes N-doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe, SiC, SiGe, or ZnS. In some embodiments, the first band adjustment layer 110a is N-type doped with Si, C, Ge, Sn, Pb, Cl, Br, or I, and the N-type doping concentration is between 1E15 / cm ³ to 1E25 / cm ^3. In some embodiments, the thickness of the first band adjustment layer 110a is 1% to 99% of the thickness of the band adjustment layer 110, and preferably 10% to 50% of the thickness of the band adjustment layer 110. The thickness of the band adjustment layer 110a is between 1 nm and 1000 nm. In some embodiments, the N-type doping concentration of the first energy band adjustment layer 110a and the height of the energy band can be adjusted by adjusting the N-type doping concentration of the first energy band adjustment layer 110a. For example, when the N-type doping concentration of the first band adjustment layer 110a is high and the thickness is thick, when the high electron mobility transistor 100 is turned on (gate voltage is greater than zero), the entire band adjustment layer 110 is formed. The energy band is less easily reduced. Conversely, when the N-type doping concentration of the first band adjustment layer 110a is low and the thickness is thin, when the high electron mobility transistor 100 is turned on (gate voltage is greater than zero), the overall band of the band adjustment layer 110 is Easier to lower. In some embodiments, molecular beam epitaxy, organometallic vapor deposition, chemical vapor deposition, and hydride vapor epitaxy can be used to deposit N-type doped three on the second band adjustment layer 110b. The Group 5 semiconductor material or the N-type doped Group 2 or 6 semiconductor material forms the first band adjustment layer 110a.

In some embodiments, the first energy band adjustment layer 110a, the second energy band adjustment layer 110b, and the third energy band adjustment layer 110c may include the same Group III semiconductor material or the Group II semiconductor material. The doped, undoped, and P-doped dopants and the energy band structure of the energy band adjustment layer 110. In other embodiments, the first band adjustment layer 110a, the second band adjustment layer 110b, and the third band adjustment layer 110c may include different Group III semiconductor materials or Group II semiconductor materials. Different band structures of materials, and dopants of N-type doped, undoped and P-type doped and concentration-adjusted band adjustment layer 110.

Then, the first band adjustment layer 110a, the second band adjustment layer 110b, and the third band adjustment layer 110c may be patterned by a lithography and etching process to form the band adjustment layer 110. Lithography processes can include photoresist coating (e.g. spin coating), soft baking, mask alignment, exposure pattern, post-exposure baking, photoresist development, cleaning and drying (e.g. hard baking )), Other suitable technologies, or a combination thereof. The etching process may include a dry etching process (for example, reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination thereof. In some embodiments, the band adjustment layer 110 is located below a gate electrode to be formed later.

It is worth noting that in the foregoing description, the third band adjustment layer 110c, the second band adjustment layer 110b, and the first band adjustment layer were separately deposited. After 110a, they are patterned together to form the band adjustment layer 110. However, the embodiments of the present invention are not limited thereto. In some embodiments, the third band adjustment layer 110c, the second band adjustment layer 110b, and the first band adjustment layer 110a may be separately patterned to form the band adjustment layer band adjustment layer 110 after being deposited.

Compared to the P band adjustment layer structure 110P including only the third band adjustment layer 110c as shown in FIG. 4B or the first band adjustment layer 110a and the first band adjustment layer as shown in FIG. 4C from top to bottom The NP band adjustment layer structure 110NP of the three band adjustment layer 110c forms a NIP band including the first band adjustment layer 110a, the second band adjustment layer 110b, and the third band adjustment layer 110c from top to bottom. The adjustment layer 110 can increase the energy band when the high electron mobility transistor 100 is turned on (gate voltage is greater than zero). As a result, the conduction band energy at the interface between the buffer layer 104 and the barrier layer 106 is higher, resulting in less two-dimensional electron gas in the channel region 108. If the on-state current is to be formed in the channel region 108, the gate voltage needs to be increased before the energy band can be lowered to form the on-state current. Therefore, the NIP band adjustment layer structure 110 can increase the threshold voltage of the high electron mobility transistor 100 and eliminate the ultra-high voltage noise interference. In some embodiments, the electron mobility transistor 100 having the NIP band adjustment layer structure 110 may be suitable for applications greater than 1000V.

In addition, compared with the P band adjustment layer structure 110P or the NP band adjustment layer structure 110NP, the NIP band adjustment layer structure 110 is reverse biased when the high electron mobility transistor 100 is turned on (gate voltage is greater than zero), At this time, the second band adjustment layer 110b can increase the empty area. In this way, the gate leakage can be greatly reduced, thereby increasing the operating range of the gate voltage.

It should be noted that the band adjustment layer 110 in FIG. 4A includes three band adjustment layers 110a, 110b, and 110c. However, the embodiment of the present invention does not use This is a limitation. The energy band adjustment layer 110 may include three or more energy band adjustment layers. Generally speaking, the energy band adjustment layer 110 includes an N-type doped group III semiconductor or an N-type doped group II semiconductor, and an undoped layer. The three or five group semiconductors or undoped two or six group semiconductors, and the P type doped three or five group semiconductors or the p type doped two or six group semiconductors depend on the process requirements.

Next, as shown in FIG. 5, a first passivation layer 112 is formed on the barrier layer 106 and is adjacent to the band adjustment layer 110. In some embodiments, the first passivation layer 112 may include SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzene Polybenzoxazole (PBO), other insulating materials, or a combination thereof. The thickness of the first passivation layer 112 is between 1 nm and 1000 nm. In some embodiments, the first passivation layer 112 may be formed using an organic metal vapor deposition method, a chemical vapor deposition method, a spin coating method, other suitable methods, or a combination thereof. In some embodiments, the first passivation layer 112 may be blanket formed on the barrier layer 106 and the band adjustment layer 110. Then, the first passivation layer 112 may have a flat upper surface by chemical mechanical polishing (CMP). In some embodiments, the top surface of the first passivation layer 112 is the same height as the top surface of the band adjustment layer 110. The first passivation layer 112 can protect the underlying film layer and provide physical isolation and structural support.

Next, as shown in FIG. 6, a source / drain electrode 114 is formed, which passes through the first passivation layer 112 and is disposed on the barrier layer 106. In some embodiments, each of the source / drain electrodes 114 may include Ti, Al, W, Au, Pd, other suitable metal materials, an alloy thereof, or a combination thereof. In some embodiments, a lithography process and an etching process may be performed to form a source / drain electrode in the first passivation layer 112. The electrode is opened, and then conductive is deposited on the first passivation layer 112 by chemical vapor deposition, physical vapor deposition (such as evaporation or sputtering), electroplating, atomic layer deposition, other appropriate methods, or a combination thereof. The material is filled into the above source / drain electrode opening, and then conductive materials other than the opening are removed by an etching process to form the source / drain electrode 114.

Next, as shown in FIG. 7, a second passivation layer 112 a is formed on the first passivation layer 112, the band adjustment layer 110, and the source / drain electrode 114. In some embodiments, the second passivation layer 112a may include SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzene Polybenzoxazole (PBO), other insulating materials, or a combination thereof. In some embodiments, the first passivation layer 112 is the same material as the second passivation layer 112a. In other embodiments, the materials of the first passivation layer 112 and the second passivation layer 112a are different. The thickness of the second passivation layer 112a is between 1 nm and 1000 nm. In some embodiments, the second passivation layer 112a may be formed using an organic metal vapor deposition method, a chemical vapor deposition method, a spin coating method, other suitable methods, or a combination thereof. In some embodiments, a second passivation layer 112 a may be conformally formed on the first passivation layer 112, the band adjustment layer 110, and the source / drain electrode 114.

Next, as shown in FIG. 8, a gate electrode 116 is formed on the band adjustment layer 110. In some embodiments, the gate electrode 116 may include polycrystalline silicon, a metal (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or a combination thereof), a metal alloy, a metal nitride (e.g., nitrogen Tungsten silicide, molybdenum nitride, titanium nitride, tantalum nitride, or the like, or metal silicides (such as tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, hafnium silicide, etc.) Things, Or a combination thereof), a metal oxide (ruthenium oxide, indium tin oxide, the like, or a combination thereof), other applicable conductive materials, or a combination thereof. In some embodiments, a lithography process and an etching process may be performed to form a gate opening in the second passivation layer 112a, and then a chemical vapor deposition process (such as a low pressure vapor deposition process or a plasma-assisted chemical vapor deposition) is used. Process), physical vapor deposition process (such as resistance heating evaporation, electron beam evaporation, or sputtering), electroplating, atomic layer deposition, other suitable processes, or a combination of the above on the second passivation layer A conductive material is deposited on 112a and filled into the gate opening, and then conductive materials other than the opening are removed by an etching process to form the gate electrode 116. In some embodiments, the gate electrode 116 is electrically connected to the band adjustment layer 110.

As described above, the formation of N-type doped Group III semiconductors or N-type doped Group II semiconductors, undoped Group III or V semiconductors or undoped Group II or VI semiconductors, and N-type band adjustment layer for P-type doped III or V semiconductors or P-type doped II or 6 semiconductors can increase the critical voltage of high electron mobility transistors, eliminate extra-high voltage noise interference, and reduce gate leakage current To increase the gate operating range.

FIG. 9 is a diagram of a drain current-gate voltage of a high electron mobility transistor according to some embodiments. The dotted line data represents the high electron mobility transistor including the P band adjustment layer structure 110P, the chain line data represents the high electron mobility transistor including the NP band adjustment layer structure 110NP, and the solid line data represents the high electron mobility transistor including the NIP energy Belt adjustment layer 110.

As shown in FIG. 9, under the same drain current, the gate voltage of the high electron mobility transistor having the NIP structure band adjustment layer 110 is large. That is, the criticality of the high electron mobility transistor having the NIP structure band adjustment layer 110 The voltage is high. Therefore, the NIP structure band adjustment layer 110 can effectively increase the threshold voltage when the high electron mobility transistor is turned on (gate voltage is greater than zero).

FIG. 10 is a gate current-gate voltage diagram of a high electron mobility transistor according to some embodiments. The dotted line data represents the high electron mobility transistor including the P band adjustment layer structure 110P, the chain line data represents the high electron mobility transistor including the NP band adjustment layer structure 110NP, and the solid line data represents the high electron mobility transistor including the NIP energy Belt adjustment layer 110.

As shown in FIG. 10, under the same gate voltage, the gate current of the high electron mobility transistor having the NIP structure band adjustment layer 110 is small. That is, the gate leakage of the high electron mobility transistor having the NIP structure band adjustment layer 110 is small. Therefore, the NIP structure band adjustment layer 110 can effectively increase the range of gate operation.

In summary, the embodiment of the present invention provides a method for forming a high electron mobility transistor, and an N-type doped Group III semiconductor or an N-type doped Group II semiconductor, Band adjustment layers (NIP structure band adjustment layers) for doped Group III semiconductors or undoped Group II semiconductors and P-type doped Group III semiconductors or P-type doped Group II semiconductors The critical voltage of the electron mobility transistor can eliminate the extra-high voltage noise interference and reduce the gate leakage current to increase the gate operating range.

It should be noted that, although the advantages and effects of some embodiments of the present invention have been described above, not all embodiments need to achieve all the advantages and effects.

The above outlines the features of many embodiments, so anyone with ordinary knowledge in the technical field can better understand the various embodiments of the present invention. Facing. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the embodiments of the present invention without difficulty to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such equivalent creations do not exceed the spirit and scope of the embodiments of the present invention.

Claims (20)

A high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a barrier layer on the buffer layer; and a channel region in the buffer layer adjacent to the buffer layer. An interface between the buffer layer and the barrier layer; a band adjustment layer is located on the barrier layer and includes a first band adjustment layer, a second band adjustment layer, And a third band adjustment layer; a first passivation layer located on the barrier layer, adjacent to the band adjustment layer, and the band adjustment layer is completely embedded in the first passivation layer; a gate electrode is located at The energy band adjustment layer is electrically connected to the energy band adjustment layer; a source / drain electrode is located on two opposite sides of the gate electrode, passes through the first passivation layer, and is disposed on the barrier Layer; and a second passivation layer on the top surface of the band adjustment layer; wherein the first band adjustment layer includes an N-type doped Group III semiconductor or an N-type doped Group II semiconductor. The two-band adjustment layer includes an undoped III-V semiconductor or an undoped II-VI semiconductor Conductor, the third band adjustment layer includes a P-type doped III-V semiconductor or a P-type doped semiconductor twenty-six. The high electron mobility transistor according to item 1 of the scope of the patent application, wherein the first energy band adjustment layer is in direct contact with the second energy band adjustment layer, and the second energy band adjustment layer is in contact with the third energy band. The adjustment layer is in direct contact. The high electron mobility transistor according to item 1 of the patent application scope, wherein the second band adjustment layer includes undoped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe, SiGe, SiC, or ZnS. The high electron mobility transistor according to item 1 of the patent application range, wherein the thickness of the second band adjustment layer is between 1 nm and 1000 nm. The high electron mobility transistor described in item 1 of the scope of patent application, wherein the thickness of the second band adjustment layer is 1% to 99% of the thickness of the band adjustment layer. The high electron mobility transistor according to item 1 of the patent application scope, wherein the first band adjustment layer includes N-doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe , SiC, SiGe, or ZnS. The high electron mobility transistor according to item 1 of the patent application scope, wherein the first band adjustment layer is doped with Si, C, Ge, Sn, Pb, Cl, Br, or I. The high electron mobility transistor according to item 1 of the patent application scope, wherein the N-type doping concentration of the first band adjustment layer is between 1E15 / cm ³ and 1E25 / cm ³ . The high electron mobility transistor described in item 1 of the scope of the patent application, wherein the thickness of the first band adjustment layer is 1% to 99% of the thickness of the band adjustment layer. The high electron mobility transistor according to item 1 of the patent application scope, wherein the third band adjustment layer includes P-type doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe , SiC, SiGe, or ZnS. The high electron mobility transistor according to item 1 of the patent application scope, wherein the third band adjustment layer is made of Mg, Zn, Ca, Be, Sr, Ba, Ra, C, Ag, Au, Li, or Na Doping. The high electron mobility transistor according to item 1 of the scope of the patent application, wherein the P-type doping concentration of the third band adjustment layer is between 1E15 / cm ³ and 1E25 / cm ³ . The high electron mobility transistor described in item 1 of the scope of patent application, wherein the thickness of the third band adjustment layer is 1% to 99% of the thickness of the band adjustment layer. The high electron mobility transistor described in item 1 of the patent application scope, wherein the barrier layer includes Al _x Ga _1-x N, where 0 <x <1. The high electron mobility transistor according to item 1 of the patent application scope, wherein the buffer layer includes GaN. The high electron mobility transistor as described in item 1 of the scope of the patent application, wherein the passivation layer includes SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), phencyclidine Benzocyclobutene (BCB) or polybenzoxazole (PBO). A method for forming a high electron mobility transistor (HEMT) includes: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer, wherein a channel region is located in the buffer layer; Adjacent to the interface between the buffer layer and the barrier layer; forming a band adjustment layer on the barrier layer, including a first band adjustment layer and a second band from top to bottom An adjustment layer and a third energy band adjustment layer; forming a first passivation layer on the barrier layer, adjacent to the energy band adjustment layer, and the energy band adjustment layer is completely embedded in the first passivation layer; forming a gate An electrode is on the band adjustment layer and is electrically connected to the band adjustment layer. A source / drain electrode is formed on two opposite sides of the gate electrode, passes through the first passivation layer, and is disposed on On the barrier layer; and forming a second passivation layer on the top surface of the band adjustment layer; wherein the first band adjustment layer includes an N-type doped Group III semiconductor or an N-type doped Group II semiconductor The second band adjustment layer includes an undoped III-V semiconductor or Twenty-six doped semiconductors, the energy band adjustment layer comprises a third P-type doped III-V semiconductor or a P-type doped semiconductor twenty-six. The method for forming a high electron mobility transistor as described in item 17 of the patent application scope, wherein the second band adjustment layer includes undoped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS , CdTe, SiGe, SiC, or ZnS. The method for forming a high electron mobility transistor as described in item 17 of the patent application, wherein the thickness of the second band adjustment layer is between 1 nm and 1000 nm. The method for forming a high electron mobility transistor as described in item 17 of the scope of the patent application, wherein the thickness of the second band adjustment layer is 1% to 99% of the thickness of the band adjustment layer.