TWI678723B - High electron mobility transistor and methods for forming the same - Google Patents

Abstract

x<1；漸變式緩衝層設置於基底上方，其中漸變式緩衝層包含多個Al_yGa_(1-y)N層，其中0

y<1；以及通道層設置於漸變式緩衝層上方。 A high electron mobility transistor device includes a substrate; a superlattice buffer layer is disposed above the substrate, wherein the superlattice buffer layer includes a plurality of sets of alternating layers, and each set of alternating layers includes at least one AlN layer and at least one staggered array. Al _x Ga _(1-x) N layers, where 0

x <1; the gradient buffer layer is disposed above the substrate, where the gradient buffer layer includes multiple Al _y Ga _(1-y) N layers, where 0

y <1; and the channel layer is disposed above the gradient buffer layer.

Description

High electron mobility transistor device and manufacturing method thereof

This disclosure relates to a semiconductor manufacturing technology, and more particularly to a high electron mobility transistor device and a method for manufacturing the same.

High electron mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET), is a kind of Field effect transistor (FET), which is composed of semiconductor materials with different energy gaps. A two-dimensional electron gas (2 DEG) layer is generated near the formed interface adjacent to different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor can have advantages such as high breakdown voltage, high electron mobility, low on-resistance, and low input capacitance, and is therefore suitable for high power components.

However, because the base material and the semiconductor layer material are different, the two have problems such as lattice differences and different thermal expansion coefficients, which easily lead to structural deformation in the high electron mobility transistor. Therefore, a buffer layer is provided between the base and the semiconductor layer. To alleviate this structural deformation and its possible defects. In order to improve the existing high electron mobility transistors in various aspects, such as the formation Semiconductor layers with better crystalline properties and reduced manufacturing costs need to continue to improve the placement of buffer layers.

x<1；漸變式緩衝層設置於基底上方，其中漸變式緩衝層包含多個Al_yGa_(1-y)N層，其中0

y<1；以及通道層設置於漸變式緩衝層上方。 According to some embodiments of the present disclosure, a high electron mobility transistor device is provided. The device includes a substrate; a superlattice buffer layer is disposed above the substrate, wherein the superlattice buffer layer includes a plurality of sets of alternating layers, each set of alternating layers including at least one AlN layer and at least one Al _x Ga _(1-x) arranged alternately N layers, where 0

x <1; the gradient buffer layer is disposed above the substrate, where the gradient buffer layer includes multiple Al _y Ga _(1-y) N layers, where 0

y <1; and the channel layer is disposed above the gradient buffer layer.

In some embodiments, these Al _x Ga _(1-x) N layers have the same x value in each set of alternating layers.

In some embodiments, these Al _x Ga _(1-x) N layers have different x values for different sets of alternating layers.

In some embodiments, the x value of the Al _x Ga _(1-x) N layers of the set of alternating layers adjacent to the substrate is greater than the x value of the Al _x Ga _(1-x) N layers of the set of alternating layers away from the substrate value.

In some embodiments, in each set of alternating layers, the thickness of the AlN layer is in a range of 1 nm to 20 nm, and the thickness of the Al _x Ga _(1-x) N layer is in a range of 5 nm to 100 nm.

In some embodiments, the ratio of the thickness of the Al _x Ga _(1-x) N layer to the thickness of the AlN layer ranges from 3 to 10.

In some embodiments, the thickness of each of these Al _y Ga _(1-y) N layers is in the range of 50 nm to 500 nm.

In some embodiments, the substrate adjacent the _{Al y Ga (1-y)} y N layer is greater than the value of the substrate remote from the _{Al y Ga (1-y)} y N layer value.

In some embodiments, the gradient buffer layer is disposed above the superlattice buffer layer.

In some embodiments, the high electron mobility transistor device further includes a nucleation layer disposed between the substrate and the superlattice buffer layer, wherein the nucleation layer includes aluminum nitride, aluminum gallium nitride, or a combination thereof.

In some embodiments, the high electron mobility transistor device further includes a barrier layer disposed above the channel layer; and a source electrode, a drain electrode, and a gate electrode disposed above the barrier layer.

x<1；在基底上方形成漸變式緩衝層，其中漸變式緩衝層包含多個AlyGa(1-y)N層，其中0

y<1；以及在漸變式緩衝層上方形成通道層。 According to some embodiments of the present disclosure, a method for manufacturing a high electron mobility transistor device is provided. The method includes: forming a substrate; forming a superlattice buffer layer above the substrate, wherein the superlattice buffer layer includes a plurality of sets of alternating layers, each set of alternating layers including at least one AlN layer and at least one AlxGa (1-x) staggered N layers, where 0

x <1; a gradient buffer layer is formed above the substrate, where the gradient buffer layer includes multiple AlyGa (1-y) N layers, where 0

y <1; and forming a channel layer above the gradient buffer layer.

In some embodiments, these Al _x Ga _(1-x) N layers have the same x value in each set of alternating layers.

In some embodiments, these Al _x Ga _(1-x) N layers have different x values for different sets of alternating layers.

In some embodiments, the x value of the Al _x Ga _(1-x) N layers of the set of alternating layers adjacent to the substrate is greater than the x value of the Al _x Ga _(1-x) N layers of the set of alternating layers away from the substrate value.

In some embodiments, in each set of alternating layers, the thickness of the AlN layer is in the range of 1 nm to 20 nm, the thickness of the Al _x Ga _(1-x) N layer is in the range of 5 nm to 100 nm, and the Al _x Ga _{(1- x)} The ratio of the thickness of the N layer to the thickness of the AlN layer is in the range of 3 to 10.

In some embodiments, the thickness of each of these Al _y Ga _(1-y) N layers is in the range of 50 nm to 500 nm.

In some embodiments, the substrate adjacent the _{Al y Ga (1-y)} y N layer is greater than the value of the substrate remote from the _{Al y Ga (1-y)} y N layer value.

In some embodiments, a graded buffer layer is formed over the superlattice buffer layer.

In some embodiments, the method for manufacturing a high electron mobility transistor device further includes forming a nucleation layer between the substrate and the superlattice buffer layer, wherein the nucleation layer includes aluminum nitride, aluminum gallium nitride, or a combination thereof. .

100‧‧‧High Electron Mobility Transistor Device

110‧‧‧ substrate

120‧‧‧nucleation layer

130‧‧‧Superlattice buffer layer

132‧‧‧The first set of alternating layers

132a, 134a, 136a‧‧‧Al _x Ga _(1-x) N layers

132b, 134b, 136b‧‧‧AlN layer

134‧‧‧Second set of alternating layers

136‧‧‧The third group of alternating layers

140‧‧‧ Gradient buffer layer

142‧‧‧First Al _y Ga _(1-y) N layer

144‧‧‧Second Al _y Ga _(1-y) N layer

146‧‧‧Third Al _y Ga _(1-y) N layer

150‧‧‧channel floor

152‧‧‧Two-dimensional electron gas

160‧‧‧Barrier layer

170‧‧‧Source

180‧‧‧Gate

190‧‧‧ Drain

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the features of the present disclosure.

FIGS. 1-5 are schematic cross-sectional views illustrating various stages in manufacturing a high electron mobility transistor device according to some embodiments.

The following summarizes some embodiments so that those with ordinary knowledge in the technical field to which the present invention pertains can more easily understand the present invention, but these embodiments are not intended to limit the present invention. It can be understood that the technical field to which the present invention belongs Those skilled in the art can adjust the embodiments described below according to requirements, such as changing the process sequence and / or including more or fewer steps than described herein. In addition, other elements may be added to the embodiments described below. For example, the description of "forming a second element on a first element" may include an embodiment in which the first element is in direct contact with the second element. It may include an embodiment in which there are other elements between the first element and the second element, so that the first element and the second element are not in direct contact, and the up-down relationship between the first element and the second element may vary with the operation of the device in different orientations Use and change.

In the following, according to some embodiments of the present invention, it is described that a superlattice buffer layer and a gradient buffer layer are provided between the substrate and the channel layer of the high electron mobility transistor device, so as to improve the productivity and improve the high electron mobility Efficiency and yield of crystal devices.

FIGS. 1-5 are schematic cross-sectional views illustrating various stages in manufacturing the high electron mobility transistor device 100 according to some embodiments. As shown in FIG. 1, the high electron mobility transistor device 100 includes a substrate 110. The substrate 110 may be a bulk semiconductor substrate or a composite substrate formed of different materials, and any substrate suitable for a semiconductor device may be used. Materials such as silicon, germanium, silicon carbide, gallium nitride, sapphire.

In some embodiments, a nucleation layer 120 is formed above the substrate 110 to mitigate a lattice difference between the substrate 110 and a film layer grown above. For example, the material of the nucleation layer 120 may include, for example, Aluminium Nitride (AlN), Aluminium Gallium Nitride (AlGaN), a similar material, or a combination thereof, and the thickness of the nucleation layer 120 It may be in the range of about 100 nanometers (nm) to about 1000 nm, for example About 200nm. The formation of the nucleation layer 120 may include a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), and Liquid Phase Epitaxy (LPE) ) Or other deposition techniques.

As shown in FIG. 2, in some embodiments, a superlattice buffer layer 130 is formed over the nucleation layer 120. The nucleation layer 120 is selective. In other embodiments, the nucleation layer 120 is not provided, and the superlattice buffer layer 130 is directly formed on the substrate. The formation of the superlattice buffer layer 130 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques.

x<1。如第2圖所示，第一組交替層132包含交錯排列的三層Al_xGa_(1-x)N層132a和三層AlN層132b，第二組交替層134包含交錯排列的三層Al_xGa_(1-x)N層134a和三層AlN層134b，以及第三組交替層136包含交錯排列的三層Al_xGa_(1-x)N層136a和三層AlN層136b。 The superlattice buffer layer 130 includes a plurality of sets of alternating layers. For example, in the embodiment shown in FIG. 2, the superlattice buffer layer 130 includes a first set of alternating layers 132, a second set of alternating layers 134, and a separation layer closest to the substrate. The third group of alternating layers 136 furthest from the base. Each set of alternating layers includes at least one Aluminium Nitride (AlN) layer and at least one Aluminium Gallium Nitride (Al _x Ga _(1-x) N) layer staggered, wherein aluminum nitride Gallium can be expressed as Al _x Ga _(1-x) N according to different aluminum content, where 0

x <1. As shown in FIG. 2, the first group of alternating layers 132 includes three layers of Al _x Ga _(1-x) N layers 132 a and three layers of AlN 132 _b , and the second group of alternating layers 134 includes three layers of Al _x Ga _(1-x) N layers 134a and three AlN layer 134b, and a third group 136 comprising alternating layers of three staggered _{Al x Ga (1-x)} N layers 136a and three AlN layer 136b.

Although in the embodiment of FIG. 2, the superlattice buffer layer 130 includes a first group of alternating layers 132, a second group of alternating layers 134, and a third group of alternating layers 136, and each of these alternating layers includes three groups of staggered Al _x Ga _(1-x) N layers and AlN layers, but the number of alternating layers and / or Al _x Ga _(1-x) N layers and AlN layers can be increased or decreased as required, and for different sets of alternating layers, Each may have a different number of staggered Al _x Ga _(1-x) N layers and AlN layers.

In each set of alternating layers, the x value of the Al _x Ga _(1-x) N layer is the same, and for different sets of alternating layers, the x value of the Al _x Ga _(1-x) N layer is different. That is, Al _x Ga _(1-x) N layers having the same aluminum content are the same set of alternating layers. Further, Al _x Ga set of alternating layers of the substrate adjacent the values of x _(1-x) N layer is greater than the base away from the other set of alternating layers of _{Al x Ga (1-x)} x N layer value. In other words, _(1-x) N layer has a maximum aluminum content and the aluminum content and away from the substrate with alternating layers of Al _x Ga substantially reduced from the substrate to the nearest set of alternating layers.

In addition, the value of x, that is, the aluminum content in the Al _x Ga _(1-x) N layer can be adjusted according to the needs. For example, in the embodiment of FIG. 2, the x value of the Al _x Ga _(1-x) N layer 132 a of the first set of alternating layers 132 is about 0.75, and the Al _x Ga _{(1 -x)} The x value of the N layer 134a is about 0.5, and the x value of the Al _x Ga _(1-x) N layer 136a of the third set of alternating layers 136 is about 0.25, so the Al _x Ga _(1-x) N layer 132a , 134a, and 136a may also be referred to as Al _0.75 Ga _0.25 N layer, Al _0.5 Ga _0.5 N layer, and Al _0.25 Ga _0.75 N layer, respectively.

According to some embodiments, in each set of alternating layers, the thickness of the Al _x Ga _(1-x) N layer is in a range of about 5 nm to about 100 nm, and the thickness of the AlN layer is in a range of about 1 nm to about 20 nm, such as Al _x Ga The thickness of the _(1-x) N layer is about 20 nm, and the thickness of the AlN layer is about 5 nm. In some embodiments, the ratio of the thickness of the Al _x Ga _(1-x) N layer to the thickness of the AlN layer is in a range of about 3 to about 10. Although shown in a first set of alternating layers 132 in FIG. 2, a second set of alternating layers 134 and 136 and a third set of alternating layers of the alternating layers of _{Al x Ga (1-x)} N layers 132a, 134a, 136a, and The AlN layers 132b, 134b, and 136b have the same thickness, but the present invention is not limited thereto. The thicknesses of each group of alternating layers and / or staggered Al _x Ga _(1-x) N layers and AlN layers can be adjusted according to requirements, and For different sets of alternating layers, there may be staggered Al _x Ga _(1-x) N layers and AlN layers each having a different thickness. In some embodiments, the thickness of the superlattice buffer layer 130 is in a range of about 0.05 micrometers (μm) to about 10 μm, such as about 0.2 μm.

y<1。鄰近基底的Al_yGa_(1-y)N層的y值大於遠離基底的另一組交替層的Al_yGa_(1-y)N層的y值。換句話說，離基底最近的一組交替層的Al_yGa_(1-y)N層具有最大的鋁含量，且鋁含量隨著交替層遠離基底而大致上減少。 As shown in FIG. 3, in some embodiments, a gradient buffer layer 140 is formed over the superlattice buffer layer 130. The formation of the gradient buffer layer 140 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. The graded buffer layer 140 includes a plurality of Aluminium Gallium Nitride (Al _y Ga _(1-y) N) layers, and may be represented by Al _y Ga _(1-y) N according to different aluminum contents, where 0

y <1. Adjacent to the substrate _{Al y Ga (1-y)} y N layer is greater than the value of the Al _y Ga substrate away from the other set of alternating layers _{(1-y) y} N layer value. In other words, the Al _y Ga _(1-y) N layer of the set of alternating layers closest to the substrate has the largest aluminum content, and the aluminum content decreases substantially as the alternating layers move away from the substrate.

In the embodiment shown in FIG. 3, the gradient buffer layer 140 includes a first Al _y Ga _(1-y) N layer 142 closest to the substrate, a second Al _y Ga _(1-y) N layer 144, and a separation layer. The third farthest Al _y Ga _(1-y) N layer 146. The number of Al _y Ga _(1-y) N layers can be increased or decreased according to demand, and the y value can be adjusted, that is, the aluminum content in the Al _y Ga _(1-y) N layer. For example, in the embodiment of FIG. 3, the y value of the first Al _y Ga _(1-y) N layer 142 is about 0.75, and the y value of the second Al _y Ga _(1-y) N layer 144 is about 0.75. About 0.5, the y value of the third Al _y Ga _(1-y) N layer 146 is about 0.25, so the first Al _y Ga _(1-y) N layer 142 and the second Al _y Ga _(1-y) N layer The 144 and the third Al _y Ga _(1-y) N layer 146 may also be referred to as an Al _0.75 Ga _0.25 N layer, an Al _0.5 Ga _0.5 N layer, and an Al _0.25 Ga _0.75 N layer, respectively.

According to some embodiments, the thickness of the Al _y Ga _(1-y) N layer is in a range of about 50 nm to about 500 nm, such as about 100 nm. Although FIG. 3 illustrates that the first Al _y Ga _(1-y) N layer 142, the second Al _y Ga _(1-y) N layer 144, and the third Al _y Ga _(1-y) N layer 146 have The thickness is the same, but the present invention is not limited thereto, and the thickness of each layer of Al _y Ga _(1-y) N layer can be adjusted according to requirements. In some embodiments, the thickness of the graded buffer layer 140 is in a range of about 0.1 μm to about 10 μm, such as about 0.3 μm.

Although FIG. 3 illustrates that the thickness of the superlattice buffer layer 130 is greater than the thickness of the graded buffer layer 140, the present invention is not limited thereto, and the respective thicknesses of the two can be adjusted according to requirements. In some embodiments, the total thickness of the superlattice buffer layer 130 and the graded buffer layer 140 is in a range of about 0.1 μm to about 10 μm, such as about 0.3 μm. In some embodiments, the ratio of the thickness of the superlattice buffer layer 130 to the thickness of the graded buffer layer 140 ranges from about 0.2 to about 2, such as about 0.75.

According to some embodiments of the present invention, a superlattice buffer layer 130 and a gradient buffer layer 140 are provided above the substrate 110 of the high electron mobility transistor device 100, which can alleviate the gap between the substrate 110 and other film layers formed thereon. Lattice differences can avoid defects such as bows or cracks caused by the lattice mismatch between the two when forming these films, so the yield of the high electron mobility transistor device 100 can be improved.

In addition, since the process time of the gradient buffer layer 140 is shorter than the process time of the superlattice buffer layer 130, for forming a buffer layer of the same thickness above the substrate 110, according to some embodiments of the present invention, a superlattice is formed. The buffer layer 130 and the buffer layer of the gradient buffer layer 140 can significantly reduce the process time and increase the production capacity of the high electron mobility transistor device 100 compared to the formation of only the superlattice buffer layer 130.

On the other hand, compared with the superlattice buffer layer 130, the gradient buffer layer 140 has a lower effect of alleviating lattice differences. For forming a buffer layer of the same thickness over the substrate, according to some embodiments of the present invention, a buffer layer including a superlattice buffer layer 130 and a gradient buffer layer 140 is provided. A film layer with better crystalline quality is formed over it, and therefore the thickness of the film layer such as the channel layer can be increased.

In addition, according to some embodiments of the present invention, a superlattice buffer layer 130 is disposed above the substrate 110 of the high electron mobility transistor device 100, and then a gradient buffer layer 140 is disposed. The superlattice buffer layer 130 below may be Preventing the differential rows in the substrate 110 from entering other film layers formed above the gradient buffer layer 140. Compared with the gradient buffer layer 140 and the superlattice buffer layer 130, the crystallization of the other film layers above can be further enhanced. quality.

Next, as shown in FIG. 4, a channel layer 150 is formed above the gradient buffer layer 140. In some embodiments, the material of the channel layer 150 may include a group III nitride, such as a group III-V compound semiconductor material. In some embodiments, the material of the channel layer 150 includes Gallium Nitride (GaN). The channel layer 150 may be doped or undoped according to requirements. The formation of the channel layer 150 may include a deposition process, such as organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. The thickness of the channel layer 150 may be selected according to requirements. For example, in some embodiments, the thickness of the channel layer 150 is in a range between about 10 nm and about 1000 nm, such as about 200 nm.

As shown in FIG. 5, according to some embodiments, a barrier layer 160 is formed over the channel layer 150. The formation of the barrier layer 160 may include a deposition process, such as organometallic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, or other deposition techniques. The thickness of the barrier layer 160 may be selected according to requirements. In some embodiments, the material of the barrier layer 160 may include a group III nitride, such as a group III-V compound semiconductor material. The barrier layer 160 may include a single-layer or multi-layer structure. For example, the barrier layer 160 includes AlN, AlGaN, AlInN, AlGaInN, similar materials, or a combination thereof. The barrier layer 160 may be doped or undoped according to requirements. The materials of the channel layer 150 and the barrier layer 160 are selected to generate a two-dimensional electron gas 152 at the interface between the two.

Then, according to some embodiments, a source 170, a gate 180, and a drain 190 are disposed above the barrier layer 160 to form a high electron mobility transistor device 100. The source 170, gate 180, and drain 190 can be formed using any suitable material, process, and sequence, and the pitch and position of the components can be adjusted as required. As shown in FIG. 5, according to some embodiments, the source 170 and the drain 190 pass through the barrier layer 160 into the channel layer 150, and the gate 180 is located on the surface of the barrier layer 160, but the present invention is not limited thereto , Can be a variety of other arrangements or configurations. For example, a p-type doped gallium nitride (p-GaN) layer may be provided between the gate 180 and the barrier layer 160 so that the gate 180 does not contact the barrier layer 160, and a high electron mobility transistor is formed. The device 100 is an enhancement mode (E-mode) device; or a p-doped gallium nitride (p-GaN) layer is not provided between the gate 180 and the barrier layer 160, and a high electron mobility is formed. The transistor device 100 is a depletion mode (D-mode) device.

Generally speaking, in the formation of high electron mobility transistor devices, In the track layer, due to the lattice difference between the channel layer and the substrate, defects such as cracks or warpage are easily formed in the channel layer. These defects will become serious as the thickness of the channel layer increases, affecting the performance of the high electron mobility transistor device, so the thickness of the channel layer is limited. In some embodiments of the present invention, a superlattice buffer layer and a gradient buffer layer are provided between the substrate and the channel layer of the high electron mobility transistor device, and the aluminum content in the superlattice buffer layer and the gradient buffer layer is adjusted. It can alleviate the lattice difference between the channel layer and the substrate formed above, reduce the defects caused thereby, improve the crystalline quality of the channel layer, and can further increase the thickness of the channel layer, improving the efficiency and goodness of the high electron mobility transistor device rate.

In addition, compared to the superlattice buffer layer, the process time of the gradient buffer layer is shorter, but the effect of avoiding defects in the channel layer is not as good as the superlattice buffer layer. Therefore, for forming a buffer layer of the same thickness, according to some embodiments of the present invention, a buffer layer including a superlattice buffer layer and a gradient buffer layer is provided above the substrate, as compared with only a superlattice buffer layer, Significantly shorten the process time, so the productivity of high electron mobility transistor devices can be improved; on the other hand, compared with only the buffer layers with gradients, a channel layer with better crystal quality can be formed above these buffer layers, improving high electrons Yield of mobility transistor device.

In addition, according to some embodiments of the present invention, a superlattice buffer layer is provided above the substrate of the high-electron mobility transistor device, and then a gradient buffer layer is provided, which can effectively prevent the differential rows in the substrate from entering the channel area, and further improve The crystalline quality of the channel layer. Therefore, some embodiments of the present invention can improve the efficiency and efficiency of the high electron mobility transistor device while increasing the production capacity. Yield.

Although the present invention has been described above with a plurality of embodiments, these embodiments are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should understand that they can make various changes, substitutions and replacements based on the embodiments of the present invention to achieve the same purpose as the multiple embodiments described herein. And / or advantages. Those skilled in the art to which the present invention pertains can also understand that such modifications or designs do not depart from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (20)

A high electron mobility transistor (HEMT) device includes: a substrate; a superlattice buffer layer disposed above the substrate, wherein the superlattice buffer layer includes a plurality of alternating layers, and each group of alternating layers includes a staggered arrangement At least one A1N layer and at least one Al _x Ga _(1-x) N layer, where 0 x <1, and for different sets of alternating layers, the Al _x Ga _(1-x) N layers have different x values, where the Al _x Ga _{(1-x )} The x value of the N layer is greater than the x value of the Al _x Ga _(1-x) N layers of the set of alternating layers far from the substrate; a gradient buffer layer is disposed above the substrate, wherein the gradient buffer layer Including multiple Al _y Ga _(1-y) N layers, where 0 y <1; and a channel layer disposed above the gradient buffer layer. The high electron mobility transistor device according to item 1 of the scope of the patent application, wherein in each set of alternating layers, the Al _x Ga _(1-x) N layers have the same x value. The high electron mobility transistor device according to item 1 of the scope of the patent application, wherein a ratio of a thickness of the superlattice buffer layer to a thickness of the graded buffer layer is in a range of 0.2 to 2. The high electron mobility transistor device described in item 1 of the patent application scope, wherein the AlN layer of the superlattice buffer layer directly contacts the Al _y Ga _(1-y) N layer of the graded buffer layer. The high electron mobility transistor device according to item 1 of the scope of patent application, wherein in each set of alternating layers, the thickness of the AlN layer is in a range of 1 nm to 20 nm, and the thickness of the Al _x Ga _(lx) N layer is In the range of 5nm to 100nm. The high electron mobility transistor device described in item 1 of the patent application range, wherein a ratio of a thickness of the Al _x Ga _(1-x) N layer to a thickness of the AlN layer is in a range of 3 to 10. The high electron mobility transistor device described in item 1 of the patent application range, wherein the thickness of each of the Al _y Ga _(1-y) N layers is in a range of 50 nm to 500 nm. The high electron mobility transistor device described in item 1 of the scope of patent application, wherein the y value of the Al _y Ga _(1-y) N layer adjacent to the substrate is greater than the Al _y Ga _{(1-y )} The y value of the N layer. The high-electron-mobility transistor device according to item 1 of the patent application scope, wherein the gradient buffer layer is disposed above the superlattice buffer layer. The high-electron-mobility transistor device described in item 1 of the patent application scope further includes a nucleation layer disposed between the substrate and the superlattice buffer layer, wherein the nucleation layer includes aluminum nitride (AlN ), Aluminum gallium nitride (AlGaN), or a combination thereof. The high electron mobility transistor device described in item 10 of the scope of patent application, further includes: a barrier layer disposed above the channel layer; and a source, a drain, and a gate disposed on the resistor Above the barrier. A method for manufacturing a high electron mobility transistor device includes: forming a substrate; forming a superlattice buffer layer on the substrate, wherein the superlattice buffer layer comprises a plurality of alternating layers, and each group of alternating layers includes a staggered arrangement At least one AlN layer and at least one Al _x Ga _(1-x) N layer, where 0 x <1, and for different sets of alternating layers, the Al _x Ga _(1-x) N layers have different x values, where the Al _x Ga _{(1-x )} The x value of the N layer is greater than the x value of the Al _x Ga _(1-x) N layers of the set of alternating layers far from the substrate; a gradient buffer layer is formed above the substrate, wherein the gradient buffer layer includes A plurality of Al _y Ga _(1-y) N layers, where 0 y <1; and a channel layer is formed above the gradient buffer layer. The method for manufacturing a high electron mobility transistor device according to item 12 of the scope of the patent application, wherein in each set of alternating layers, the Al _x Ga _(1-x) N layers have the same x value. The method for manufacturing a high electron mobility transistor device according to item 12 of the application, wherein the ratio of the thickness of the superlattice buffer layer to the thickness of the graded buffer layer is in the range of 0.2 to 2. The method for manufacturing a high-electron-mobility transistor device according to item 12 of the application, wherein the AlN layer of the superlattice buffer layer directly contacts the Al _y Ga _(1-y) N of the graded buffer layer. Floor. The method for manufacturing a high electron mobility transistor device according to item 12 of the scope of patent application, wherein in each set of alternating layers, the thickness of the AlN layer is in a range of 1 nm to 20 nm, and the Al _x Ga _(1-x) The thickness of the N layer is in a range of 5 nm to 100 nm, and the ratio of the thickness of the Al _x Ga _(1-x) N layer to the thickness of the AlN layer is in a range of 3 to 10. The method for manufacturing a high electron mobility transistor device according to item 12 of the scope of the patent application, wherein the thickness of each of the Al _y Ga _(1-y) N layers is in a range of 50 nm to 500 nm. The method for manufacturing a high electron mobility transistor device according to item 12 of the scope of the patent application, wherein the y value of the Al _y Ga _(1-y) N layer adjacent to the substrate is greater than the Al _y Ga _{( 1-y)} The y value of the N layer. The method for manufacturing a high-electron-mobility transistor device according to item 12 of the application, wherein the gradient buffer layer is formed above the superlattice buffer layer. The method for manufacturing a high-electron-mobility transistor device according to item 12 of the patent application scope, further comprising forming a nucleation layer between the substrate and the superlattice buffer layer, wherein the nucleation layer includes aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination thereof.