TW202146921A - Multi-channel antenna chip test system and method - Google Patents

Abstract

A multi-channel antenna chip test system is provided. First internal test paths of a multi-channel antenna chip are coupled to 2N-1-th connection pads through antenna switches and are coupled to 2N-th connection pads. Second internal test path of the multi-channel antenna chip are coupled to the 2N-th connection pads through the antenna switches and are coupled to the 2N+1-th connection pads. Under a first test mode, a first connect pad receives a test signal to be transmitted through the connection pads, the first internal test paths and external test paths such that a last connection pad generates a test result signal. Under a second test mode, the last connection pad receives the test signal to be transmitted through the connection pads, the second internal test paths and external test paths such that the fist connection pad generates the test result signal.

Description

Multi-channel antenna chip testing system and method

The present invention relates to wafer testing technology, in particular to a multi-channel antenna wafer testing system and method.

Wireless communication is the focus of the development of network technology. An electronic device with wireless communication function must be equipped with an antenna to transmit and receive wireless signals, and a signal processing chip that can be electrically coupled to the antenna processes the signals transmitted and received by the antenna.

As the number of channels on the chip supporting the antenna increases, the chip must be provided with more connection pads on the package structure to be electrically coupled to the antenna. In order to ensure that the connection pads can work properly, each connection pad needs to be tested by, for example, but not limited to, a testing machine. However, as the number of connection pads increases, more time and hardware costs are required to test these connection pads. If a more efficient and reliable test architecture or method cannot be provided, the time cost and hardware cost will not be reduced.

In view of the problems of the prior art, one object of the present invention is to provide a multi-channel antenna chip testing system and method to improve the prior art.

One objective of the present invention is to provide a multi-channel antenna chip testing system and method, which can greatly reduce the cost of pin setting required by a testing machine by setting internal and external test paths.

The present invention includes a multi-channel antenna chip testing system, an embodiment of which includes a multi-channel antenna chip and a plurality of external test paths. The multi-channel antenna chip includes: a plurality of antenna switching switches, a plurality of connection pads, a plurality of first internal test paths and a plurality of second internal test paths. The connection pads each include a first end and a second end, the first end is electrically coupled to the signal processing end through a corresponding antenna switch, and the second end is electrically coupled to an external antenna. The first internal test paths each include a first end and a second end, the first end is electrically coupled to the 2N-1th connection pads through a corresponding antenna switch, and the second end is not electrically coupled through the antenna switch at the 2Nth connection pad, where N is a positive integer. Each of the second internal test paths includes a first end and a second end. The first end is electrically coupled to the 2Nth connection pad through a corresponding antenna switch, and the second end is electrically coupled to the 2Nth connection pad without the antenna switch. 2N-1 connection pads. The external test paths each include a first end and a second end, the first end is electrically coupled to the 2Nth connection pad, and the second end is electrically coupled to the 2N+1th connection pad; wherein, in the first test mode, The first connection pad is configured to receive the first test signal, and after passing through the connection pad, the first inner test path and the outer test path, the last connection pad generates the first test result signal. In the second test mode, the last connection pad is configured to receive the second test signal, and after passing through the connection pad, the second inner test path and the outer test path, the first connection pad generates a second test result signal.

The present invention further includes a method for testing a multi-channel antenna chip, an embodiment of which includes the following steps: providing a multi-channel system including a plurality of antenna switches, a plurality of connection pads, a plurality of first internal test paths and a plurality of second internal test paths The channel antenna chip, wherein the first end of each connection pad is electrically coupled to the signal processing end through the corresponding antenna switch, and the second end is used to be electrically coupled to the external antenna; in the first test mode, the first Each connection pad receives the first test signal, and after passing through the connection pad, the first inner test path and the plurality of outer test paths, the last connection pad generates a first test result signal, wherein the first end of each first inner test path is The 2N-1th connection pad is electrically coupled through a corresponding antenna switch, the second end is electrically coupled to the 2Nth connection pad through the antenna switch, and the first end of each external test path is electrically coupled connected to the 2Nth connection pad, and the second terminal is electrically coupled to the 2N+1th connection pad; in the second test mode, the last connection pad receives the second test signal to pass through the connection pad and the second internal test path After the external test path is connected, a second test result signal is generated by the first connection pad, wherein the first end of each second internal test path is electrically coupled to the 2Nth connection pad through a corresponding antenna switch, and the second The terminal is electrically coupled to the 2N-1th connection pad through the antenna switch.

Regarding the features, implementation and effects of this case, a preferred embodiment is described in detail as follows in conjunction with the drawings.

One objective of the present invention is to provide a multi-channel antenna chip testing system and method, which can greatly reduce the cost of pin setting required by a testing machine by setting internal and external test paths.

Please refer to FIG. 1A and FIG. 1B at the same time. 1A and FIG. 1B are block diagrams of a multi-channel antenna chip testing system 100 according to an embodiment of the present invention, respectively. 1A and 1B are actually the same multi-channel antenna chip testing system 100 . However, for ease of viewing, a portion of the components included in the multi-channel antenna wafer test system 100 are shown in FIG. 1A , while another portion of the components included in the multi-channel antenna wafer test system 100 are shown in FIG. 1B .

The multi-channel antenna wafer test system 100 is configured to test the multi-channel antenna wafer 110 . The multi-channel antenna chip 110 is used to electrically couple a plurality of external antennas ANT ₁ -ANT _{N during operation} , wherein N is a positive integer. After the multi-channel antenna wafer 110 may be processed within the data, through an external antenna ANT ₁ -ANT _N sends data to the wireless signal out of the way. On the other hand, the antenna chip 110 can also receive data in the form of wireless signals _{through the external antennas ANT 1} -ANT _{N, and then process the data internally.}

The multi-channel antenna chip testing system 100 includes: a multi-channel antenna chip 110 and a plurality of external test paths EP ₁ -EP _N/2-1 .

The multi-channel antenna chip 110 includes: a plurality of antenna switching switches SW ₁ -SW _N , a plurality of connection pads PAD ₁ -PAD _N , a plurality of first internal test paths IPA ₁ -IPA _N/2 and a plurality of second internal test paths IPB ₁ -IPB _N/2 .

The connection pads PAD ₁ -PAD _N each include a first end and a second end. The first end is electrically coupled to the signal processing end 120 through one of the corresponding antenna switching switches SW ₁ -SW _N , and the second end is electrically coupled to the external antennas ANT ₁ -ANT _N .

Taking the connection pad PAD ₁ as an example, the first end thereof is _{electrically coupled to the signal processing end 120 through the antenna switch SW 1} , and the second end is electrically coupled to the external antenna ANT ₁ . Taking the connection pad PAD ₂ as an example, its first end is _{electrically coupled to the signal processing end 120 through the antenna switch SW 2} , and the second end is electrically coupled to the external antenna ANT ₂ . By analogy, for the connection pad PAD _N , its first end is _{electrically coupled to the signal processing end 120 through the antenna switch SW N} , and the second end is electrically coupled to the external antenna ANT _N .

It should be noted that, during the test, the second ends of the _{connection pads PAD 1} -PAD _N do not have to be electrically coupled to the _{external antennas ANT 1} -ANT _N. More specifically, the second connection pads PAD ₁ -PAD _N end can be tested in the absence of _{1 -ANT N} electrically coupled to an external antenna ANT.

In one embodiment, the signal processing end 120 may selectively include, for example, but not limited to, an amplifier 130 , an analog-to-digital converter 140 (marked as D/A in FIG. 1 ), a bus bar 150 and a processor 160 .

With the above-described mechanism, data processor 160 may be processed for digital to analog conversion, and amplified by the transmit bus 150 and digital to analog converter 140 and an amplifier 130, and then transmitted through an antenna switch SW ₁ -SW _N selection appropriate path, the data from at least one external antenna ANT ₁ -ANT _N sent out in the form of the wireless signal. On the other hand, the information can come in the form of wireless signals received from at least one of an external antenna ANT ₁ -ANT _N, through amplifier 130 and analog to digital converter 140 and amplifies the analog-to-digital conversion, and then via the bus 150 is passed to processor 160 .

Therefore, end 120 may be signal processing by the above-mentioned mechanism, through an antenna switch SW ₁ -SW _N select an appropriate external antenna ANT ₁ -ANT _N for transmitting and receiving data.

As shown in FIG. 1A , the first internal test paths IPA ₁ -IPA _N/2 each include a first end and a second end, and the first end is electrically coupled to the 2N-1th connection pad through a corresponding antenna switch. , the second end is electrically coupled to the 2Nth connection pad through the antenna switch.

For example, a first end of a first internal test path ₁ IPA switching switch SW ₁ through the antenna is electrically coupled to the PAD connection pads _1, a second end electrically coupled directly to the connection pads PAD _2. A first end of a first internal test path IPA ₂ is switched through the switch SW ₃ is electrically connected to an antenna coupled to pad PAD _3, a second end electrically coupled directly to the connection pads PAD _4. So, a first end of a first internal test path IPA _{N / 2} through the switch SW ₁ is electrically coupled to the antenna connection pads PAD _N-1, a second end electrically coupled directly to the connection pads PAD _N.

As shown in FIG. 1B , each of the second internal test paths IPB ₁ -IPB _N/2 includes a first end and a second end. The first end is electrically coupled to the 2Nth connection pad through a corresponding antenna switch. The two terminals are electrically coupled to the 2N-1th connection pad through the antenna switch.

For example, the second end of a first internal test path IPB changeover switch SW ₁ through the antenna ₂ is electrically coupled to the PAD connection pad _2, a second end electrically coupled directly to the connection pads PAD _1. IPB second internal test path of the first end ₂ of the switch SW ₄ is electrically coupled to the antenna through connection pads PAD _4, a second end electrically coupled directly to the connection pads PAD _3. So, the second internal test path IPB _{N / 2} first end of the switch SW _N is electrically coupled to the antenna through connection pads PAD _N, a second terminal electrically coupled directly to the connection pads PAD _N-1.

The external test paths EP ₁ -EP _N/2-1 each include a first end and a second end, the first end is electrically coupled to the 2Nth connection pad, and the second end is electrically coupled to the 2N+1th connection pad.

For example, the first end of the external test path EP ₁ is electrically coupled to the connection pad PAD ₂ , and the second end is electrically coupled to the connection pad PAD ₃ . The first end of the external test path EP ₂ is electrically coupled to the connection pad PAD ₄ , and the second end is electrically coupled to the connection pad PAD ₅ . By analogy, the first end of the external test path EP _N/2-1 is electrically coupled to the connection pad PAD _N-1 , and the second end is electrically coupled to the connection pad PAD _N .

In one embodiment, the above-mentioned connection pads PAD ₁ -PAD _N are disposed to be exposed outside the package structure of the multi-channel antenna chip 110 , but outside the external test paths EP ₁ -EP _N/2-1 through the above-mentioned way to electrically couple the connection pads. In one embodiment, the external test paths EP ₁ -EP _N/2-1 are disposed on a test fixture (not shown), so that after the multi-channel antenna chip 110 and the test fixture are electrically coupled, The connection pads are electrically coupled in the manner described above.

As shown in FIG. 1A , in the first test mode, the first connection pad PAD _{1 is} configured to receive the first test signal IS1 . In one embodiment, the first test signal IS1 is generated by a test machine (not shown). In more detail, the first connection pad PAD ₁ can be electrically coupled to the test machine, for example, but not limited to, through the aforementioned test fixture to receive the first test signal IS1 from the test machine.

Further, the first test signal IS1 can be passed through a circuit including, for example, but not limited to, the connection pad PAD ₁ , the antenna switch SW ₁ , the first inner test path IPA ₁ , the connection pad PAD ₂ , the outer test path EP ₁ , and the connection pad PAD ₃ , antenna switch SW ₃ , first internal test path IPA ₂ , connection pad PAD ₄ , external test path EP ₂ , connection pad PAD ₅ , ... antenna switch SWN-1 , first internal test path IPA _N/2 , connection Path for pad PAD _N , delivered to connection pad PAD _N . The connection pads, the antenna switch, the first internal test path, and the external test path included in the above paths are shown as thick frames in FIG. 1A .

The last connection pad PADN will generate the first test result signal OS1. In one embodiment, the first test result signal OS1 is received by the test machine. More specifically, the last connection pad PAD _N can be electrically coupled to the testing machine, for example, but not limited to, through the aforementioned test fixture, so that the testing machine can receive the first test result signal OS1.

As shown in FIG. 1B , in the second test mode, the last connection pad PAD _{N is} configured to receive the second test signal IS2 . In one embodiment, the second test signal IS2 is generated by a test machine (not shown). In more detail, the last connection pad PAD _N can be electrically coupled to the testing machine, for example, but not limited to, through the aforementioned test fixture to receive the second test signal IS2 from the testing machine.

Further, the second test signal IS2 can be passed through, for example, but not limited to, the connection pad PAD _N , the antenna switch SW _N , the second inner test path IPA _N/2 , the connection pad PAD _N-1 , and the outer test path EP _{N/ 2-1} , connection pad PAD _N-2 , antenna switch SW _N-2 , second internal test path IPA _N/2-1 , connection pad PAD _N-3 , external test path EP _N/2-2 , connection pad PAD _N-4 , ... antenna switch SW ₂ , the first internal test path IPA ₁ , the path of the connection pad PAD ₁ , are transmitted to the connection pad PAD ₁ . The connection pads, the antenna switch, the second internal test path, and the external test path included in the above paths are shown as thick frames in FIG. 1B .

A first connection pad PAD ₁ will generate a second test result signal OS2. In one embodiment, the second test result signal OS2 is received by the test machine. In more detail, the first connection pad PAD ₁ can be electrically coupled to the test machine, for example, but not limited to, through the aforementioned test fixture, so that the test machine can receive the second test result signal OS2.

Therefore, in the above manner, the multi-channel antenna chip testing system 100 can observe the signal generated _{by the last connection pad PAD N} after receiving the first test signal IS1 _{through the first connection pad PAD 1 in the first test mode.} Whether the value of the first test result signal OS1 is the same as that of the first test signal IS1, and in the second test mode, _{after receiving the second test signal IS2 through the last connection pad PAD N} , observe whether the first connection pad PAD ₁ Whether the generated second test result signal OS2 is the same as the value of the first test signal IS1, so as to quickly determine whether the multiple channels formed _{by the connection pads PAD 1} -PAD _N and the antenna switches SW ₁ -SW _{N can work normally} .

Wherein, in the first test mode, the first internal test paths IPA ₁ -IPA _{N/2 are} electrically coupled to half of the antenna switching switches SW ₁ -SW _N , and in the second test mode, the second internal test paths IPB ₁ -IPB _{N/2 is} electrically coupled to the other half of the antenna switching switches SW ₁ -SW _N , so the first and second test modes will test each half of the channels.

Please refer to FIG. 2A and FIG. 2B at the same time. 2A and 2B are block diagrams of a multi-channel antenna chip testing system 200 according to an embodiment of the present invention. 2A and 2B are actually the same multi-channel antenna chip testing system 200 . However, for ease of viewing, a portion of the components included in the multi-channel antenna wafer test system 200 are shown in FIG. 2A, while another portion of the components included in the multi-channel antenna wafer test system 200 are shown in FIG. 2B.

The multi-channel antenna chip testing system 200 shown in FIGS. 2A and 2B is similar to the multi-channel antenna chip testing system 100 shown in FIGS. 1A and 1B , and also includes: the multi-channel antenna chip 110 and a plurality of external test paths EP ₁ -EP _N/2-1 . In FIGS. 2A and 2B , the signal processing end 120 and the external antennas ANT ₁ -ANT _{N that} can be electrically coupled to the multi-channel antenna chip 110 are omitted and not shown.

As shown in FIG. 2A , the multi-channel antenna chip 110 in the multi-channel antenna chip testing system 200 in this embodiment has first test registers RA ₁ -RA _N/2 , which are respectively included in the first internal test path IPA _1- IPA _N/2 on. As shown in FIG. 2B , the multi-channel antenna chip 110 further has second test registers RB ₁ -RB _N/2 , which are respectively included in the second internal test paths IPB ₁ -IPB _N/2 .

Since the first internal test paths IPA ₁ -IPA _N/2 and the second internal test paths IPB ₁ -IPB _N/2 respectively include the first test registers RA ₁ -RA _N/2 and the second test registers RA 1 -RA N/2 that can temporarily store test data The test registers RB ₁ -RB _N/2 , so the multi-channel antenna chip testing system 100 can pass the first test signal IS1 and the second test signal IS2 to generate the first test result signal OS1 and the second test result signal OS1 after the registers are shifted. 2. Test the result signal OS2, observe whether the channel corresponding to each timing is working normally. Therefore, compared with the embodiment of FIG. 1 to quickly determine whether the overall connection pads PAD ₁ -PAD _N work normally, the embodiment of FIG. 2 can individually determine whether each of the connection pads PAD ₁ -PAD _N works normally.

Please refer to FIG. 3A and FIG. 3B . 3A and 3B are block diagrams of a multi-channel antenna chip testing system 300 according to an embodiment of the present invention. 3A and 3B are actually the same multi-channel antenna chip testing system 300 . However, for ease of viewing, a portion of the components included in the multi-channel antenna wafer test system 300 are shown in FIG. 3A, while another portion of the components included in the multi-channel antenna wafer test system 300 are shown in FIG. 3B.

The multi-channel antenna chip testing system 300 shown in FIGS. 3A and 3B is similar to the multi-channel antenna chip testing systems 100 and 200 shown in FIGS. 1A , 1B, 2A and 2B, and also includes: a multi-channel antenna The wafer 110 and a plurality of external test paths EP ₁ -EP _N/2-1 . In FIGS. 3A and 3B , the signal processing end 120 and the external antennas ANT ₁ -ANT _{N that} can be electrically coupled to the multi-channel antenna chip 110 are omitted and not shown.

As shown in FIG. 3A , the multi-channel antenna chip 110 in the multi-channel antenna chip testing system 300 in this embodiment has multiplexers MUA ₁ -MUA _N/2 , first sub-paths PAA ₁ -PAA _N/2 , The second sub-path PBA ₁ -PBA _N/2 and the third sub-path PCA ₁ -PCA _N/2 .

Each group of multiplexers, the first sub-path, the second sub-path, and the third sub-path are correspondingly included in a first internal test path, and for a first internal test path, the multiplexer includes two selection inputs terminal and output terminal, its first sub-path is electrically coupled to one of the corresponding antenna switch and one of the two selection input terminals, its second sub-path includes a first test register, the first test register It is electrically coupled to a corresponding antenna switch and the other of the two selection input terminals. The third sub-path is electrically coupled to the output end of the multiplexer and the 2Nth connection pad.

For example, the multiplexer MUA ₁ , the first sub-path PAA ₁ , the second sub-path PBA ₁ and the third sub-path PCA _{1 are} correspondingly included in the first inner test path IPA ₁ . The first sub-path PAA _{1 is} electrically coupled to the antenna switch SW _{1 and one} of the two selection input terminals of the multiplexer MUA 1 . The second sub-path PBA ₁ includes a first test register RA ₁ , and the first test register RA _{1 is} electrically coupled to the corresponding antenna switch SW ₁ and the other of the two selection input terminals of the _{multiplexer MUA 1} . The third sub-path is electrically coupled to the output end of the _{multiplexer MUA 1 and the connection pad PAD 2} .

By analogy, the multiplexer MUA _N/2 , the first sub-path PAA _N/2 , the second sub-path PBA _N/2 and the third sub-path PCA _{1 are} correspondingly included in the first inner test path IPA _N/2 . The first sub-path PAA _{N/2 is} electrically coupled to the antenna switch SW _N-1 and one of the two selection input terminals of the multiplexer MUA _N/2. The second sub-path PBA _N/2 includes a first test register RA _N/2 , and the first test register RA _{N/2 is} electrically coupled to the corresponding antenna switch SW _N-1 and the multiplexer MUA _{N The second} of /2 selects the other input. The third sub-path is electrically coupled to the output end of the _{multiplexer MUA N/2 and the connection pad PAD N} .

Similarly, as shown in FIG. 3B, the multi-channel antenna die 110 has multiplexers MUB ₁ -MUB _N/2 , first sub-paths PAB ₁ -PAB _N/2 , second sub-paths PBB ₁ -PBB _N/2 and The third subpath PCB ₁ -PCB _N/2 .

Each group of multiplexers, the first sub-path, the second sub-path, and the third sub-path are correspondingly included in a first internal test path, and for a first internal test path, the multiplexer includes two selection inputs terminal and output terminal, its first sub-path is electrically coupled to one of the corresponding antenna switch and one of the two selection input terminals, its second sub-path includes a first test register, the first test register It is electrically coupled to a corresponding antenna switch and the other of the two selection input terminals. The third sub-path is electrically coupled to the output end of the multiplexer and the 2N-1th connection pad.

For example, the multiplexer MUB ₁ , the first sub-path PAB ₁ , the second sub-path PBB ₁ and the third sub-path PCB _{1 are} correspondingly included in the second internal test path IPB ₁ . The first sub-path PAB _{1 is} electrically coupled to the antenna switch SW _{2 and one} of the two selection input terminals of the multiplexer MUB 1 . The second sub-path PBB ₁ includes a first test register RB ₁ , and the first test register RB _{1 is} electrically coupled to the corresponding antenna switch SW ₂ and the other of the two selection input terminals of the _{multiplexer MUB 1} . The third sub-path is electrically coupled to the output end of the _{multiplexer MUB 1 and the connection pad PAD 1} .

By analogy, the multiplexer MUB _N/2 , the first sub-path PAB _N/2 , the second sub-path PBB _N/2 and the third sub-path PCB _{1 are} correspondingly included in the second inner test path IPB _N/2 . The first sub-path PAB _{N/2 is} electrically coupled to the antenna switch SW _N and one of the two selection input terminals of the multiplexer MUA _N/2. The second sub-path PBA _N/2 includes a first test register RB _N/2 , and the first test register RB _{N/2 is} electrically coupled to the corresponding antenna switch SW _N and the multiplexer MUB _N/2 The second selects the input of the other. The third sub-path is electrically coupled to the output end of the _{multiplexer MUB N/2 and the connection pad PAD N-1} .

Thus, in a first test mode, each of the first internal test path multiplexer IPA _{1 -IPA N / 2} of the MUA ₁ -MUA _{N / 2} can be selected for each sub-path through the first PAA ₁ -PAA _{N / 2} test, and in the second test mode, each of the second internal test path IPB multiplexer _{1 -IPB N / 2} of MUB ₁ -MUB _{N / 2} may both be selected through the first sub-path PAB ₁ -PAB _{N / 2} carry out testing. In this way, the rapid test mechanism of FIG. 1 can be achieved.

On the other hand, in the first test mode, the internal test path of each first multiplexer IPA _{1 -IPA N / 2} of the MUA ₁ -MUA _{N / 2} may both be selected through the second sub-path PBA _{1 -PBA N / 2} were tested, and in the second test mode, each of the second internal test path IPB multiplexer _{1 -IPB N / 2} of MUB ₁ -MUB _{N / 2} may each selected sub-path through the second PBB ₁ -PBB _N/2 for testing. In this way, the individual testing mechanism of FIG. 2 can be achieved.

To sum up the above, the multi-channel antenna chip testing system in the above-mentioned embodiment can set the internal test path and the external test path, so that the test machine only needs to transmit the test signal and the test signal through the first connection pad and the last connection pad. receive, greatly reducing the cost of the required pin setup. Further, with the arrangement of the paths that do not include registers and include registers, the multi-channel antenna chip testing system can perform fast overall connection pad testing or individual connection pad testing.

Please refer to Figure 4. FIG. 4 is a flowchart of a method 400 for testing a multi-channel antenna chip according to an embodiment of the present invention.

In addition to the aforementioned apparatus, the present invention further discloses a multi-channel antenna chip testing method 400, which is applied to, for example, but not limited to, the multi-channel antenna chip testing systems 100, 200 and 300 shown in FIGS. 1 , 2 and 3 . An embodiment of a multi-channel antenna chip testing method 400 is shown in FIG. 4 , and includes the following steps:

S410: Provide a multi-channel antenna including antenna switch switches SW ₁ -SW _N , connection pads PAD ₁ -PAD _N , first internal test paths IPA ₁ -IPA _N/2 and second internal test paths IPB ₁ -IPB _N/2 wafer 110 .

S420: In the first test mode, enable the first connection pad PAD _{1 to} receive the first test signal IS1 to pass through the connection pads PAD ₁ -PAD _N , the first internal test paths IPA ₁ -IPA _N/2 and the external test path After EP ₁ -EP _N/2-1 , the first test result signal OS1 is generated by the last connection pad PAD _N.

S430: the second test mode to make a connection pad PAD _N last receiving a second test signal IS2, to pass through the connection pads PAD ₁ -PAD _N, a second internal test path IPB ₁ -IPB _{N / 2} and an external test path EP after ₁ -EP _{N / 2-1,} by the first connection pad pAD ₁ generating a second test result signal OS2.

It should be noted that the above-mentioned embodiment is only an example. In other embodiments, those skilled in the art can make changes without departing from the spirit of the present invention.

To sum up the above, the multi-channel antenna chip testing system and method of the present invention can greatly reduce the cost of setting pins required by the testing machine by setting the internal test path and the external test path.

Although the embodiments of the present case are as described above, these embodiments are not intended to limit the present case. Those with ordinary knowledge in the technical field can make changes to the technical features of the present case according to the explicit or implicit contents of the present case. All may belong to the scope of patent protection sought in this case. In other words, the scope of patent protection in this case must be determined by the scope of the patent application in this specification.

100, 200, 300: Multi-channel antenna chip test system 110: Multi-channel antenna chip 120: Signal processing end 130: Amplifier 140: Analog and digital converter 150: Bus bar 160: Processor ANT ₁ -ANT _N : External antenna EP ₁ -EP _N/2-1 : External test path IPA _{1- IPA N/2} : First internal test path IPB _{1- IPB N/2} : Second internal test path IS1: First test signal IS2: Second test signal MUA ₁ -MUA _N/2 , MUB ₁ -MUB _N/2 : Multiplexer OS1 : The first test result signal OS2 : The second test result signal PAA ₁ -PAA _N/2 , PAB ₁ -PAB _N/2 : the first test result signal a sub-path pAD ₁ -PAD _N: connection pad _{PBA 1 -PBA N / 2, PBB} 1 -PBB N / 2: the second sub-path _{PCA 1 -PCA N / 2, PCB} 1 -PCB N / 2: third sub Path RA ₁ -RA _N/2 : first test register RB ₁ -RB _N/2 : second test register SW ₁ -SW _N : antenna switch S410~S430: step

[FIG. 1A] and [FIG. 1B] respectively show a block diagram of a multi-channel antenna chip testing system according to an embodiment of the present invention; [FIG. 2A] and [FIG. 2B] show a block diagram of a multi-channel antenna chip testing system according to an embodiment of the present invention; [FIG. 3A] and [FIG. 3B] show a block diagram of a multi-channel antenna chip testing system according to an embodiment of the present invention; and [FIG. 4] A flow chart showing a method for testing a multi-channel antenna chip in an embodiment of the present invention.

100: Multi-channel antenna chip test system

110: Multi-channel antenna chip

120: Signal processing terminal

130: Amplifier

140: Analog and Digital Converters

150: Busbar

160: Processor

ANT ₁ -ANT _N : External Antenna

EP ₁ -EP _N/2-1 : External Test Path

IPA ₁ -IPA _N/2 : First Internal Test Path

IS1: The first test signal

OS1: The first test result signal

PAD ₁ -PAD _N : Connection pads

SW ₁ -SW _N : Antenna switch

Claims (14)

A multi-channel antenna chip testing system, comprising: A multi-channel antenna chip, comprising: A plurality of antenna switches; A plurality of connection pads each includes a first end and a second end, the first end is electrically coupled to a signal processing end through a corresponding one of the antenna switches, and the second end is used for electrical coupling on an external antenna; A plurality of first internal test paths each include a first end and a second end, the first end is electrically coupled to the 2N-1th connection pads through one of the corresponding antenna switches, and the first end The two ends are not electrically coupled to the 2Nth connection pads through the antenna switches, wherein N is a positive integer; and A plurality of second internal test paths each include a first end and a second end, the first end is electrically coupled to the 2Nth connection pads through one of the corresponding antenna switches, the second end not electrically coupled to the 2N-1th connection pads through the antenna switches; and A plurality of external test paths each includes a first end and a second end, the first end is electrically coupled to the 2Nth connection pads, and the second end is electrically coupled to the 2N+1th connection pads pad; Wherein, in a first test mode, the first of the connection pads are configured to receive a first test signal, and after passing through the connection pads, the first internal test paths and the external test paths, the signal is sent from the last one of the connection pads generates a first test result signal; In a second test mode, the last of the connection pads is configured to receive a second test signal, and after passing through the connection pads, the second internal test paths and the external test paths, the first one of the The other connecting pads generate a second test result signal. The multi-channel antenna chip testing system as described in claim 1, wherein each of the first internal test paths includes a first test register, and each of the second internal test paths includes a second test scratchpad. The multi-channel antenna chip testing system as described in claim 1, wherein each of the first internal test paths includes: a multiplexer, including two selection input terminals and an output terminal; a first sub-path electrically coupled to one of the corresponding antenna switches and one of the two selection input terminals; a second sub-path including a first test register electrically coupled to one of the corresponding antenna switches and the other of the two selection inputs; and a third sub-path electrically coupled to the output end and the 2Nth connection pads; Wherein, in the first test mode, the multiplexers of each of the first internal test paths select to perform testing through the first sub-path or select to perform testing through the second sub-path. The multi-channel antenna chip testing system as described in claim 1, wherein each of the second internal test paths includes: a multiplexer, including two selection input terminals and an output terminal; a first sub-path electrically coupled to one of the corresponding antenna switches and one of the two selection input terminals; a second sub-path including a second test register electrically coupled to one of the corresponding antenna switches and the other of the two selection input terminals; and a third sub-path electrically coupled to the output end and the 2N-1th connection pads; Wherein, in the second test mode, the multiplexers of each of the second inner test paths select to perform testing through the first sub-path or both select to perform testing through the second sub-path. The multi-channel antenna chip testing system as described in claim 1, wherein the external test paths are set on a test fixture. The multi-channel antenna chip testing system as described in claim 1, wherein the signal processing end comprises an amplifier, an analog-to-digital converter, a bus bar and a processor. The multi-channel antenna chip testing system of claim 1, wherein the first test signal and the second test signal are generated by a testing machine, the first test result signal and the second test result signal is received by the test machine. A multi-channel antenna chip testing method, comprising: Provide a multi-channel antenna chip including a plurality of antenna switching switches, a plurality of connection pads, a plurality of first internal test paths and a plurality of second internal test paths, wherein a first end of each of the connection pads passes through a corresponding one The antenna switching switches are electrically coupled to a signal processing terminal, and a second terminal is electrically coupled to an external antenna; In a first test mode, the first of the connection pads receives a first test signal, and after passing through the connection pads, the first internal test paths and a plurality of external test paths, the last one of the The connection pads generate a first test result signal, wherein a first end of each of the first internal test paths is electrically coupled to the 2N-1th connection pads through one of the corresponding antenna switches, a first The two terminals are not electrically coupled to the 2Nth connection pads through the antenna switches, a first terminal of each of the external test paths is electrically coupled to the 2Nth connection pads, and a second terminal is electrically connected to the 2Nth connection pads. sexually coupled to the 2N+1th of these connection pads; and In a second test mode, the last of the connection pads receive a second test signal, so that after passing through the connection pads, the second internal test paths and the external test paths, the first one of the The connection pads generate a second test result signal, wherein a first end of each of the second internal test paths is electrically coupled to the 2Nth connection pads through one of the corresponding antenna switches, a second end It is not electrically coupled to the 2N-1th connection pads through the antenna switches. The multi-channel antenna chip testing method as described in claim 8, wherein each of the first internal test paths includes a first test register, and each of the second internal test paths includes a second test scratchpad. The multi-channel antenna chip testing method as described in claim 8, wherein each of the first internal test paths includes: a multiplexer, including two selection input terminals and an output terminal; a first sub-path electrically coupled to one of the corresponding antenna switches and one of the two selection input terminals; a second sub-path including a first test register electrically coupled to one of the corresponding antenna switches and the other of the two selection inputs; and a third sub-path electrically coupled to the output end and the 2Nth connection pads; The multi-channel antenna chip testing method further includes: In the first test mode, the multiplexers of each of the first internal test paths are selected to be tested through the first sub-path or all selected to be tested through the second sub-path. The multi-channel antenna chip testing method as described in claim 8, wherein each of the second internal test paths includes: a multiplexer, including two selection input terminals and an output terminal; a first sub-path electrically coupled to one of the corresponding antenna switches and one of the two selection input terminals; a second sub-path including a second test register electrically coupled to one of the corresponding antenna switches and the other of the two selection input terminals; and a third sub-path electrically coupled to the output end and the 2N-1th connection pads; The multi-channel antenna chip testing method further includes: In the second test mode, the multiplexers of each of the second inner test paths are selected to be tested through the first sub-path or all selected to be tested through the second sub-path. The multi-channel antenna chip testing method as described in claim 8, wherein the external testing paths are arranged on a testing jig. The multi-channel antenna chip testing method as described in claim 8, wherein the signal processing end comprises an amplifier, an analog-to-digital converter, a bus bar and a processor. The multi-channel antenna chip testing method as described in item 8 of the patent application scope further includes: generating the first test signal and the second test signal by a test machine; and The first test result signal and the second test result signal are received by the test machine.

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