JPH0359475A - Scan-in/out system - Google Patents

Abstract

PURPOSE:To shorten a data transfer time to 2/N at the time of scan-in/out operation and to 1/N when data are scanned in the same register group after being scanned out by dividing a scan path equally by N into the same number of bits. CONSTITUTION:Register groups 1A - 1N are divided equally into N groups which are equal in the number of bits, the serial-out terminal of a group (n-1) and the serial-out terminal of a group (n+1) and a scan-in data line 10 are connected to the serial-in terminal of a group (n) where 1 <= n <= N; and the serial-out terminals of the respective register groups are connected to a scan-out data line 11 through gates respectively and the terminal of the data line 10 is connected to the serial-out terminal of a scan data register 5. Then the scan operation mode of the register groups and address information on a register where data is to be scanned out are set in a scan address register 6 and scan-in/out operation is performed according to its contents. Consequently, the data transfer time can be shortened to 2/N at the time of scan-in/out operation and to 1/N when data are scanned in the same register group after being scanned out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a scan-in/out method, and in particular, a serial in-out method for registers specified by a means for specifying a group of registers to be scanned-in/out. The present invention relates to a scan-in/out method that enables operation.

[Conventional technology]

It has been conventional practice to configure registers built into LSIs to normally perform parallel in/out operations and to perform serial in/out operations in scan mode. When testing or diagnosing a processing device configured with an LSI, set the mode in which the register in the LSI performs serial in/out operation, and serially input the value to be set in the register from the scan-in data terminal. By doing this, data is set in the desired register. After setting the mode so that these registers perform parallel in/out operations, a clock signal is applied to operate the processing device, and the mode is set so that these registers perform serial in/out operations. It was common practice for the contents of these registers to be retrieved from the scan out data terminal.

[Problem to be solved by the invention]

In the conventional scan-in/out method described above, the LSI
All the registers inside were connected in series, and each had one entrance and exit. In this type of scan-in/out method, in order to read the contents of a desired register or set a value in a desired register, all registers must be serially in/out, and the data transferred at one time is The disadvantages are that the amount of data is large, that it takes a long time to transfer, and that the amount of data handled is large.

[Means to solve the problem]

The scan-in/out method of the present invention is based on the parallel-in/out method.
In the scan-in/out method, which performs serial in-out operations when scanning registers that perform out operations, the register group that makes up the scan path is divided into N register groups with the same number of bits, and 1≦n.
n-1 group (n=1
In the case of
=N, connect the serial out terminal of the first group) and the scan-in data line through the gate, connect the serial out terminal of each register group to the scan-out data line through the gate, and then Connect the scan-out data line to the serial-in terminal of the scan data register, connect the end of the scan-in data line to the serial-out terminal of the scan data register, and set the scan operation mode of the register group and the scan-in-out mode. The address information of the register to be scanned is set in a scan address register, and scan-in/out operations are performed according to the contents of the scan address register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the configuration of data stored in the scan address register 6 of FIG. 1.

In Figure 1, 1 is the scan-in/out register, I
A to ID are register groups with the same number of bits, 2A to 2D are selectors for serial-in data to each register group, 3 is a scan-out data selector, 5 is a scan data register, 6 is a scan address register, 10
11 is a scan-in data line, 11 is a scan-out data line, and 20A to 20D are register groups IA-, respectively.
The ID serial out data line is shown.

The register groups IA to ID in FIG. 1 are capable of performing parallel in/out operations and serial in/out operations.

In other words, the serial-in terminal of register group IA is scan-ined via two serial-in data selectors.
Data line 10. The serial-in terminal of register group 1B is connected to the serial-out data line 20B of register group IB and the serial-out data line 20D of register group ID, and the serial-in terminal of register group 1B is connected to scan-in data line lO1 register through serial-in data selector 2B. The serial-in terminal of the register group IC is connected to the serial-out data line 20G of the group IC and the serial-out data line 20A of the register group IA, and the serial-in terminal of the register group IC is connected to the serial-in data line 10 and the register group IA through the serial-in data selector 2C. The serial-in terminal of the register group ID is connected to the serial-out data line 20D of the ID and the serial-out data line 20B of the register group IB, and the serial-in terminal of the register group ID is connected to the user-can-in data line 10 through the serial-in data selector 2D. , serial out data line 20A of register group IA and serial out data line 20A of register group IC.
The scan-out data line 11 is connected to the data line 20C, and the scan-out data line 11 is connected to the serial-out data lines 20A to 20D of the register groups IA to ID.

The scan address register 6 contains data as shown in FIG. 2, for example. In Figure 2, the scan direction is the direction of scan between register groups from IA to IB.
→10→Information on whether the order is ID or ID→IC→IB→IA, register group specification is information that specifies the register group to be scanned in/out, presence or absence of scan-in data is the information indicating whether or not to input scan-in data to the serial in terminal of the register specified by the register group specification described above, and the register specification indicates the position of the register to be scanned in the register group. The information shown below is shown below.

When scanning out a target register group, the register group to be scanned, information indicating the register, scan direction,
and information without scan-in data is set in the scan address register, and a shift clock is generated from a shift clock generation circuit (not shown) that generates a shift clock according to the number of bits of the register group. Shift IA to ID. At this time, the scan out data selector 3 outputs serial out data of the target register group. When the scan direction is in the order of register groups IA, IB, and IC-ID, register groups IA to I before the scan-out operation
The contents of D are register groups IB, IC, ID, and I, respectively.
A, and the scan direction is register group 1D/1C.
When the order is IB and 1A, the contents of register groups IA to 1D before the scan-out operation are transferred to register groups ID and IA-IB-IC, respectively.

After scanout, if you want to return the contents of each register group to the state before scanout, set the scan direction in scan address register 6 to indicate the opposite direction from the scan direction at scanout. , Toshi, by assuming that there is no scan-in data and generating a shift clock again using the above shift clock generation circuit,
It is possible to return the register groups IA to ID to the state before scanout. When scanning in to a target register group, first specify the register group to be scanned, the scan direction, and specify no scan-in data in the scan register, and then use the shift clock generation circuit described earlier. Generate shift clock.

At this time, the contents of register groups IA to ID before the shift clock is generated are such that the scan direction is register group IA.
In the case of IB, IC, and ID, register groups IB and
If the scan direction is in the order of register group ID, IC, 1B, and IA, ID-
Moved to IA/IB-IC.

Next, the scan-in data to be scanned in is input in parallel to the scan data register 5, and the scan direction of the scan address register 6 is reversed and set.
After setting the information that there is scan-in data and the information specifying the target register group in the scan address register 6, a shift clock is generated from the shift clock generation circuit, thereby register groups IA to IA are set. Shift the ID. At this time, scan-in data is selectively input to the serial-in terminal of the register group specified by the scan address register 6, and the other register groups return to the state before the scan-in operation.

After scanning out the information of the register group that is the target of the scan operation, if you want to scan in the desired information to the register group, first specify the scan direction and the register group in the scan address register 6, and specify the scan direction and the register group.・The information indicating no data is set, and the shift clock generation circuit generates a shift clock. At this time, the scan-out data selector 3 selectively outputs the serial-out data of the register group to be scanned, and the information of the register group is read out to the scan data register 5. At this time, if the scan direction is register group 1A, IB, IC, ID, the information of register groups IA to 1D before scanning out is IB, respectively.
- If the scan direction is in the order of register group ID, IC, IB, and IA, the scan direction is moved to register group ID, IA, and IB-IC, respectively.

Next, the scan direction designation of the scan address register 6 is reversed to indicate that scan-in data is present, and the scan-in data is stored in the scan data register 5.
After inputting the data in parallel, the shift clock generation circuit generates a shift clock to shift the register groups IA to ID. At this time, scan-in data is input to the serial-in terminal of the register group to be scanned, and the other register groups return to the state before the scan-out/in operation.

〔Effect of the invention〕

As explained above, the present invention divides the scan canvas into N equal parts so that the number of bits is equal, thereby halving the data transfer time when all registers are connected in series during scan-in and scan-out operations. N, and when scanning in the same register group after scanning out, the effect is that the data transfer time can be reduced to 1/N when all registers are connected in series. be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the configuration of data stored in the scan address register 6 of FIG. 1. 1...Scan-in/out register, IA~
ID...Register group, 2A to 2D...
Serial-in data selector, 3...Scan-out data selector, 5...Scan data register, 6...Scan address register, IO. ...Scan-in data line, 11...Scan-out data line,
20A to 20D...Serial out data lines for register group.

Claims (1)

[Claims] In a scan-in-out method in which registers that perform parallel in-out operations perform serial in-out operations at the time of scan-in and out, a register group that constitutes a scan path is divided into N register groups with the same number of bits, n to the serial in terminal of n group where 1≦n≦N
Connect the serial out terminals of the −1 group (N group if n=1), the serial out terminals of the n+1 group (group 1 if n=N), and the scan-in data line through a gate. , connect the serial out terminal of each register group to the scan out data line via the gate, connect the scan out data line to the serial in terminal of the scan data register, and connect the end of the scan in data line to the scan out data line. Connect to the serial out terminal of the scan data register, set the scan operation mode of the register group and the address information of the register to be scanned in/out to the scan address register, and perform scan in/out according to the contents of the scan address register. A scan-in/out method characterized by being configured by performing an out operation.