TW202141288A - Data bus accessing device, method and system - Google Patents

Abstract

The present invention provides a data bus accessing device, method, and system. The data bus accessing device includes a plurality of host ports; a plurality of slave ports, wherein the host ports have a fixed priority order to access the slave ports; a plurality of first multiplexers and a plurality of second multiplexers configured to realize to switch between the host ports and the slave ports; a plurality of decoders configured to receive address signals sent by the host ports and decode the address signals, and generate corresponding selecting signals, the second multiplexers selects one of the corresponding slave port to connect to the master port according to the selecting signals; and a plurality of arbiters configured to receive request signals sent by the master ports, and determine the order in which the master ports accesses the slave ports according to a combination of the fixed priority order and the first-come-first-served basis.

Description

Device, method and system for accessing data bus

The present invention relates to data processing technology, in particular to a device, method and system for accessing a data bus.

At present, SOC (System on a Chip) mostly uses a multi-layer AHB (Advanced High Performance Bus) bus architecture for information interaction. The AHB specification includes the AMBA (Advanced Microcontroller Bus Architecture) specification and the AHB-Lite agreement. Among them, the AMBA specification v2.0 defines the connection between the AHB multi-layers, and determines multiple masters and multiple slaves by defining the signals of the arbiter, such as the bus request (HBUSREQx) signal and the bus authorization (HGRANTx) signal Switch between. The AHB-Lite protocol does not clearly define the connection between the AHB layers and the signal that defines the arbiter, but defines the connection between a single master and multiple slaves, and defines the strobe (HSEL) signal or the transmission type (HTRANS) signal instead of the confluence. The row request signal and the bus authorization signal are used to determine the switching between the master and multiple slaves.

However, in the above two methods, when the slave is switched to the new master, the pipeline characteristics of the AHB-Lite and AHB multilayer bus architecture may cause a single wait state to be inserted, causing delay.

In view of this, it is necessary to provide a method, device, and system for accessing the data bus that reduces the delay in the slave switching process.

The present invention provides a device for accessing a data bus. The device for accessing a data bus includes: Host port, used to connect to the host; The slave port is used to connect to the slave, the slave port is connected to the master port through a data bus, and the master port has a fixed priority order for accessing the slave port; A first multiplexer and a second multiplexer are connected between the host port and the slave port, and are used to switch between the host port and the slave port; The decoder, connected to the second multiplexer, is used to receive and decode the address signal sent by the host port to generate a corresponding selection signal, and the second multiplexer selects the corresponding address signal according to the selection signal The slave port is connected to the host port; and The arbiter, connected to the first multiplexer, is used to receive the request signal sent by the master port, and determine the number of the master port to access the slave port according to the combination of fixed priority and first-come, first-served order.

Further, when multiple master ports simultaneously issue access requests to the same slave port, the arbiter determines the order in which the master port accesses the slave port according to the fixed priority order, where the priority order is The higher the host port has the priority to access the slave port.

Further, when multiple host ports do not issue access requests to a slave port at the same time, the arbiter uses a first-come, first-doing method to determine the order in which the host port accesses the slave port, wherein the more the first is issued The host port of the request signal has the higher priority to access the slave port.

Further, when the number of the host ports is N, which are the first host port, the second host port,..., to the Nth host terminal, the corresponding priority order is the first level, the second level,..., Up to the Nth level, if the Mth master port requests to access the same slave port before the M-1th master port, the arbiter determines the Mth master port on a first come, first served basis Prioritize access to the slave port until the M-th master port stops requesting the use of the data bus, and the arbiter determines the first master port, the second master port, and the second master port according to the priority order. ... until the sequence of the M-1th master port accessing the slave port, where N and M are natural numbers, and M is less than or equal to N.

The present invention also provides a method for accessing a data bus, the data bus is used to connect a host port and a slave port, the host port has a fixed priority order for accessing the slave port, and the method includes: Receiving and decoding the address signal sent by the host port to generate a corresponding selection signal, and selecting the corresponding slave port to connect to the host port according to the selection signal; and The request signal sent by the host port is received, and the order in which the host port accesses the slave port is determined according to a combination of fixed priority and first-come-first-served.

Further, when multiple host ports simultaneously issue access requests to the same slave port, the order in which the host port accesses the slave port is determined according to the fixed priority order, and the host port with the higher priority order has The more priority the permission to access the slave port.

Further, when multiple host ports do not issue access requests to a slave port at the same time, a first-come-first-doing method is adopted to determine the order in which the host port accesses the slave port, and the host that issues the access request first The port has the priority to access the slave port.

Further, when the number of the host ports is N, which are the first host port, the second host port,..., to the Nth host terminal, the corresponding priority order is the first level, the second level,..., Up to the Nth level, if the Mth master port requests access to the same slave port before the M-1th master port, the Mth master port is determined to have priority access to the M-1 From the machine port until the Kth host port stops requesting the use of the data bus, the first host port, the second host port, ..., until the M-th host port are determined according to the priority order. 1 The sequence in which the master port accesses the slave port, where N and M are natural numbers, and M is less than or equal to N.

The present invention also provides a system for accessing a data bus. The system includes a host, a slave, and the above-mentioned device for accessing the data bus connected to the host and the slave.

The method, device, and system for accessing the data bus provided by the present invention can avoid using a single fixed priority level to determine the sequence of the host port accessing the slave port, and the host port with a lower priority sequence waits for a long time to obtain The lack of access to the data bus leads to lower data read and write efficiency, and it can also avoid the single use of a first come, first do method to determine the order in which the host port accesses the slave port, and the host with a higher priority order The speed of reading and writing data is slow and affects the operating efficiency of the system. Therefore, the method, device and system for accessing the data bus proposed by the present invention can increase the efficiency of reading and writing data on the host as a whole, realize zero wait state, and reduce Time delay.

In order to be able to understand the above objectives, features and advantages of the present invention more clearly, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other if there is no conflict.

In the following description, many specific details are set forth in order to fully understand the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention.

Please refer to FIG. 1, which is a schematic diagram of modules of an embodiment of a system for accessing a data bus proposed by the present invention. The system 100 for accessing a data bus includes a host 10, a slave 20, and a device 30 for accessing the data bus. .

In this embodiment, the device 30 for accessing the data bus includes a host port 31, a slave port 32, a first multiplexer 33, a second multiplexer 34, a decoder 35, and an arbiter 36.

The host port 31 is used to connect to the host 10. The host port 31 is used to connect to the host 10. The slave port 32 is used to connect the slave 20, and the slave port 32 is connected to the master port 31 through a data bus. The host port 31 has a fixed priority order for accessing the slave port 32. In this preferred embodiment, the host port 31 with the higher priority has the higher priority to access the slave port 32, that is to say, the host port 31 with the higher priority has the right to access the data. The platoon has the more preferential use right.

The first multiplexer 33 and the second multiplexer 34 are multiplexers, which are connected between the host port 31 and the slave port 32, and are used to implement the transfer from the host port 31 to the slave port 32. Switch between the slave ports 32.

The decoder 35 is connected to the second multiplexer 34, and is configured to receive the address signal (for example, HADDR0, HADDR4 shown in FIG. 1) sent by the host port 31 and decode it to generate a corresponding selection signal The second multiplexer 34 selects the corresponding slave port 32 to be connected to the master port 31 according to the selection signal.

The arbiter 36 is connected to the first multiplexer 33, and is configured to receive the request signal HREQx sent by the host port 31, and determine the access of the host port 31 according to the combination of fixed priority and first-come, first-served The sequence of the slave port 32. The request signal HREQx indicates that the host port 31 requests to use the data bus to access the slave port 32.

In this embodiment, when multiple master ports 31 simultaneously issue access requests to the same slave port 32, the arbiter 36 determines that the master port 31 accesses the slave port 32 according to the fixed priority order. The higher the priority of the host port 31, the higher the priority to access the slave port 32.

When multiple master ports 31 do not issue access requests to one slave port 32 at the same time, the arbiter 36 uses a first-come, first-served approach to determine the order in which the master port 31 accesses the slave port 32, and the earlier the request is issued The host port 31 of the access request has the permission to access the slave port 32 with higher priority.

Please refer to FIG. 2, the present invention also proposes a method for accessing data bus. The steps of the method are as follows:

For ease of understanding, in this embodiment, description is made by taking four master ports 31 and slave ports 32 as an example. The host port 31 includes a first host port M0, a second host port M1, a second host port M2, and a third host port M3. The priority order of the host port 31 to the slave port 32 is: Host port M0>second host port M1>second host port M2>third host port M3.

Step S101, the initial state of the arbiter 36 is set, specifically, the request signal HREQ and the transmission type signal HTRANS of the host port 31 are set. In this embodiment, the initial value of the request signal is set to HREQ=4'hf, indicating that the number of host ports 31 is four, and the transmission type signal Mx_HTRANS[1] is set to IDEL, indicating that there is no host port 31 requests to access the slave port 32.

Step S102, if the first host port M0, the second host port M1, the third host port M2, and the fourth host port M3 simultaneously request access to the same slave port 32, the arbiter 36 The priority order determines the order in which the master port 31 accesses the slave port 32, and the corresponding request signal HREQ is {!M3_HTRANS[1], !M2_HTRANS[1], !M1_HTRANS[1], M0_HTRANS[1] }, which indicates that the first host port M0 preferentially accesses the slave port 32, and the second host M1, the third host M2, and the fourth host M3 queue in turn to wait for access to the slave port 32. The arbiter 36 determines that the first master port M0 accesses the slave port 32 until the first master port M0 stops requesting the use of the data bus, and the corresponding transmission type signal M0_HTRANS[1] is set to IDE . The arbiter 36 sequentially determines the second master port M1, the third master port M2, and the fourth master port M3 to access the slave port 32 according to the priority level, until there is no master port 31 requests access to the slave port 32, and the corresponding transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

Step S103, if the second master port M1 requests to access the same slave port 32 before the first master port M0, the corresponding request signal HREQ is {!M3_HTRANS[1], !M2_HTRANS[1] , M1_HTRANS[1], !M0_HTRANS[1]}, indicating that the arbiter 36 determines that the second master port M1 preferentially accesses the slave port 32 according to a first-come, first-served manner, until the second master port M1 stops requesting to use the data bus, and the corresponding transmission type signal M1_HTRANS[1] is set to IDEL. The arbiter 36 then determines the first master port M0, the third master port M2, and the fourth master port M3 to access the slave port 32 according to the priority order, until there is no master port 31 requests access to the slave port 32, and the corresponding transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

Similarly, in step S104, if the third master port M2 requests to access the same slave port 32 before the first master port M0 and the second master port M1, the corresponding request signal HREQ is { !M3_HTRANS[1], M2_HTRANS[1], !M1_HTRANS[1], !M0_HTRANS[1]}, indicating that the arbiter 36 determines that the third host port M2 preferentially accesses the slave For the machine port 32, until the third host port M2 stops requesting to use the data bus, the corresponding transmission type signal M2_HTRANS[1] is set to IDEL. The arbiter 36 then determines according to the priority order that the first master port M0, the second master port M1, and the fourth master port M3 access the slave port 32 until there is no master port 31 requests access to the slave port 32, and the corresponding transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

Step S105, if the fourth master port M3 requests access to the same slave port 32 before the first master port M0, the second master port M1, and the third master port M2, the corresponding The request signal HREQ is {M3_HTRANS[1], !M2_HTRANS[1], !M1_HTRANS[1], !M0_HTRANS[1]}, indicating that the arbiter 36 determines the fourth host port M3 in a first-come, first-served manner Priority is given to the slave port 32 until the fourth master port M3 stops requesting the use of the data bus, and the corresponding transmission type signal M3_HTRANS[1] is set to IDEL. The arbiter 36 then determines according to the priority order that the first master port M0, the second master port M1, and the third master port M2 access the slave port 32 until there is no master port 31 requests access to the slave port 32, and the corresponding transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

It can be understood that when the number of the host ports 31 is N, they are respectively the first host port, the second host port, ..., up to the Nth host port, and the corresponding priority order is the first level, the second level, …, up to the Nth level, where N is a natural number. If the Mth master port requests access to the same slave port before the M-1th master port, where M is a natural number and is less than or equal to N, the arbiter 36 will do it according to first come first It is determined that the M-th master port preferentially accesses the slave port 32 until the M-th master port stops requesting the use of the data bus, and the corresponding transmission type signal MK_HTRANS[1] is set to IDEL. The arbiter 36 then determines the first host port, the second host port,..., until the M-1th host port accesses the slave port 32 according to the priority order, until there is no such The host port 31 requests to access the slave port 32, the corresponding transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

The method, device 30, and system 100 for accessing the data bus provided by the present invention can avoid using a single fixed priority level to determine the sequence of the host port 31 accessing the slave port 32, the host port 31 with a lower priority. The data read and write efficiency is low due to the long time waiting to obtain the use right of the data bus, and it can also avoid the use of a single first come, first do method to determine the order in which the host port 31 accesses the slave port 32. The host 10 with a higher priority order has a slower speed of reading and writing data, which affects the operating efficiency of the system. The method, device 30, and system 100 for accessing the data bus proposed by the present invention can increase the overall efficiency of reading and writing data of the host 10, and realize Zero wait state, reducing time delay.

In addition, the method, device 30, and system 100 for accessing the data bus proposed by the present invention use the first multiplexer 33 and the second multiplexer 34 to switch between the host 10 and the slave 20, which improves readability. The efficiency of writing data, at the same time, is not easy to cause the problem of timing closure.

The foregoing descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention shall be included in the protection of the present invention. Within range.

100: System to access data bus 10: Host 20: Slave 30: Access to the data bus device 31: host port 32: Slave port 33: The first multiplexer 34: second multiplexer 35: Decoder 36: Arbiter

FIG. 1 is a schematic diagram of modules of a system for accessing a data bus according to an embodiment of the present invention.

Fig. 2 is a schematic flowchart of a method for accessing a data bus according to an embodiment of the present invention.

none

100: System to access data bus

10: Host

20: Slave

30: Access to the data bus device

31: host port

32: Slave port

33: The first multiplexer

34: second multiplexer

35: Decoder

36: Arbiter

Claims (9)

A device for accessing a data bus, the device for accessing a data bus includes: Host port, used to connect to the host; The slave port is used to connect to the slave, the slave port is connected to the master port through a data bus, and the master port has a fixed priority order for accessing the slave port; A first multiplexer and a second multiplexer are connected between the host port and the slave port, and are used to switch between the host port and the slave port; The decoder, connected to the second multiplexer, is used to receive and decode the address signal sent by the host port to generate a corresponding selection signal, and the second multiplexer selects the corresponding address signal according to the selection signal The slave port is connected to the host port; and The arbiter, connected to the first multiplexer, is used to receive the request signal sent by the master port, and determine the number of the master port to access the slave port according to the combination of fixed priority and first-come, first-served order. The device for accessing the data bus according to claim 1, wherein when multiple master ports simultaneously issue an access request to the same slave port, the arbiter determines the access point of the master port according to the fixed priority order. The order of the slave ports is described, wherein the host port with the higher priority has the higher priority to access the slave port. The device for accessing the data bus according to claim 2, wherein when multiple host ports do not issue access requests to a slave port at the same time, the arbiter uses a first-come, first-served method to determine where the host port accesses According to the sequence of the slave ports, the host port that sends out the request signal first has the priority to access the slave port. The device for accessing the data bus as described in claim 1, wherein when the number of the host ports is N, which are the first host port, the second host port, and up to the Nth host, the corresponding priority order is as follows At level 1, level 2, up to level N, the M-th host port requests access to the same slave before the first host port, the second host port, and the M-1 host port Machine port, the arbiter determines that the M-th master port has priority access to the slave port according to a first-come-first-served manner, until the M-th master port stops requesting the use of the data bus, the arbiter Then determine the order in which the first host port, the second host port, and the M-1th host port access the slave port according to the priority order, where N and M are natural numbers, and M is less than or equal to N. A method for accessing a data bus, the data bus is used to connect a host port and a slave port, the host port has a fixed priority order for accessing the slave port, and the improvement is that the method includes: Receiving and decoding the address signal sent by the host port to generate a corresponding selection signal, and selecting the corresponding slave port to connect to the host port according to the selection signal; and The request signal sent by the host port is received, and the order in which the host port accesses the slave port is determined according to a combination of fixed priority and first-come-first-served. The method for accessing the data bus according to claim 5, wherein when multiple master ports simultaneously issue access requests to the same slave port, the master port is determined to access the slave port according to the fixed priority order The higher the priority of the host port, the higher the priority to access the slave port. The method for accessing the data bus as described in claim 6, wherein when multiple host ports do not issue access requests to one slave port at the same time, a first-come, first-doing method is adopted to determine that the host port accesses the slave port In the order of, the first host port that issues the access request has the higher priority to access the slave port. The method for accessing the data bus according to claim 5, wherein when the number of the host ports is N, which are the first host port, the second host port, and up to the Nth host, the corresponding priority order is as follows Level 1, Level 2, up to Level N, if the M-th master port requests access to the same slave before the first master port, the second master port, and the M-1 master port Port, the M-th master port will give priority to access the slave port according to the first-come-first-served manner, until the K-th master port stops requesting the use of the data bus, and then determine all the ports according to the priority order. The sequence in which the first host port, the second host port, and the M-1th host port access the slave port, wherein N and M are natural numbers, and M is less than or equal to N. A system for accessing a data bus. The system includes a host, a slave, and a device for accessing the data bus connected to the host and the slave. The improvement lies in that the device for accessing the data bus is request items 1 to 4 Any one of the devices for accessing the data bus.

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