TWI764139B - Data bus accessing device, method and system - Google Patents

Abstract

The present invention provides a data bus accessing device, method, and system. The data bus accessing device includes a plurality of host ports; a plurality of slave ports, wherein the host ports have a fixed priority order to access the slave ports; a plurality of first multiplexers and a plurality of second multiplexers configured to realize to switch between the host ports and the slave ports; a plurality of decoders configured to receive address signals sent by the host ports and decode the address signals, and generate corresponding selecting signals, the second multiplexers selects one of the corresponding slave port to connect to the master port according to the selecting signals; and a plurality of arbiters configured to receive request signals sent by the master ports, and determine the order in which the master ports accesses the slave ports according to a combination of the fixed priority order and the first-come-first-served basis.

Description

Apparatus, method and system for accessing a data bus

The present invention relates to data processing technology, in particular to a device, method and system for accessing data bus.

At present, SOC (System on a Chip, system on a chip) mostly adopts a multi-layer AHB (Advanced High Performance Bus, advanced high performance bus) bus structure for information exchange. AHB specification includes AMBA (Advanced Microcontroller Bus Architecture, Advanced Microcontroller Bus Architecture) specification and AHB-Lite agreement. Among them, AMBA specification v2.0 defines the connection between multiple layers of AHB, and judges multiple masters and multiple slaves by defining the signals of the arbiter, such as the bus request (HBUSREQx) signal and the bus grant (HGRANTx) signal switch between. The AHB-Lite protocol does not clearly define the connection between the multiple layers of AHB and the signal that defines the arbiter, but defines the connection between a single master and multiple slaves, and defines the strobe (HSEL) signal or the transmission type (HTRANS) signal instead of the bus The bus request signal and the bus authorization signal are used to judge the switching between the master and multiple slaves.

However, in the above two methods, when the slave is switched to the new master, a single wait state may be inserted due to the pipeline characteristics of the AHB-Lite and AHB multilayer bus architectures, causing delays.

In view of this, it is necessary to provide a method, apparatus and system for accessing a data bus which reduces the delay phenomenon of the slave switching process.

The present invention provides a device for accessing a data bus, the device for accessing a data bus includes: a host port for connecting to a host; a slave port for connecting to a slave, and the slave port is connected to a slave through the data bus The master port, the master port has a fixed priority for accessing the slave port; the first multiplexer and the second multiplexer are connected between the master port and the slave port, using In order to realize the switch between the master port and the slave port; the decoder, connected to the second multiplexer, is used to receive the address signal sent by the master port and decode it to generate the corresponding selection signal, the second multiplexer selects the corresponding slave port to connect to the master port according to the selection signal; and an arbiter connected to the first multiplexer for receiving the master port The request signal sent, and the order in which the master port accesses the slave port is determined according to the combination of fixed priority and first come first.

Further, when multiple host ports send access requests to the same slave port at the same time, the arbiter determines the order in which the host port accesses the slave port according to the fixed priority order, wherein the priority order is different. A higher master port has a higher priority to access the slave port.

Further, when multiple host ports do not send access requests to one slave port at the same time, the arbiter determines the order in which the host ports access the slave ports in a first-come, first-served manner, The master port of the request signal has the higher priority to access the slave port.

Further, when the number of the host ports is N, which are the first host port, the second host port, ..., up to the Nth host side, the corresponding priority order is the first level, the second level, ... Up to the Nth level, if the Mth host port requests access to the same slave port before the M-1th host port, the arbiter determines the Mth host port on a first-come, first-served basis The slave port is preferentially accessed until the Mth master port stops requesting to use the data bus, and the arbiter then determines the first master port, the second master port, the second master port, and the ..., until the M-1th master port accesses the slave port, wherein N and M are natural numbers, and M is less than or equal to N.

The present invention also provides a method for accessing a data bus, the data bus is used for connecting a master port and a slave port, the master port has a fixed priority for accessing the slave port, and the method includes: receiving Decoding the address signal sent by the host port to generate a corresponding selection signal, and selecting the corresponding slave port to connect to the host port according to the selection signal; and receiving the request signal sent by the host port, The sequence of accessing the slave port by the master port is determined according to the combination of fixed priority and first come first.

Further, when multiple host ports send access requests to the same slave port at the same time, the order in which the host port accesses the slave port is determined according to the fixed priority order, and the host port with a higher priority has a Permission to access the slave port has higher priority.

Further, when multiple host ports do not send access requests to a slave port at the same time, a first-come, first-served approach is used to determine the order in which the host ports access the slave ports, and the host that sends the access request first. The port has the higher priority to access the slave port.

Further, when the number of the host ports is N, which are the first host port, the second host port, ..., up to the Nth host side, the corresponding priority order is the first level, the second level, ... Up to the Nth level, if the Mth host port requests to access the same slave port before the M-1th host port, it is determined that the Mth host port preferentially accesses the Slave ports, until the K th host port stops requesting to use the data bus, and then determine the first host port, the second host port, ..., until the M-th host port according to the priority order. 1 The order in which the master port accesses the slave port, wherein N and M are natural numbers, and M is less than or equal to N.

The present invention also provides a system for accessing a data bus, the system comprising a master, a slave, and the above-mentioned device for accessing the data bus connected to the master and the slave.

The method, device and system for accessing a data bus provided by the present invention can avoid using a single fixed priority to determine the sequence of the master port accessing the slave port, and the host port with a lower priority will wait for a long time to acquire the slave port. The data read and write efficiency is low due to the lack of the right to use the data bus, and it can also avoid the use of a first-come-first-do method to determine the order of the host port accessing the slave port, and the host with higher priority can be avoided. The speed of reading and writing data is slow and affects the efficiency of the system. Therefore, The method, device and system for accessing a data bus proposed by the present invention can increase the overall efficiency of the host to read and write data, realize zero wait state, and reduce time delay.

100: System for accessing data busses

10: Host

20: Slave

30: Device for accessing the data bus

31: host port

32: slave port

33: First Multiplexer

34: Second Multiplexer

35: Decoder

36: Arbiter

FIG. 1 is a schematic diagram of a module of a system for accessing a data bus according to an embodiment of the present invention.

FIG. 2 is a schematic flowchart of a method for accessing a data bus according to an embodiment of the present invention.

In order to more clearly understand the above objects, features and advantages of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments may be combined with each other under the condition of no conflict.

In the following description, many specific details are set forth in order to facilitate a full understanding of the present invention, and the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention.

Please refer to FIG. 1 , which is a schematic diagram of a module of an embodiment of a system for accessing a data bus according to the present invention. The system 100 for accessing a data bus includes a host 10 , a slave 20 , and a device 30 for accessing the data bus. .

In this embodiment, the device 30 for accessing the data bus includes a master port 31 , a slave port 32 , a first multiplexer 33 , a second multiplexer 34 , a decoder 35 and an arbiter 36 .

The host port 31 is used to connect the host 10 . The host port 31 is used to connect the host 10 . The slave port 32 is used to connect the slave 20 , and the slave port 32 is connected to the master port 31 through a data bus. The master port 31 has a fixed priority for accessing the slave port 32 . In this preferred embodiment, the master port 31 with higher priority has the permission to access the slave port 32 more preferentially, that is to say, the master port 31 with higher priority has access to the data flow The row has the higher priority to use.

The first multiplexer 33 and the second multiplexer 34 are multiplexers, which are connected between the master port 31 and the slave port 32, and are used to realize the connection from the master port 31 to the slave port 32. Switching between the slave ports 32 .

The decoder 35 is connected to the second multiplexer 34 for receiving the address signal (for example, HADDR0, HADDR4 shown in FIG. 1 ) sent by the host port 31 and decoding it to generate a corresponding selection signal , the second multiplexer 34 selects the corresponding slave port 32 to connect to the master port 31 according to the selection signal.

The arbiter 36 is connected to the first multiplexer 33 for receiving the request signal HREQx sent by the host port 31, and determines the access of the host port 31 according to a combination of fixed priority and first come first The sequence of the slave ports 32. The request signal HREQx indicates that the master port 31 requests access to the slave port 32 using the data bus.

In this embodiment, when multiple master ports 31 send access requests to the same slave port 32 at the same time, the arbiter 36 respectively determines that the master port 31 accesses the slave port 32 according to the fixed priority order. , the master port 31 with a higher priority has a higher priority to access the slave port 32 .

When multiple master ports 31 do not send access requests to one slave port 32 at the same time, the arbiter 36 determines the order in which the master ports 31 access the slave ports 32 in a first-come, first-served manner, and the earlier the access requests are sent out. The master port 31 of the access request has a higher priority to access the slave port 32 .

Please refer to FIG. 2 , the present invention also provides a method for accessing a data bus. The steps of the method are as follows: In order to facilitate understanding, in this embodiment, the master port 31 and the slave port 32 are both four as an example for description. The host port 31 includes a first host port M0, a second host port M1, a second host port M2 and a third host port M3. The priority order of the host port 31 accessing the slave port 32 is: The host port M0 > the second host port M1 > the second host port M2 > the third host port M3.

Step S101 , setting the initial state of the arbiter 36 , specifically, setting the request signal HREQ and the transmission type signal HTRANS of the host port 31 . In this embodiment, the request letter The initial value of the number is set to HREQ=4'hf, indicating that the number of the host ports 31 is four, and the transmission type signal Mx_HTRANS[1] is set to IDEL, indicating that no host port 31 requests to access the slave port 32 .

Step S102, if the first host port M0, the second host port M1, the third host port M2 and the fourth host port M3 request to access the same slave port 32 at the same time, the arbiter 36 according to The priority order determines the order in which the host port 31 accesses the slave port 32, and the corresponding HREQ request signal is {!M3_HTRANS[1], !M2_HTRANS[1], !M1_HTRANS[1], M0_HTRANS[1] }, indicating that the first host port M0 preferentially accesses the slave port 32 , and the second host M1 , the third host M2 and the fourth host M3 queue up in sequence to access the slave port 32 . The arbiter 36 determines that the first host port M0 accesses the slave port 32 until the first host port M0 stops requesting to use the data bus, and the corresponding transfer type signal M0_HTRANS[1] is set to IDE . The arbiter 36 sequentially determines that the second host port M1, the third host port M2 and the fourth host port M3 access the slave port 32 according to the priority level, until there is no host port. 31 requests to access the slave port 32, the corresponding transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

Step S103, if the second host port M1 requests to access the same slave port 32 before the first host port M0, the corresponding request signal HREQ is {!M3_HTRANS[1], !M2_HTRANS[1] , M1_HTRANS[1], !M0_HTRANS[1]}, indicating that the arbiter 36 determines that the second master port M1 preferentially accesses the slave port 32 on a first-come-first-served basis until the second master port M1 stops requesting to use the data bus and the corresponding transfer type signal M1_HTRANS[1] is set to IDEL. The arbiter 36 then determines according to the priority order The first host port M0, the third host port M2, and the fourth host port M3 access the slave port 32 until the host port 31 does not request access to the slave port 32. The transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

Similarly, in step S104, if the third host port M2 requests to access the same slave port 32 before the first host port M0 and the second host port M1, the corresponding request signal HREQ is { !M3_HTRANS[1], M2_HTRANS[1], !M1_HTRANS[1], !M0_HTRANS[1]}, indicating that the arbiter 36 determines that the third host port M2 preferentially accesses the slave For the port 32, until the third host port M2 stops requesting to use the data bus, the corresponding transfer type signal M2_HTRANS[1] is set to IDEL. The arbiter 36 then determines that the first host port M0, the second host port M1 and the fourth host port M3 access the slave port 32 according to the priority order, until there is no host port. 31 requests to access the slave port 32, the corresponding transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

Step S105, if the fourth host port M3 requests to access the same slave port 32 before the first host port M0, the second host port M1 and the third host port M2, the corresponding The request signal HREQ is {M3_HTRANS[1], !M2_HTRANS[1], !M1_HTRANS[1], !M0_HTRANS[1]}, indicating that the arbiter 36 determines the fourth host port M3 on a first-come, first-served basis The slave port 32 is preferentially accessed until the fourth master port M3 stops requesting to use the data bus, and the corresponding transfer type signal M3_HTRANS[1] is set to IDEL. The arbiter 36 then determines according to the priority order The first host port M0, the second host port M1, and the third host port M2 access the slave port 32 until the host port 31 does not request access to the slave port 32, the corresponding The transmission type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

It can be understood that when the number of the host ports 31 is N, they are the first host port, the second host port, . ..., up to the Nth level, where N is a natural number. If the M-th master port requests access to the same slave port before the M-1-th master port, where M is a natural number and less than or equal to N, the arbiter 36 performs a first-come-first-served The method determines that the Mth host port preferentially accesses the slave port 32 until the Mth host port stops requesting to use the data bus, and the corresponding transfer type signal MK_HTRANS[1] is set to IDEL. The arbiter 36 then determines the first host port, the second host port, ..., until the M-1th host port accesses the slave port 32 according to the priority order, until there is no The master port 31 requests to access the slave port 32, the corresponding transfer type signal Mx_HTRANS[1] is set to IDEL, and the process returns to step S101.

The method, device 30 and system 100 for accessing a data bus provided by the present invention can avoid using a single fixed priority to determine the order of the master port 31 accessing the slave port 32, the master port 31 with a lower priority The data read and write efficiency is low due to waiting for a long time to obtain the right to use the data bus, and it can also avoid using a single first-come-first-do method to determine the order in which the host port 31 accesses the slave port 32. The speed of reading and writing data by the host 10 with a higher priority is slower, which affects the system operation efficiency. The method, device 30 and system 100 for accessing a data bus proposed by the present invention can increase the overall efficiency of the host 10 to read and write data, and realize the Zero wait state, reducing latency.

In addition, the method, device 30 and system 100 for accessing a data bus proposed by the present invention use the first multiplexer 33 and the second multiplexer 34 to realize the switching between the master 10 and the slave 20, thus improving the readability of the data bus. The efficiency of writing data, and at the same time, it is not easy to cause timing convergence problems.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

100: System for accessing data busses

10: Host

20: Slave

30: Device for accessing the data bus

31: host port

32: slave port

33: First Multiplexer

34: Second Multiplexer

35: Decoder

36: Arbiter

Claims (5)

A device for accessing a data bus, the device for accessing a data bus comprises: a host port for connecting to a host; a slave port for connecting to a slave, the slave port being connected to the host through the data bus a port, the master port has a fixed priority for accessing the slave port; a first multiplexer and a second multiplexer are connected between the master port and the slave port for implementing all Switching between the master port and the slave port; a decoder, connected to the second multiplexer, is used to receive and decode the address signal sent by the master port to generate a corresponding selection signal, so The second multiplexer selects the corresponding slave port to be connected to the host port according to the selection signal; and an arbiter is connected to the first multiplexer for receiving a request sent by the host port signal, and determine the order in which the master port accesses the slave port according to the combination of fixed priority and first come first. The device determines the order in which the master port accesses the slave port according to the fixed priority, wherein a master port with a higher priority has a higher priority to access the slave port; When the port does not send an access request to a slave port at the same time, the arbiter determines the order in which the master port accesses the slave port in a first-come, first-served manner, wherein the master port that sends the request signal earlier Has the higher priority to access the slave port. The device for accessing a data bus according to claim 1, wherein when the number of the host ports is N, they are the first host port, the second host port, and the Nth host port, respectively, and the corresponding priority order is as follows: Level 1, level 2, up to level N, the M th host port requests access to the same slave port before the first host port, the second host port, and the M-1 th host port port, the arbiter determines that the Mth master port preferentially accesses the slave port on a first-come, first-served basis, until the Mth master port stops requesting to use the data bus, the arbiter Then determine the sequence of the first host port, the second host port, and the M-1th host port accessing the slave port according to the priority order, wherein N and M are natural numbers, and M is less than or equal to N. A method for accessing a data bus, the data bus is used for connecting a master port and a slave port, the master port has a fixed priority for accessing the slave port, the improvement is that: the method comprises: receiving Decoding the address signal sent by the host port to generate a corresponding selection signal, and selecting the corresponding slave port to connect to the host port according to the selection signal; and receiving the request signal sent by the host port, And determine the order in which the master port accesses the slave port according to the combination of fixed priority and first come first, wherein when multiple master ports send access requests to the same slave port at the same time, according to the fixed priority The order determines the order in which the host port accesses the slave port, and the host port with a higher priority has the priority to access the slave port. When the access request is issued, the order in which the host port accesses the slave port is determined in a first-come, first-served manner, and the host port that issues the access request earlier has the priority to access the slave port. The method for accessing a data bus according to claim 3, wherein when the number of the host ports is N, they are the first host port, the second host port, up to the Nth host port, and the corresponding priorities are in sequence: Level 1, level 2, up to level N, if the Mth host port requests access to the same slave before the first host port, the second host port, up to the M-1th host port port, the M-th host port will be prioritized to access the slave port on a first-come-first-served basis, until the K-th host port stops requesting the use of the data bus, and then the M-th host port will be determined according to the priority order. The sequence of accessing the slave port from the first master port, the second master port, to the M-1th master port, wherein N and M are natural numbers, and M is less than or equal to N. A system for accessing a data bus, the system comprising a master, a slave, and a device for accessing the data bus connecting the master and the slave, the improvement is that: the device for accessing the data bus is request items 1 to 2 Any one of the devices for accessing a data bus.

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