JP2004078998A - Bus control method and computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for issuing a plurality of split read requirements at the same time from the same adaptor to a specified adaptor to enhance processing performance for a bus, in the system bus for a workstation or the like. <P>SOLUTION: A plurality of module IDs is allocated theoretically to one bus adaptor 405, 408, 409, 410 as a protocol for the bus, and the bus adaptor 405 in a starter guarantees an order of read data by module ID information of a response cycle. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to an information processing apparatus such as a personal computer and a workstation, and in particular, an address and data are multiplexed as a system bus, and another transfer is inserted between a start cycle and a response cycle of a read access operation. The present invention relates to a bus control method that supports a split transfer protocol that can be separated by a computer, and a computer system using the same.

In the above technical field, conventionally, as a system bus, another transfer is inserted between a start cycle and a response cycle of a read access operation, such as “Futurebus + P896.1 Logical Layer Specifications” (1990, IEEE). In many cases, a bus that supports a split transfer protocol that can be separated by performing the operation is used. The reason is that it is possible to improve the bus use efficiency and the responsiveness by enabling transfer of another module to be inserted between the activation cycle and the response cycle of the read access operation. FIG. 13 shows a typical timing example of the split transfer. FIG. 13 shows an example of a conventional split read access timing. ADDT [0:63] is an 8-byte multiplexed address / data bus, and ADRV is a valid address on an address / data bus ADDT [0:63]. The address valid signal DATAV indicating that the data is output is a data valid signal indicating that valid data is being output on the address / data bus ADDT [0:63]. When performing split read access on a conventional bus such as Futurebus +, first, the activation source module acquires the right to use the bus, then validates the address valid signal ADRV, and sets the address of the access destination by ADDT [0:63]. specify. At the same time, the mode designation control signal line is used to notify the access destination module that the currently activated access is a split read access (timing of 1301). Thereafter, the right to use the bus is abandoned, and the start cycle is terminated. On the other hand, the module of the access destination that has received this activation acquires the bus use right when the read data is ready, makes the address valid signal ADRV valid, and specifies the address of the access destination by ADDT [0:63]. . At the same time, the start-source module is notified by the mode designation control signal line that the transfer currently being started is a response to the split read access (timing of 1302). Next, the data valid signal DATAV is made valid, and valid read data is output on ADDT [0:63]. Thereafter, the access destination module relinquishes the right to use the bus and ends the response cycle. The activation source module determines a response to the access initiated by itself based on the mode designation control signal line output from the access destination module and the address of the access destination, and performs a series of controls of capturing the response data. I was

In recent years, in order to reduce the size and cost, the number of buses in which address and data are multiplexed by reducing the number of bus signal lines has been increasing. In this case, if a cycle for outputting the address of the access destination is provided at the time of the response transfer of the split read access as in the conventional example of FIG. 13, the bus is occupied extra by the address cycle due to the multiplexing of the address and the data. As a result, there arises a problem that the bus use efficiency is reduced and the response time is increased.

An object of the present invention is to provide a high-performance bus control system that solves such problems, improves bus use efficiency, and reduces response time.

(4) In order to achieve the above object, the present invention provides means for designating a module ID for each module connectable to a bus. Further, in a system having a multi-bus structure in which at least two or more layers are hierarchically connected, a module ID is assigned to each module existing on a bus of another layer. When an access from a module existing on a bus of another hierarchy is sent to the system bus, a module ID on the system bus allocated to the module is added to an adapter that takes an interface to perform read access. Provide a means for starting. On the other hand, when the activated module receives a response, there is provided a means for returning a response to a module existing on a bus of another hierarchy according to the added module ID.

By flowing module IDs assigned to individual modules existing on buses of other layers on the system bus, even if the same adapter is used as the interface of the system bus, the module ID differs for the system bus. By issuing a read request with the module ID, the switching of the read response can be identified by the adapter by the module ID in the response cycle. That is, in a multiprocessor system or the like, since up to one I / O access performed by each processor can be issued on the system bus in parallel, the response time of the system bus access is reduced.

According to the present invention, the accesses performed by the respective modules can be continuously issued on the system bus and the parallel processing can be performed while guaranteeing the access order, thereby reducing the response time of the system bus access. There is an effect that can be achieved. Further, even in a multiprocessor system or the like, I / O access performed by each processor can be similarly processed with a small number of pins. Further, according to the present invention, the module ID specified at the time of transfer can be set completely separately from the physical adapter, so that the module ID can be centrally assigned to modules with high necessity, and This has the effect of increasing the flexibility that can be handled.

FIG. 1 is a diagram showing split read access timing in the first embodiment of the present invention. In this embodiment, the cycle for outputting the address of the access destination is deleted, and the cycle is replaced with an identifier (module ID) for receiving the read data. In the start cycle, as in the conventional example of FIG. 13, the start source module first acquires the bus use right, then enables the address valid signal ADRV, and specifies the address of the access destination by ADDT [0:63]. At the same time, the mode designation control signal line notifies the access destination module that the currently activated access is the split read access (timing at 105). Thereafter, the right to use the bus is abandoned, and the start cycle is terminated. On the other hand, upon receiving the activation, the module at the access destination acquires the right to use the bus at the time when the read data is ready, then immediately makes the data valid signal DATAV valid, and puts the valid read data on ADDT [0:63]. Is output. At the same time, the start-source module is notified by the mode designation control signal line that the transfer currently being started is a response to the split read access (timing of 106). Thereafter, the access destination module relinquishes the right to use the bus and ends the response cycle. The activation source module responds to the access initiated by itself using the mode designation control signal line output by the access destination module and the module ID (SINKMOD: identifier of the split read response destination module) representing the access source module. Is determined, and a series of control of taking in the response data is performed. As in the present embodiment, if the SINKMOD has 4 bits, 16 modules can be designated. Specifically, as shown in FIG. 2, one module ID is assigned to each bus adapter connected to the bus. FIG. 2 shows an example of a system configuration having a hierarchical bus structure, wherein 201 and 202 are high-speed processor buses, 203 and 204 are bus adapters for interfacing with the high-speed processor bus, 205 is a system bus, and 206, 207 and 208 are IOs. Bus adapters 209, 210 and 211 for interfacing with the bus are IO buses. In this embodiment, one module ID is assigned to each bus adapter such as “0”, “1”, “2”, “3”, and “4” to the bus adapters 203, 204, 206, 207, and 208, respectively. Has been.

By the way, when the bus for controlling as in the first embodiment is applied to the system, the system configuration often has a hierarchical bus structure. FIG. 3 is a diagram showing a data flow diagram of the split read access at this time, where 301, 302, and 303 are processors (P1, P2, and P3), 304 is a multiprocessor-compatible processor bus, and 305 is a processor bus 304. A bus adapter for interfacing the system bus 307; 306, a main memory; 307, a system bus; 308, a bus adapter for interfacing the system bus 307 and the IO bus 311; 309, a bus for interfacing the system bus 307 and the IO bus 312 An adapter 310 is a bus adapter for interfacing the system bus 307 and the IO bus 313. 311, 312, and 313 are IO buses, 314 and 315 are IOs on the IO bus 311, and 316 and 317 are IOs and 318 on the 3IO bus 312. , 319 It is the IO on the IO bus 313. Here, if one module ID is assigned to each bus adapter, for example, “0” is assigned to the bus adapter 305, “1” is assigned to the bus adapter 308, “2” is assigned to the bus adapter 309, and “2” is assigned to the bus adapter 310. It looks like "3". At this time, the processor 1, the processor 2, and the processor 3 independently issue read requests to IOs connected to the system bus. At this time, in the bus system as shown in FIG. 3, if the module ID is issued on the system bus 307 without any limitation, if the IO bus 311 to be accessed supports the split transfer, the access time is short. There is a possibility that the response from the IO may return earlier, and there is a problem that the access order cannot be guaranteed only by referring to the module ID. (In this example, the SINKMOD in the response cycle is all returned as "0".) ). That is, if the buses of the other layers support the split transfer protocol as in the case of the conventional bus, only one read request can be issued from one bus adapter in order to guarantee the order of the response data. This occurs especially in the case of a multiprocessor system.

The second embodiment of the present invention further solves such a problem in a multiprocessor system by continuously issuing I / O accesses performed by respective processors on a system bus and parallelizing them. It is. Hereinafter, a second embodiment of the present invention will be described.

FIG. 4 is a block diagram of the system configuration of the present embodiment. Reference numerals 401, 402, and 403 denote processors (P1, P2, and P3); 404, a processor bus compatible with a multiprocessor; and 405, an interface between the processor bus 404 and the system bus 407. 406 is a main memory, 407 is a system bus, 408 is a bus adapter that interfaces between the system bus 407 and the IO bus 411, 409 is a bus adapter that interfaces between the system bus 407 and the IO bus 412, and 410 is a system bus A bus adapter for interfacing 407 with the IO bus 413, 411, 412, 413 are IO buses, 414, 415 are IOs on the IO bus 411, 416, 417 are IOs on the IO bus 412, 418, 419 are IO buses 413 In the IO above . Here, it is assumed that the number of bus adapters that can be connected to the system bus of this embodiment is four. However, in the present invention, it is assumed that 4 bits are allocated as a module identifier. This makes it possible to logically identify 16 modules. In the present invention, the processor 401 is “0”, the processor 402 is “1”, the processor 403 is “2”, the main memory 406 is “3”, the bus adapter 408 is “4”, and the bus adapter 409 is “4”. Is assigned to the bus adapter 410, and a module ID is assigned to the bus adapter 410, such as "6". The adapter 405 issues IO access requests from the processors 401 to 403 to the system bus 407 in parallel if the number of processors is one or less.

FIG. 5 shows an access time chart in the system configuration of FIG. 4, in which all the access destinations from the processors 401 to 403 are modules 408, and the access times of the IOs of the access destinations from the processors 401 to 403 are 12, respectively. 9 and 6 cycles. A cycle 501 is a read activation cycle, in which the bus master indicates the bus adapter 405 and the SINKMOD which is the response destination of the read data indicates "0" (indicating that the activation source is the processor 401). A cycle 502 is a read activation cycle, in which the bus master indicates the bus adapter 5 and the SINKMOD which is the response destination of the read data indicates "1" (indicating that the activation source is the processor 402).

A cycle 503 is a read activation cycle, in which the bus master indicates the bus adapter 405 and the SINKMOD which is the response destination of the read data indicates "2" (indicating that the activation source is the processor 403). A cycle 504 is a read response cycle, in which the bus master indicates the bus adapter 408 and the SINKMOD which is the response destination of the read data indicates "2". At this time, the bus adapter 405 performs control so as to see the SINKMOD “2” and return the fetched data to the processor 403. FIG. 8 shows the data flow at this time. A cycle 505 is a read response cycle, in which the bus master indicates the bus adapter 408 and the SINKMOD which is the read data response destination indicates "1". At this time, the bus adapter 405 sees the SINKMOD “1” and performs control to return the fetched data to the processor 402. FIG. 7 shows the data flow at this time. A cycle 506 is a read response cycle, in which the bus master indicates the bus adapter 408 and the SINKMOD which is the read data response destination indicates "0". At this time, the bus adapter 405 sees the SINKMOD “0” and performs control to return the fetched data to the processor 401. FIG. 6 shows the data flow at this time. If a module ID is allocated to the main memory, designation of DMA (direct memory access) becomes easy (FIG. 9).

FIG. 10 shows the number of cycles at the time of split read competition according to the first and second embodiments of the present invention. (A) is the number of cycles when the protocol of the first embodiment is used, and (b) is the number of cycles when the protocol of the second embodiment is used. Reference numerals 1001 and 1007 denote activation cycles of the IO access of the processor 1, 1002 and 1008 denote response cycles of the IO access of the processor 1, 1003 and 1009 denote the activation cycles of the IO access of the processor 1, and 1004 and 1010 denote the response of the IO access of the processor 1. Cycles 1005 and 1011 are activation cycles of the IO access of the processor 1, and 1006 and 1012 are response cycles of the IO access of the processor 1. As described above, if activation of a plurality of reads from the same adapter is not permitted as in the first embodiment, all read accesses are serialized, which takes a total of 27 cycles. On the other hand, if the parallel activation is performed as in the second embodiment, the number of cycles becomes 12 and the read access responsiveness is further improved.

By the way, in the description of the first and second embodiments, the response destination of the split read access is indicated by the identifier SINKMOD. However, as a third embodiment, the identifier of the response source of the split read access is defined by the present invention. If the destination can be specified in the same manner as the response destination, the split read request can be simultaneously issued to a plurality of response sources having different identifiers (SINKMOD) even if the identifiers are the same. In this case, as shown in FIGS. 11 and 12, module IDs “7” and “8” are assigned to the IOs 414 and IO 415, respectively, and the bus adapter 405 guarantees the order based on the information of the responder identifiers. Control may be performed.

FIG. 4 is a data flow diagram of split read access according to a bus protocol according to the first embodiment of the present invention. 1 is a configuration example of a hierarchical bus system. FIG. 5 is a flow chart of data of split read access according to a bus protocol when the first embodiment is directly used in a hierarchical bus system. FIG. 6 is a block diagram of a system configuration according to a second embodiment of the present invention. 9 is a split read access contention time chart according to the second embodiment of the present invention. FIG. 9 is a data flow diagram (1) of the second embodiment of the present invention. The data flow chart (2) of the 2nd Example of this invention. The data flow chart (3) of the 2nd Example of this invention. The data flow chart (4) of the 2nd Example of this invention. The figure which shows the number of cycles at the time of split read competition. The data flow chart (1) of the 3rd Example of this invention. 9 is a data flow diagram (2) of the third embodiment of the present invention. FIG. 6 is a data flow diagram of split read access according to a conventional bus protocol.

Explanation of reference numerals

401, 402, 403 ... processors,
404 ... Processor bus,
405 bus adapter,
406 main memory 407 system bus
408, 409, 410 ... bus adapter,
411, 412, 413 ... IO bus,
414, 415... IO on the IO bus 11,
416, 417... IO on the IO bus 12,
418, 419... IO on IO bus 13.

Claims (3)

An information processing apparatus, wherein a first module, the first module is connected, a first signal line employing a split protocol, a second module, and the second module are connected, An information processing apparatus comprising: a second signal line adopting a protocol; and a bus adapter in which the first signal line and the second signal line are hierarchically connected. 2. The information processing apparatus according to claim 1, wherein the first module transmits the transfer request to the second module via the first signal line, the bus adapter, and the second signal line. An information processing apparatus, which transfers the information. 2. The information processing device according to claim 1, further comprising: a third signal line connected to the bus adapter, and a third module connected to the third signal line.

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