TW202139396A - 雙晶粒半導體封裝結構及其製備方法 - Google Patents
雙晶粒半導體封裝結構及其製備方法 Download PDFInfo
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- TW202139396A TW202139396A TW110107579A TW110107579A TW202139396A TW 202139396 A TW202139396 A TW 202139396A TW 110107579 A TW110107579 A TW 110107579A TW 110107579 A TW110107579 A TW 110107579A TW 202139396 A TW202139396 A TW 202139396A
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Abstract
本揭露提供一種半導體封裝結構及其製備方法。該半導體封裝結構具有一封裝基底、一下元件晶粒、一夾層封裝基底以及一上元件晶粒。該下元件晶粒接合到該封裝基底。該夾層封裝基底位在該下元件晶粒上,並接合到該封裝基底。該上元件晶粒接合到該夾層封裝基底,且該夾層封裝基底形成在該夾層封裝基底上。
Description
本申請案主張2020年3月27日申請之美國正式申請案第16/832,305號的優先權及益處,該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體封裝結構及其製備方法。特別是有關於一種雙晶粒半導體封裝結構及其製備方法。
由於各種電子元件的積體密度的不斷改善,所以半導體產業經歷了持續的增長。此等改善主要係來自最小特徵尺寸的不斷減小,從而允許將更多元件整合到一給定的晶片面積中。
因為積體元件所佔據的體積基本上在半導體晶圓的表面上,所以這些整合的改善本質上是二維的(2D)。雖然微影技術的顯著改善已導致在二維積體電路形成中的顯著改進,但是其可在二維所達到的密度仍是有實體上的限制。當二維的縮放(scaling)仍是一些新設計的一選項,但採用利用z方向的三維(3D)封裝組合已成為業界研究的重點。在一三維封裝結構中,多個半導體晶粒可相互堆疊在其上。結果,一位在較上的半導體晶粒與該三維封裝結構的多個輸入/輸出(I/Os)之間的一訊號路徑,係長於在一位在較下的半導體晶粒與該等輸入/輸出之間的一訊號路徑,因此可延遲位在較上的半導體晶粒之訊號傳輸時間。
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一封裝基底;一下元件晶粒,接合到該封裝基底;一層間封裝基底,位在該下元件晶粒上,並接合到該封裝基底;以及一上元件晶粒,從該層間封裝基底的上方接合到該層間封裝基底。
在本揭露的一些實施例中,該封裝基底與該層間封裝基底的一周圍部分接合在一起。
在本揭露的一些實施例中,該層間封裝基底垂直地與該下元件晶粒分開設置。
在本揭露的一些實施例中,該半導體封裝結構還包括多個電連接件,連接在該層間封裝基底的一周圍部分與該封裝基底之間。
在本揭露的一些實施例中,該下元件晶粒位在側向分開設置的該等電連接件之間。
在本揭露的一些實施例中,該等電連接件與該下元件晶粒為側向分開設置。
在本揭露的一些實施例中,該等電連接件的一高度,係大於從該下元件晶粒的一上表面測量到該封裝基底的一上表面的一高度。
在本揭露的一些實施例中,該等電連接件為多個球柵陣列 (ball-grid-array,BGA)球或多個受控塌陷晶片連接(controlled-collapse-chip-connection,C4)凸塊。
在本揭露的一些實施例中,該半導體封裝結構還包括一囊封體(encapsulant),囊封該下元件晶粒、該層間封裝基底以及該上元件晶粒。
在本揭露的一些實施例中,在該下元件晶粒與該層間封裝基底之間的一空間,充填有該囊封體。
在本揭露的一些實施例中,該半導體封裝結構還包括多個額外的電連接件,設置在該封裝基底的一下側處。
在本揭露的一些實施例中,該半導體封裝結構還包括:多個第一導電柱,設置在該下元件晶粒與該封裝基底之間;以及多個第二導電柱,設置在該上元件晶粒與該層間封裝基底之間。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一封裝基底;一下元件晶粒,接合到該封裝基底;一層間封裝基底,位在該下元件晶粒的上方,其中該層間封裝基底的一周圍部分接合到該封裝基底,且該層間封裝基底的一覆蓋區(footprint area)係大於該下元件晶粒的一覆蓋區,並小於該封裝基底的一覆蓋區;以及一上元件晶粒,接合到該層間封裝基底上。
在本揭露的一些實施例中,該層間封裝基底的該覆蓋區係大於該上元件晶粒的一覆蓋區。
本揭露之一實施例提供一種半導體封裝結構的製備方法。該製備方法包括接合一下元件晶粒到一封裝基底上;接合一上元件晶粒到一層間封裝基底上;以及接合該層間封裝基底與該上元件晶粒到該封裝基底上,其中該接合的層間封裝基底位在該下元件晶粒與該上元件晶粒之間。
在本揭露的一些實施例中,該製備方法還包括:在接合該層間封裝基底到該封裝基底之前,形成多個電連接件在該層間封裝基底的一下側。
在本揭露的一些實施例中,該等電連接件形成如側向圍繞的一開放區,且當該層間封裝基底接合到該封裝基底時,該下元件晶粒位在該開放區中。
在本揭露的一些實施例中,該製備方法還包括:在該層間封裝基底接合到該封裝基底之後,以一囊封體囊封該下元件晶粒、該層 封裝基底以及該上元件晶粒。
在本揭露的一些實施例中,該層間封裝基底被該囊封體的一部分側向圍繞。
在本揭露的一些實施例中,在該下元件晶粒與該層間封裝基底之間的一空間,充填有該囊封體。
藉由設置該層間封裝基底,可提供額外的功率平面(power plane)以及額外的接地平面(ground plane)給該上元件晶粒(top device die)。相較於形成在該封裝基底中的該功率平面與該接地平面,在層間封裝基底中的這些額外的功率平面與接地平面可更靠近該上元件晶粒。因此,可藉由該層間封裝基底以提供功率及多個參考電壓給該上元件晶粒,而該層間封裝基底具有較少的損耗(loss)。據此,可改善上元件晶粒的效能。
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式,說明本揭露之實施例,然而本揭露並不受限於該實施例。此外,以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性,然而並非每一實施例必須包含該特定特徵、結構或是特性。再者,重複使用「在實施例中」一語並非必須指相同實施例,然而可為相同實施例。
為了使得本揭露可被完全理解,以下說明提供詳細的步驟與結構。顯然,本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外,已知的結構與步驟不再詳述,以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而,除了詳細說明之外,本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容,而是由申請專利範圍定義。
應當理解,以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實施例或實例以簡化本揭露內容。當然,該些僅為實例且不旨在進行限制。舉例而言,元件的尺寸並非僅限於所揭露範圍或值,而是可相依於製程條件及/或裝置的所期望性質。此外,以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。為簡潔及清晰起見,可按不同比例任意繪製各種特徵。在附圖中,為簡化起見,可省略一些層/特徵。
此外,為易於說明,本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係 用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
圖1為依據本揭露一些實施例一種半導體封裝結構10的剖視示意圖。圖2A為如圖1所示之該半導體封裝結構10的頂視示意圖。圖2B為在如圖1所示之該半導體封裝結構10中每一元件晶粒的一主動側的平面示意圖。
請參考圖1,在一些實施例中,半導體封裝結構10為一雙晶粒半導體封裝結構。在這些實施例中,半導體封裝結構10可具有一下元件晶粒100以及一上元件晶粒110,上元件晶粒110位在下元件晶粒100上。下元件晶粒100與上元件晶粒110均接合到一封裝基底120。因此,當下元件晶粒100的一後側BS1與上元件晶粒110的一後側BS2面向遠離封裝基底120處時,下元件晶粒100的一主動側AS1與上元件晶粒110的一主動側AS2面朝封裝基底120。一元件晶粒100/110的主動側AS1/AS2表示該元件晶粒在有多個晶粒輸入/輸出(die inputs/outputs,I/Os)形成在其上的一側。在一些實施例中,下元件晶粒100的該等晶粒輸入/輸出102包括多個導電墊AP1,且上元件晶粒110的該等晶粒輸入/輸出112包括多個導電墊AP2。在該等導電墊AP1/AP2電性連接到在元件晶粒100/110中的一積體電路。舉例來說,積體電路包括主動元件及/或被動元件(圖未示),並包括用於佈線主動及/或被動元件的多個內連接(圖未示)。導電墊AP1/AP2可經由該等內連接而連接到該等主動/被動元件。在一些實施例中,下元件晶粒100與上元件晶粒110為記憶體晶粒,例如動態隨機存取記憶體(DRAM)晶粒。在這些實施例中,在下元件晶粒100與上元件晶粒110中的積體電路,可包括記憶體胞的一矩陣,每一記憶體胞具有至少一存取電晶體(access transistor)以及至少一儲存電容器。此外,就電路與尺寸而言,上元件晶粒110可大致與下元件晶粒100相同。或者是,就電路、尺寸以及其他特徵而言,上元件晶粒110與下元件晶粒100可相互不同。
在一些實施例中,半導體封裝結構10還包括一夾層封裝基底(interposing package substrate)130。夾層封裝基底130設置在下元件晶粒100與上元件晶粒110之間。上元件晶粒110接合到夾層封裝基底130,且夾層封裝基底130接合到封裝基底120。換言之,上元件晶粒110並未直接接合到封裝基底120,但卻是接合到封裝基底120,而夾層封裝基底130係位在上元件晶粒110與封裝基底120之間。如圖2A所示,夾層封裝基底130的一覆蓋區(footprint area),可大於下元件晶粒100的一覆蓋區,但小於封裝基底120的一覆蓋區。依此方式,夾層封裝基底130的一周圍部位係位在下元件晶粒100的一跨度(span)外,且夾層封裝基底130可經由此周圍部位(如圖1所示)而接合到封裝基底120。在這些實施例中,就尺寸而言,在下元件晶粒100與上元件晶粒110相互相同的情況下,夾層封裝基底130的覆蓋區係大於上元件晶粒110的一覆蓋區。在一些實施例中,夾層封裝基底130與下元件晶粒100為垂直地分開設置。在這些實施例中,下元件晶粒100並未直接接觸夾層封裝基底130。
在一些實施例中,下元件晶粒100經由多個電連接件EC1而接合到封裝基底120。該等電連接件EC1連接下元件晶粒100的晶粒輸入/輸出102到封裝基底120。在一些實施例中,該等電連接件EC1分別包括一導電柱CP1以及一焊料接頭SJ1。導電柱CP1的一端子(terminal)連接到其中一晶粒輸入/輸出102,且導電柱CP1的另一端子經由焊料接頭SJ1而連接到封裝基底120。類似於下元件晶粒100,上元件晶粒110可經由多個電連接件EC2而接合到夾層封裝基底130。該等電連接件EC2連接上元件晶粒110的該等晶粒輸入/輸出112到夾層封裝基底130。在一些實施例中,該等電連接件EC2分別包括一導電柱CP2及一焊料接頭SJ2。導電柱CP2的一端子連接到其中一晶粒輸入/輸出112,而導電柱CP2的另一端子經由焊料接頭SJ2而連接到夾層封裝基底130。在一些實施例中,當且焊料接頭SJ1、SJ2由一焊錫材料(solder material)所製時,導電柱CP1、CP2的一材料可包含金屬(例如銅或銅合金)。此外,該等電連接件EC1、EC2可分別具有一高度,介於30μm到150μm的範圍內。然而,所屬技術領域中具有通常知識者可依據設計所需,而選擇該等電連接件EC1、EC2的材料及/或改良該等電連接件EC1、EC2的尺寸,本揭露並不以此為限。
在一些實施例中,夾層封裝基底130經由多個電連接件EC3而接合到封裝基底120。該等電連接件EC3可為球狀柵格陣列(ball grid array,BGA)球、受控塌陷晶片連接(controlled-collapse-chip-connection,C4)凸塊或其類似物。該等電連接件EC3可接觸夾層封裝基底130位在下元件晶粒100的一跨度(span)外的一周圍部,以使下元件晶粒100可被該等電連接件EC3側向圍繞。或者是,該等電連接件EC3可設置在下元件晶粒100的相對側處。在一些實施例中,該等電連接件EC3與下元件晶粒100係側向分開設置。在夾層封裝基底130與下元件晶粒100垂直分開設置的這些實施例中,該等電連接件EC3的一高度H1大於下元件晶粒100與該等電連接件EC1的一總高度H2。在一些實施例中,高度H1對應高度H2的一比率可介於1.04到3.5的範圍內。舉例來說,當高度H2可介於100μm到240μm之間時,高度H1可介於250μm到350μm之間。
在一些實施例中,封裝基底120為具有一介電核心層(dielectric core layer)122的一封裝基底。在這些實施例中,封裝基底120包括介電核心層122,並包括多個積層介電層(built-up dielectric layers)124以及多個導電圖案126的多層,而多個導電圖案126的該等層交錯地形成在介電核心層122的相對側處。如圖1所示,該等積層介電層124與該等導電圖案126的該等層可交錯地堆疊在介電核心層122的一上側以及一下側。該等導電圖案126的該等層可包括至少一層接地面(ground plane)、至少一層電源面(power plane)以及至少一訊號面(signal plane)。舉例來說,二訊號面跨設在一接地面與一電源面之間。此外,封裝基底120還可包括多個佈線結構(routing structures)RS1,用於將在封裝基底120上的該等電連接件EC1、EC3佈線到在封裝基底120中的該等導電圖案126的一些層,並封裝形成在封裝基底120之一下側處的多個輸入/輸出EC4。該等佈線結構RS1可具有多個導電跡線(conductive traces)、多個導電通孔(conductive vias)以及多個穿孔(through vias)。該等導電跡線分別延伸在其中一積層介電層124的一表面上,或者是在介電核心層122的一表面上。該等導電通孔分別穿過一或多個積層介電層124,並電性連接到一或多個導電跡線及/或該等導電圖案126的其中一層。此外,該等穿孔穿經介電核心層122,並經配置以建立該等佈線結構RS1位在接電核心層122之相對側之部分之間的電性連接。在一些實施例中,當該等導電圖案126的最下層與該等佈線結構RS1的最下部分接觸封裝輸入/輸出EC4時,該等導電圖案126的最上層以及該等佈線結構RS1的最上部分,係接觸該等電連接件EC1、EC3。該等封裝輸入/輸出EC4可為球狀柵格陣列(ball grid array,BGA)球、受控塌陷晶片連接(controlled-collapse-chip-connection,C4)凸塊或其類似物,並可具有一尺寸,係大於、大致相同於或小於該等電連接件EC3的一尺寸。
在一些實施例中,夾層封裝基底130為一無核心(core-less)封裝基底。在這些實施例中,夾層封裝基底130包括交錯堆疊的多個積層介電層132以及多個導電圖案134的多層。類似於在封裝基底120中之該等導電圖案126的該等層,在夾層封裝基底130中之該等導電圖案126的該等層可包括至少一層接地面、至少一層電源面以及至少一訊號面。由於封裝基底120經配置以從下元件晶粒100與上元件晶粒110傳送多個訊號/傳送多個訊號到下元件晶粒100與上元件晶粒110,當夾層封裝基底130經配置以僅從上元件晶粒110傳送多個訊號或僅傳送多個訊號到上元件晶粒110時,夾層封裝基底130可具有比封裝基底120更少的訊號面。舉例來說,當二訊號面可包含在封裝基底120中時,一單一訊號面跨設在夾層封裝基底130中的一接地面與一電源面之間。再者,類似於封裝基底120,夾層封裝基底130可包括多個佈線結構RS2,係用於將在夾層封裝基底130上的該等電連接件EC2佈線到在夾層封裝基底130中的該等導電圖案134的一些層,以及佈線到設置在夾層封裝基底130之一下側處的該等電連接件EC3。該等佈線結構RS2可包括多個導電跡線以及多個導電通孔。當該等導電通孔分別穿經一或多個積層介電層132並電性連接到一或多個導電跡線及/或該等導電圖案134的該等層時,該等導電跡線分別延伸在其中一積層介電層132的一表面上。
在其他實施例中,每一封裝基底120及夾層封裝基底130為一無核心封裝基底。在再另一實施例中,每一封裝基底120及夾層封裝基底130為具有一介電核心層的一封裝基底。或者是,當夾層封裝基底130為具有一介電核心層的一封裝基底時,封裝基底120為一無核心封裝基底。當無核心封裝基底可具有例如重量輕與Z方向的低高度之優點時,則具有一介電核心層的封裝基底係由一剛性材料(rigid material)所製,並可改善機械強度。所屬技術領域中具有通常知識者可依據製程所需,選擇用於封裝基底120與夾層封裝基底130之適合的基底形態,本揭露並不以此為限。
在一些實施例中,半導體封裝結構10還具有一囊封體(encapsulant)140。囊封體140囊封接合在封裝基底120上的多個元件。換言之,下元件晶粒100、上元件晶粒110、夾層封裝基底130以及該等電連接件EC1、EC2、EC3係被囊封體140所囊封。在一些實施例中,接合在封裝基底120上的該等元件被囊封體140所過度膜封(over-molded)。在此等實施例中,上元件晶粒110的一上表面(例如後側BS2)係被囊封體140的一上部所覆蓋。此外,在一些實施例中,囊封體140的一側壁大致與封裝基底120的一側壁為共面。囊封體140具有一模塑化合物(molding compound),例如環氧樹脂(epoxy resin)。在一些實施例中,囊封體140還具有多個填充粒子(filler particles)(圖未示),分散在模塑化合物中。該等填充粒子可由一非有機材料(inorganic material)(例如矽石(silica))所製,並經配置以改良囊封體140的材料特性(例如熱膨脹係數(coefficient of thermal expansion,CTE))。
請參考圖1及圖2B,在一些實施例中,下元件晶粒100該等晶粒輸入/輸出102還包括多個重分布結構RD1。在多個導電墊AP1形成在下元件晶粒100之主動側AS1的一中心區內處的實施例中,一些導電墊AP1藉由該等重分布結構RD1而佈線到主動側AS1的一周圍區。在此方法中,下元件晶粒100的該等晶粒輸入/輸出102可分佈在下元件晶粒100之主動側AS1的中心區與周圍區內。舉個例子,該等導電墊AP1可配置在中心區中的二行中,且在每一行中的該等導電墊AP1交錯地連接到延伸至周圍區的重分布結構RD1。然而,所屬技術領域中具有通常知識者可依據設計所需,改良該等導電墊AP1與該等重分布結構RD1的架構,且下元件晶粒100的該等晶粒輸入/輸出102可分佈在下元件晶粒100之主動側AS1的中心區與周圍區內。在一些實施例中,該等重分布結構RD1分別具有一導墊線CL1以及一重分布墊RP1。應當理解,在圖1中僅顯示出該等重分布結構RD1的該等重分布墊RP1,從圖1中省略該等導電線CL1。另一方面,該等導電線CL1與與該等重分布墊RP1均顯示在圖2A中。導電線CL1從其中一導電墊AP1延伸到其中一重分布墊RP1。在一些實施例中,導電線CL1從暴露在主動側AS1處之對應的導電墊AP1的一表面延伸,並側向接觸對應的重分布墊RP1。導電線CL1可形成為一直線。或者是,導電線CL1可具有沿著其延伸方向的至少一轉折(turn)。此外,該等電連接件EC1可形成在該等重分布墊RP1上,且該等導電墊AP1並未連接到該等重分布結構RD1。
類似於下元件晶粒100的描述,上元件晶粒110的該等晶粒輸入/輸出112還可包括多個重分布結構RD2。在一些實施例中,該重分布結構RD2分別包括一導電線CL2以及一重分布墊RP2。導電線CL2連接在其中一導電墊AP2與其中一重分布墊RP2之間。該等電連接件EC2可形成在該等重分布墊RP2上,而該等導電墊AP2並未連接到該等重分布結構RD1。該等導電墊AP2與該等重分布結構RD2的一架構可相同於或不同於該等導電墊AP1與該等重分布結構RD1的一架構,且上元件晶粒110的該等晶粒輸入/輸出112可分佈在上元件晶粒110之主動側AS2的一中心區與一周圍區內。
在另外的實施例中,省略該等重分布結構RD1及/或該等重分布結構RD2。在這些另外的實施例中,下元件晶粒100的該等輸入/輸出102及/或上元件晶粒110的該等輸入/輸出112僅包括該等導電墊AP1/AP2。
如上所述,依據本揭露的一些實施例的半導體封裝結構10係為一雙晶粒半導體封裝,並具有下元件晶粒100與上元件晶粒110,而上元件晶粒110位在下元件晶粒100上。下元件晶粒100接合到封裝基底120。上元件晶粒110接合到具有夾層封裝基底130在其間的封裝基底120。夾層封裝基底130位在下元件晶粒100與上元件晶粒110之間。此外,夾層封裝基底130可藉由電連接件EC3而接合到封裝基底,因此用於連接夾層封裝基底130到封裝基底120的該等電連接件EC3係側向圍繞下元件晶粒100。藉由設置夾層封裝基底130,可提供額外的電源面與額外的接地面給上元件晶粒110。相較於形成在封裝基底120中的電源面以及接地面,在夾層封裝基底130中的這些額外的電源面與接地面係接近上元件晶粒110。因此,可藉由具有較低損耗之夾層封裝基底而提供電源及參考電壓給上元件晶粒110。據此,可改善上元件晶粒110的效能。
圖3為依據本揭露一些實施例之如圖1所示的該半導體封裝結構10之製備方法S10的流程示意圖。圖4A到圖4I為在如圖1所示之該半導體封裝結構的製備流程期間在不同階段之結構的剖視示意圖。
請參考圖3及圖4A,執行步驟S11,並提供夾層封裝基底130。在夾層封裝基底130為無核心封裝基底的這些實施例中,多個積層介電層132、多個導電圖案134的多層以及該等佈線結構RS2係形成在一載體(carrier)(圖未示)上。之後,移除載體,且餘留的結構則形成夾層封裝基底130。每一積層介電層132的形成方法可包括疊層製程(lamination process)。此外,該等導電圖案134之每一層的形成方法可包括一微影(lithography)製程以及一鍍覆(plating)製程或一沉積製程。在一些實施例中,該等佈線結構RS2的一部份可與該等導電圖案134的其中一層一起形成。當該等導電圖案134與該等佈線結構RS2可由一金屬材料所構成時,該等積層介電層132可由聚合物材料所構成。在夾層封裝基底130為具有一介電核心層之一封裝基底的那些實施例中,如此封裝基底的形成方法可類似於參考將於圖4E所描述之封裝基底120的形成方法。
請參考圖3及圖4B,執行步驟S13,且上元件晶粒110經由該等電連接件EC2而接合到夾層封裝基底130上。在一些實施例中,該等電連接件EC2係預形成在上元件晶粒110的該等晶粒輸入/輸出112上。在上元件晶粒110接合到夾層封裝基底130上之後,該等電連接件EC2可接觸在夾層封裝基底130中之該等導電圖案134的最上層以及該等佈線結構RS2的最上部分,且可建立在上元件晶粒110與在夾層封裝基底130中的該等導電圖案134之間的電性連接。在一些實施例中,一拾取及放置製程(pick and place process)係用於貼合上元件晶粒110到夾層封裝基底130。此外,可接著執行一熱處理,以接合上元件晶粒110到夾層封裝基底130。
請參考圖3及圖4C,執行步驟S15,且多個電連接件EC3形成在夾層封裝基底130的一下側處。該等電連接件EC3接觸該等導電圖案134的最下層以及在夾層封裝基底130中之該等佈線結構RS2的最下部分。在一些實施例中,在夾層封裝基底130接合到封裝基底120上(將在參考圖4G進行描述)之後,該等電連接件EC3圍繞一開放區配置,而下元件晶粒100可容置在該開放區中。在該等電連接件EC3為BGA球的那些實施例中,該等電連接件EC3的形成方法可包括一植球製程(ball placement process)或一球安裝製程(ball mount process)。
請參考圖3及圖4D,執行步驟S17,且對夾層封裝基底130進行一單體化製程(singulation process)。其中一單體化結構係描述成在圖4D中的夾層封裝基底130。在一些實施例中,單體化製程可包括一鋸刀切割製程(blade sawing process)、一電漿切割(plasma dicing)製程或其類似製程。
應當理解,在參考圖4C及圖4D所描述的實施例中,在形成電連接件EC3之後進行單體化製程。然而,在另外的實施例中,單體化製程可在該等電連接件EC3形成之前進行。本揭露並未限制步驟S15、S17的前後順序。
請參考圖3及圖4E,執行步驟S19,且提供封裝基底120。在封裝基底120為具有介電核心層122的封裝基底的那些實施例中,多個積層介電層124與多個導電圖案126的多層可形成在介電核心層122的相對側處。此外,多個佈線結構RS1的多個導電通孔以及多個導電跡線與該等導電圖案126的該等層一起形成,且該等佈線結構R1的多個穿孔可形成在介電核心層122中。在一些實施例中,每一積層介電層124的形成方法包括一疊層製程(lamination process),且該等導電圖案126的每一層包括一微影製程以及一鍍覆製程或一沉積製程。此外,在一些實施例中,該等佈線結構RS1的該等穿孔之形成方法包括藉由一鑽孔(drilling)製程(例如一雷射鑽孔製程)以形成多個透孔(through holes)在介電核心層122中,且充填一導電材料進入這些透孔中,以藉由一鍍覆製程或一沉積製程而形成該等穿孔。在封裝基底120為一無核心封裝基底的那些實施例中,如此封裝基底的形成方法可類似於如參考圖4A所描述之夾層封裝基底130的形成方法。
請參考圖3及圖4F,執行步驟S21,且下元件晶粒100經由該等電連接件EC1而接合到封裝基底120上。在一些實施例中,該等電連接件EC1預形成在下元件晶粒100的該等晶粒輸入/輸出102上。在下元件晶粒100接合到封裝基底120上之後,該等電連接件EC1可接觸該等導電圖案126的最上層以及在封裝基底120中之該等佈線結構RS1的最上部分,並可建立下元件晶粒100與在封裝基底120中的該等導電圖案126之間的電性連接。在一些實施例中,一拾取及放置製程(pick and place process)係用於貼合下元件晶粒100到封裝基底120。此外,可接著執行一熱處理,以接合下元件晶粒100到封裝基底120。
在一些實施例中,用於製備包含夾層封裝基底130以及上元件晶粒110之結構的步驟(例如步驟S11、S13、S15、S17),係在製備包含封裝基底120與下元件晶粒100之結構的步驟(例如步驟S19、S21)之前進行。然而,在另外的實施例中,製備包含封裝基底120與下元件晶粒100之結構的步驟(例如步驟S19、S21),係在製備包含夾層封裝基底130與上元件晶粒110之結構的步驟(例如步驟S11、S13、S15、S17)之後進行。本揭露並未限制這些步驟群組的前後順序。
請參考圖3及圖4G,執行步驟S23,且夾層封裝基底130與上元件晶粒110經由該等電連接件EC3而接合到封裝基底120。在該等電連接件EC3接合到封裝基底120之後,該等電連接件EC3可接觸該等導電圖案126的最上層以及該等佈線結構RS1的最上部分,並可建立夾層封裝基底130與封裝基底120之間的電性連接。在一些實施例中,一拾取及放置製程係用於貼合接合有上元件晶粒110之夾層封裝基底130到封裝基底120。此外,可接著執行一熱處理,以接合夾層封裝基底130到封裝基底120。在一些實施例中,在夾層封裝基底130與封裝基底120的貼合之前,被該等電連接件EC3所側向圍繞的開放區係位在下元件晶粒100上,以使該等貼合的電連接件EC3可側向圍繞下元件晶粒100。
請參考圖3及圖4H,執行步驟S25,且接合在封裝基底120上的多個元件係被囊封體140所囊封。換言之,下元件晶粒100、上元件晶粒110、夾層封裝基底130以及該等電連接件EC3係被囊封體140所囊封。在一些實施例中,一轉移模塑(transfer molding)製程、一壓縮模塑(compression molding)製程或其他適合的模塑製程可被用來形成囊封體140。此外,在一些實施例中,囊封體140可進行一平坦化製程(例如一化學機械研磨製程),且上元件晶粒110仍可埋置在囊封體140中。
請參考圖3及圖4I,執行步驟S27,且該等封裝輸入/輸出EC4可形成在封裝基底120遠離下元件晶粒100的一側處。在該等封裝輸入/輸出EC4為BGA球的那些實施例中,該等封裝輸入/輸出EC4的形成方法可包括一植球製程或一球安裝製程。
請參考圖3及圖1,執行步驟S29,且目前結構係進行一封裝單體化製程。其中一單體結構係如圖1所描述。在一些實施例中,封裝單體化製程可包括一鋸刀切割製程(blade sawing process)、一電漿切割(plasma dicing)製程或其類似製程。在如上所述的實施例中,該等封裝輸入/輸出EC4的形成係在封裝單體化製程之前進行。然而,在另外的實施例中,封裝單體化製程可在該等封裝輸入/輸出EC4之後進行。本揭露並未限制這兩步驟的前後順序。
至此,形成依據一些實施例的半導體封裝結構10。半導體封裝結構10還可進行其他封裝製程或測試程序。
圖5A為依據本揭露一些實施例一種半導體封裝結構20的剖視示意圖。圖5B為在如圖5A之該半導體封裝結構20中每一元件晶粒之一主動側的平面示意圖。如參考圖5A及圖5B所描述的半導體封裝結構20,係類似於如圖1所示的半導體封裝結構10。係將僅描述其差異處,且類似或相同的部分在文中不再重複描述。
請參考圖5A及圖5B,在一些實施例中,省略參考圖1及圖2B所述的該等重分布結構RD1、RD2。在這些實施例中,下元件晶粒100的該等晶粒輸入/輸出102可僅包括多個導電墊AP1,且上元件晶粒110的該等晶粒輸入/輸出112可僅包括多個導電墊AP2。此外,一黏貼材料AM1可設置在下元件晶粒100與封裝基底120之間。黏貼材料AM1並位覆蓋下元件晶粒100的整個主動側AS1。在該等導電墊AP1形成在主動側AS1的一中心區內的那些實施例中,黏貼材料AM1可具有二分開的子部份,且該等導電墊AP1可位在黏貼材料AM1之該等子部分之間的一空間中。類似地,一黏貼材料AM2可設置在上元件晶粒110與夾層封裝基底130之間。此外,黏貼材料AM2可具有二分開的子部份,且上元件晶粒110的該等導電墊AP2可位在黏貼材料AM2的二子部分之間的一空間內。
關於半導體封裝結構20的一製造流程,在下元件晶粒100接合到封裝基底120上之前,黏貼材料AM1可分散在封裝基底120上。此外,在上元件晶粒110接合到夾層封裝基底130上之前,黏貼材料AM2可分散在夾層封裝基底130上。
圖6A為依據本揭露一些實施例之一種半導體封裝結構20a的剖視示意圖。圖6B為在如圖6A之該半導體封裝結構20a中每一元件晶粒之一主動側的平面示意圖。參考如圖6A及圖6B所述的半導體封裝跡結構20a係類似如圖5A及圖5B所示的半導體封裝結構20。僅討論其間的差異,而相同或相似的部分則不再重複。
請參考圖6A及圖6B,在該等導電墊AP1形成在下元件晶粒100之主動側AS1的一周圍區內的實施例中,該等導電墊AP1可側向圍繞黏貼材料AM1,或可位在黏貼材料AM1的相對側。此外,黏貼材料AM1可形成如一連續伸展圖案,而不是形成如具有多個分開的子部份。類似地,在該等導電墊AP2形成在上元件晶粒110之主動側AS2的一周圍部內的實施例中,該等導電墊AP2可側向圍繞黏貼材料AM2,或可位在黏貼材料AM2的相對側。再者,黏貼材料AM2可形成如一連續伸展圖案,而不是形成如具有多個分開的子部份。
圖7為依據本揭露一些實施例一種半導體封裝結構30的剖視示意圖。圖8A及圖8B為依據本揭露一些實施例中一種接合該下元件晶粒100到該封裝基底120上之方法的示意圖。參考如圖7、圖8A及圖8B所述的實施例係類似參考如圖1、圖2A、圖2B、圖3及圖4A到圖4I所述的實施例。僅討論其間的差異,而相同或相似的部分則不再重複。
請參考圖7,在一些實施例中,下元件晶粒100經由一線接合方法(wire bonding manner)而接合到封裝基底120上。在這些實施例中,當下元件晶粒100的主動側AS1面對遠離封裝基底120方向時,下元件晶粒100的後側BS1面對朝向封裝基底120方向。此外,多個接合線BW形成來連接一些晶粒輸入/輸出102到封裝基底120。舉例來說,該等接合線BW連接在該等重分布墊RP1與封裝基底120之間。
請參考圖8A及圖8B,關於半導體封裝結構30的一製造流程中,在下元件晶粒100貼合到封裝基底120上之後,形成該等接合線BW。
如上所述,依據本揭露的一些實施例之半導體封裝結構為一雙晶粒半導體封裝結構,並包括下元件晶粒以及上元件晶粒,而上元件晶粒位在下元件晶粒上。下元件晶粒接合到封裝基底。上元件晶粒接合到具有夾層封裝基底在其間的封裝基底。此外,夾層封裝基底位在下元件晶粒與上元件晶粒之間。可提供在夾層封裝基底中之額外的電源面以及額外的接地面給上元件晶粒。相較於形成在封裝基底中的電源面以及接地面,在夾層封裝基底中之這些額外的電源面以及接地面係接近上元件晶粒。因此,可藉由具有較少損耗之夾層封裝基底提供電源及參考電壓給上元件晶粒。據此,可改善上元件晶粒的效能。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一封裝基底;一下元件晶粒,接合到該封裝基底;一層間封裝基底,位在該下元件晶粒上,並接合到該封裝基底;以及一上元件晶粒,從該層間封裝基底的上方接合到該層間封裝基底。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一封裝基底;一下元件晶粒,接合到該封裝基底;一層間封裝基底,位在該下元件晶粒的上方,其中該層間封裝基底的一周圍部分接合到該封裝基底,且該層間封裝基底的一覆蓋區(footprint area)係大於該下元件晶粒的一覆蓋區,並小於該封裝基底的一覆蓋區;以及一上元件晶粒,接合到該層間封裝基底上。
本揭露之一實施例提供一種半導體封裝結構的製備方法。該製備方法包括接合一下元件晶粒到一封裝基底上;接合一上元件晶粒到一層間封裝基底上;以及接合該層間封裝基底與該上元件晶粒到該封裝基底上,其中該接合的層間封裝基底位在該下元件晶粒與該上元件晶粒之間。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體封裝結構
20:半導體封裝結構
20a:半導體封裝結構
30:半導體封裝結構
100:下元件晶粒
102:晶粒輸入/輸出
110:上元件晶粒
112:晶粒輸入/輸出
120:封裝基底
122:介電核心層
124:積層介電層
126:導電圖案
130:夾層封裝基底
132:積層介電層
134:導電圖案
140:囊封體
AM1:黏貼材料
AM2:黏貼材料
AP1:導電墊
AP2:導電墊
AS1:主動側
AS2:主動側
BS1:後側
BS2:後側
BW:接合線
CL1:導電線
CL2:導電線
CP1:導電柱
CP2:導電柱
EC1:電連接件
EC2:電連接件
EC3:電連接件
EC4:輸入/輸出
H1:高度
H2:高度
RD1:重分布結構
RD2:重分布結構
RP1:重分布墊
RP2:重分布墊
RS1:佈線結構
RS2:佈線結構
SJ1:焊料接頭
SJ2:焊料接頭
S10:方法
S11:步驟
S13:步驟
S15:步驟
S17:步驟
S19:步驟
S21:步驟
S23:步驟
S25:步驟
S27:步驟
S29:步驟
參閱實施方式與申請專利範圍合併考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。
圖1為依據本揭露一些實施例一種半導體封裝結構的剖視示意圖。
圖2A為如圖1所示之該半導體封裝結構的頂視示意圖。
圖2B為在如圖1所示之該半導體封裝結構中每一元件晶粒的一主動側的平面示意圖。
圖3為依據本揭露一些實施例之如圖1所示的該半導體封裝結構之製備方法的流程示意圖。
圖4A到圖4I為在如圖1A所示之該半導體封裝結構的製備流程期間在不同階段之結構的剖視示意圖。
圖5A為依據本揭露一些實施例之一種半導體封裝結構的剖視示意圖。
圖5B為在如圖5A之該半導體封裝結構中每一元件晶粒之一主動側的平面示意圖。
圖6A為依據本揭露一些實施例之一種半導體封裝結構的剖視示意圖。
圖6B為在如圖6A之該半導體封裝結構中每一元件晶粒之一主動側的平面示意圖。
圖7為依據本揭露一些實施例一種半導體封裝結構的剖視示意圖。
圖8A及圖8B為依據本揭露一些實施例中一種接合該下元件晶粒到該封裝基底上之方法的示意圖。
10:半導體封裝結構
100:下元件晶粒
102:晶粒輸入/輸出
110:上元件晶粒
112:晶粒輸入/輸出
120:封裝基底
122:介電核心層
124:積層介電層
126:導電圖案
130:夾層封裝基底
132:積層介電層
134:導電圖案
140:囊封體
AP1:導電墊
AP2:導電墊
AS1:主動側
AS2:主動側
BS1:後側
BS2:後側
CP1:導電柱
CP2:導電柱
EC1:電連接件
EC2:電連接件
EC3:電連接件
EC4:輸入/輸出
H1:高度
H2:高度
RP1:重分布墊
RP2:重分布墊
RS1:佈線結構
RS2:佈線結構
SJ1:焊料接頭
SJ2:焊料接頭
Claims (20)
- 一種半導體封裝結構,包括: 一封裝基底; 一下元件晶粒,接合到該封裝基底; 一層間封裝基底,位在該下元件晶粒上,並接合到該封裝基底;以及 一上元件晶粒,從該層間封裝基底的上方接合到該層間封裝基底。
- 如請求項1所述之半導體封裝結構,其中該封裝基底與該層間封裝基底的一周圍部分接合在一起。
- 如請求項1所述之半導體封裝結構,其中該層間封裝基底垂直地與該下元件晶粒分開設置。
- 如請求項1所述之半導體封裝結構,還包括多個電連接件,連接在該層間封裝基底的一周圍部分與該封裝基底之間。
- 如請求項4所述之半導體封裝結構,其中該下元件晶粒位在側向分開設置的該等電連接件之間。
- 如請求項4所述之半導體封裝結構,其中該等電連接件與該下元件晶粒為側向分開設置。
- 如請求項4所述之半導體封裝結構,其中該等電連接件的一高度,係大於從該下元件晶粒的一上表面測量到該封裝基底的一上表面的一高度。
- 如請求項4所述之半導體封裝結構,其中該等電連接件為多個球柵陣列 (ball-grid-array,BGA)球或多個受控塌陷晶片連接(controlled-collapse-chip-connection,C4)凸塊。
- 如請求項1所述之半導體封裝結構,還包括一囊封體(encapsulant),囊封該下元件晶粒、該層間封裝基底以及該上元件晶粒。
- 如請求項9所述之半導體封裝結構,其中在該下元件晶粒與該層間封裝基底之間的一空間,充填有該囊封體。
- 如請求項1所述之半導體封裝結構,還包括多個額外的電連接件,設置在該封裝基底的一下側處。
- 如請求項1所述之半導體封裝結構,還包括: 多個第一導電柱,設置在該下元件晶粒與該封裝基底之間;以及 多個第二導電柱,設置在該上元件晶粒與該層間封裝基底之間。
- 一種半導體封裝結構,包括: 一封裝基底; 一下元件晶粒,接合到該封裝基底; 一層間封裝基底,位在該下元件晶粒的上方,其中該層間封裝基底的一周圍部分接合到該封裝基底,且該層間封裝基底的一覆蓋區(footprint area)係大於該下元件晶粒的一覆蓋區,並小於該封裝基底的一覆蓋區;以及 一上元件晶粒,接合到該層間封裝基底上。
- 如請求項13所述之半導體封裝結構,其中該層間封裝基底的該覆蓋區係大於該上元件晶粒的一覆蓋區。
- 一種半導體封裝結構的製備方法,包括: 接合一下元件晶粒到一封裝基底上; 接合一上元件晶粒到一層間封裝基底上;以及 接合該層間封裝基底與該上元件晶粒到該封裝基底上,其中該接合的層間封裝基底位在該下元件晶粒與該上元件晶粒之間。
- 如請求項15所述之製備方法,還包括:在接合該層間封裝基底到該封裝基底之前,形成多個電連接件在該層間封裝基底的一下側。
- 如請求項16所述之製備方法,其中該等電連接件形成如側向圍繞的一開放區,且當該層間封裝基底接合到該封裝基底時,該下元件晶粒位在該開放區中。
- 如請求項15所述之製備方法,還包括:在該層間封裝基底接合到該封裝基底之後,以一囊封體囊封該下元件晶粒、該層 封裝基底以及該上元件晶粒。
- 如請求項18所述之製備方法,其中該層間封裝基底被該囊封體的一部分側向圍繞。
- 如請求項18所述之製備方法,其中在該下元件晶粒與該層間封裝基底之間的一空間,充填有該囊封體。
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US7099293B2 (en) * | 2002-05-01 | 2006-08-29 | Stmicroelectronics, Inc. | Buffer-less de-skewing for symbol combination in a CDMA demodulator |
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US8409917B2 (en) | 2011-03-22 | 2013-04-02 | Stats Chippac Ltd. | Integrated circuit packaging system with an interposer substrate and method of manufacture thereof |
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