TW202137430A - Package structure - Google Patents

Package structure Download PDF

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Publication number
TW202137430A
TW202137430A TW109130281A TW109130281A TW202137430A TW 202137430 A TW202137430 A TW 202137430A TW 109130281 A TW109130281 A TW 109130281A TW 109130281 A TW109130281 A TW 109130281A TW 202137430 A TW202137430 A TW 202137430A
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Taiwan
Prior art keywords
package structure
lead frame
plastic packaging
protruding
packaging material
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TW109130281A
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Chinese (zh)
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TWI736409B (en
Inventor
余正富
史凱日
柳怡蓉
吳祈毅
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美商矽成積體電路股份有限公司
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Priority to US17/109,255 priority Critical patent/US20210305136A1/en
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Publication of TWI736409B publication Critical patent/TWI736409B/en
Publication of TW202137430A publication Critical patent/TW202137430A/en
Priority to US17/723,536 priority patent/US20220246501A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/38—Removing material by boring or cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Laser Beam Processing (AREA)

Abstract

A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four peripheral regions of the die pad, and include a plurality of plating surfaces. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. The leads protrude a peripheral region of the plastic package material. Therefore, it is favorable for promoting a solderable area of a lateral of the package structure and enhancing a connecting strength between the package structure and a circuit board.

Description

封裝結構Package structure

本揭示內容係關於一種封裝結構，特別是一種增加可銲接面積的封裝結構。The present disclosure relates to a package structure, especially a package structure that increases the solderable area.

現今半導體封裝產業中，四方平面無引腳封裝(Quad Flat No Leads, QFN)因其引腳側邊的可銲接的面積較少，故將四方平面無引腳封裝設置於電路板時具有較不佳的銲接效果。In the semiconductor packaging industry nowadays, the Quad Flat No Leads (QFN) package has less solderable area on the side of its pins. Therefore, the Quad Flat No Leads (QFN) package has less advantages when placed on the circuit board. Good welding effect.

為解決前述問題，目前已發展一種四方平面無引腳封裝的引腳相對底部內縮的結構，藉此提升引腳側邊可銲接的面積。然而，引腳底部設置於電路板的面積變小，造成設置於電路板上不穩定，產生壽命下降的問題。因此，發展一種可增加引腳的可銲接面積，且同時可穩定地設置於電路板的封裝結構遂成為業界重要且急欲解決的問題。In order to solve the aforementioned problems, a structure in which the leads of a quad flat leadless package are retracted relative to the bottom has been developed, thereby increasing the solderable area on the sides of the leads. However, the area at the bottom of the pin provided on the circuit board becomes smaller, which causes unstable installation on the circuit board, resulting in a problem of reduced service life. Therefore, the development of a package structure that can increase the solderable area of the pins and can be stably installed on the circuit board has become an important and urgent problem in the industry.

本揭示內容提供一種封裝結構，藉由引腳包含複數電鍍面以提升封裝結構的可銲接性，同時達到設置於電路板上的穩定性。The present disclosure provides a package structure, which improves the solderability of the package structure by including a plurality of electroplated surfaces on the pins, and at the same time achieves the stability of being installed on the circuit board.

依據本揭示內容一實施方式提供一種封裝結構，包含一導線架、一半導體晶片及一塑膠封裝材料。導線架包含一晶片座與複數引腳。引腳設置於晶片座的四周，包含複數電鍍面。半導體晶片設置於導線架的晶片座上。塑膠封裝材料設置於導線架上。引腳突出於塑膠封裝材料的外緣。According to an embodiment of the present disclosure, a package structure is provided, which includes a lead frame, a semiconductor chip, and a plastic packaging material. The lead frame includes a chip holder and a plurality of pins. The pins are arranged on the periphery of the wafer holder and include a plurality of electroplating surfaces. The semiconductor chip is arranged on the chip holder of the lead frame. The plastic packaging material is arranged on the lead frame. The pins protrude from the outer edge of the plastic packaging material.

依據前段所述實施方式的封裝結構，其中引腳可更包含一凹陷部，位於引腳的一表面，且電鍍面設置於凹陷部。According to the package structure of the embodiment described in the preceding paragraph, the lead may further include a recessed portion located on a surface of the lead, and the electroplating surface is disposed in the recessed portion.

依據前段所述實施方式的封裝結構，其中電鍍面的材質可為錫合金或鎳金合金。According to the package structure of the embodiment described in the preceding paragraph, the material of the plating surface can be tin alloy or nickel-gold alloy.

依據前段所述實施方式的封裝結構，其中引腳可更包含至少一無電鍍面。According to the package structure of the embodiment described in the preceding paragraph, the lead may further include at least one electroless plating surface.

依據前段所述實施方式的封裝結構，其中塑膠封裝材料的一長度為L，塑膠封裝材料的一寬度為W，引腳的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。According to the packaging structure of the embodiment described in the preceding paragraph, a length of the plastic packaging material is L, a width of the plastic packaging material is W, and a maximum protruding length of the pin is L2, which can satisfy the following conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L.

依據前段所述實施方式的封裝結構，其中引腳的最大突出長度可為相同。According to the package structure of the embodiment described in the preceding paragraph, the maximum protruding length of the lead can be the same.

依據前段所述實施方式的封裝結構，其中導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料的材質可為環氧樹脂。According to the packaging structure of the embodiment described in the preceding paragraph, the material of the lead frame can be iron-nickel alloy or copper alloy, and the material of the plastic packaging material can be epoxy resin.

依據前段所述實施方式的封裝結構，其中電鍍面的數量可為至少四。According to the package structure of the embodiment described in the preceding paragraph, the number of plating surfaces may be at least four.

依據前段所述實施方式的封裝結構，其中引腳可為一梯狀引腳。According to the package structure of the embodiment described in the preceding paragraph, the lead may be a ladder lead.

依據前段所述實施方式的封裝結構，其中梯狀引腳靠近封裝結構之一上表面之一部分的一突出長度可小於梯狀引腳靠近封裝結構之一下表面之另一部分的一突出長度。According to the package structure of the embodiment described in the preceding paragraph, a protruding length of a part of the ladder-shaped pin close to an upper surface of the package structure may be smaller than a protruding length of another part of the ladder-shaped pin close to a lower surface of the package structure.

依據前段所述實施方式的封裝結構，其中梯狀引腳靠近封裝結構之下表面之部分的突出長度可小於梯狀引腳靠近封裝結構之上表面之另一部分的突出長度。According to the package structure of the embodiment described in the previous paragraph, the protruding length of the part of the ladder-shaped pin near the lower surface of the package structure may be smaller than the protruding length of the other part of the ladder-shaped pin near the upper surface of the package structure.

依據前段所述實施方式的封裝結構，其中引腳可為一突出引腳。According to the package structure of the embodiment described in the preceding paragraph, the lead may be a protruding lead.

依據前段所述實施方式的封裝結構，其中突出引腳靠近封裝結構之上表面之一部分的突出長度可小於突出引腳靠近封裝結構之下表面之另一部分的突出長度。According to the package structure of the embodiment described in the preceding paragraph, the protruding length of a part of the protruding pin near the upper surface of the package structure may be smaller than the protruding length of the other part of the protruding pin near the lower surface of the package structure.

請參照第1圖至第3圖，第1圖繪示依照本發明第一實施方式中封裝結構100的正面示意圖，第2圖繪示第1圖第一實施方式中封裝結構100的背面示意圖，第3圖繪示第1圖第一實施方式中封裝結構100的部分示意圖。由第1圖至第3圖可知，封裝結構100包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料130，其中導線架用以承載半導體晶片，塑膠封裝材料130設置於導線架上並覆蓋半導體晶片形成封裝結構100。Please refer to FIGS. 1 to 3. FIG. 1 is a schematic front view of the package structure 100 in the first embodiment of the present invention, and FIG. 2 is a schematic back view of the package structure 100 in the first embodiment in FIG. 1. FIG. 3 is a partial schematic diagram of the package structure 100 in the first embodiment in FIG. 1. It can be seen from FIGS. 1 to 3 that the package structure 100 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 130. The lead frame is used to carry the semiconductor chip and the plastic package The material 130 is disposed on the lead frame and covers the semiconductor chip to form the package structure 100.

進一步來說，導線架包含一晶片座110與複數引腳，其中各引腳可為一梯狀引腳120，梯狀引腳120設置於晶片座110的四周，且梯狀引腳120包含複數電鍍面121與至少一無電鍍面122。半導體晶片設置於導線架的晶片座110上，而塑膠封裝材料130設置於導線架上，且梯狀引腳120突出於塑膠封裝材料130的外緣。藉此，突出的梯狀引腳120可提升封裝結構100的側面可銲接面積。Furthermore, the lead frame includes a die holder 110 and a plurality of pins. Each pin can be a ladder-shaped pin 120. The ladder-shaped pins 120 are arranged around the die holder 110, and the ladder-shaped pins 120 include a plurality of pins. The plating surface 121 and at least one electroless plating surface 122. The semiconductor chip is set on the chip holder 110 of the lead frame, and the plastic packaging material 130 is set on the lead frame, and the ladder-shaped pins 120 protrude from the outer edge of the plastic packaging material 130. Thereby, the protruding ladder-shaped pins 120 can increase the solderable area of the side surface of the package structure 100.

第一實施方式中，可透過蝕刻步驟、模壓步驟、二道雷射步驟、電鍍步驟及切割步驟得到封裝結構100。詳細來說，蝕刻步驟為於導線架的下表面進行蝕刻，模壓步驟為將塑膠封裝材料130設置於導線架上並覆蓋半導體晶片，二道雷射步驟則是分別於導線架的上表面與下表面以雷射光束去除一部分塑膠封裝材料130，電鍍步驟為設置電鍍面121於雷射步驟後無覆蓋塑膠封裝材料130的導線架表面，接著再以切割步驟形成封裝結構100，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the first embodiment, the package structure 100 can be obtained through an etching step, a molding step, two laser steps, an electroplating step, and a cutting step. In detail, the etching step is to etch the lower surface of the lead frame, the molding step is to place the plastic packaging material 130 on the lead frame and cover the semiconductor chip, and the two laser steps are respectively on the upper surface and the lower surface of the lead frame. A laser beam is used to remove a part of the plastic packaging material 130 on the surface. The electroplating step is to set the plating surface 121 without covering the surface of the lead frame of the plastic packaging material 130 after the laser step, and then use a cutting step to form the packaging structure 100, where the laser step can It is more than two, which depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第2圖可知，塑膠封裝材料130的長度為L，塑膠封裝材料130的寬度為W，引腳（第一實施方式為梯狀引腳120）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料130可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各梯狀引腳120的最大突出長度可為相同。藉此，封裝結構100四周的梯狀引腳120的可銲接面積可具有一致性，使後續封裝結構100銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Figure 2 that the length of the plastic packaging material 130 is L, the width of the plastic packaging material 130 is W, and the maximum protrusion length of the lead (the ladder lead 120 in the first embodiment) is L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 130 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each ladder-shaped lead 120 can be the same. Thereby, the solderable area of the ladder-shaped pins 120 around the package structure 100 can be consistent, so that when the subsequent package structure 100 is soldered to a circuit board (not shown), it is not easy to produce a difference in soldering degree, and it can be installed stably On the circuit board.

具體而言，電鍍面121的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金(NiPdAu)、鎳鈀銀金(NiPdAgAu)或鎳金(NiAu)，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料130的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 121 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel palladium gold (NiPdAu), nickel palladium silver gold (NiPdAgAu) or nickel gold (NiAu), and the material of the lead frame can be It is an iron-nickel alloy or a copper alloy, and the material of the plastic packaging material 130 can be epoxy resin, but it is not limited to the above-mentioned material.

請參照第3圖與第4圖，第4圖繪示第1圖第一實施方式中封裝結構100的側面示意圖。由第3圖與第4圖可知，梯狀引腳120靠近封裝結構100之下表面102之一部分的一突出長度小於梯狀引腳120靠近封裝結構100之一上表面101之另一部分的一突出長度。進一步來說，梯狀引腳120中靠近封裝結構100之下表面102的部分未超出塑膠封裝材料130的邊緣。因此，透過第一實施方式的封裝結構100並不需要更換封裝外型圖(Package Outline Drawing, POD)的樣式，減少重新繪製封裝外型圖的程序。再者，因梯狀引腳120的厚度較薄，故可降低毛邊(burr)的產生。Please refer to FIG. 3 and FIG. 4. FIG. 4 is a schematic side view of the package structure 100 in the first embodiment of FIG. 1. FIG. It can be seen from FIGS. 3 and 4 that a protrusion length of a part of the ladder-shaped pin 120 close to the lower surface 102 of the package structure 100 is smaller than a protrusion of another part of the ladder-shaped pin 120 close to the upper surface 101 of the package structure 100 length. Furthermore, the part of the ladder-shaped pin 120 close to the lower surface 102 of the packaging structure 100 does not exceed the edge of the plastic packaging material 130. Therefore, through the package structure 100 of the first embodiment, it is not necessary to change the style of the package outline drawing (POD), which reduces the process of redrawing the package outline drawing. Furthermore, since the thickness of the stepped lead 120 is relatively thin, the generation of burrs can be reduced.

再者，因梯狀引腳120的最小突出長度貼齊塑膠封裝材料130的邊緣（即梯狀引腳120中靠近封裝結構100之下表面102的部分），並未縮減梯狀引腳120底部與電路板接觸的長度。藉此，第一實施方式中的梯狀引腳120可提升側面可銲錫的面積外，同時可維持梯狀引腳120底部與電路板的連接強度，以增加設置於電路板的壽命。Furthermore, since the minimum protruding length of the ladder-shaped pin 120 is aligned with the edge of the plastic packaging material 130 (that is, the part of the ladder-shaped pin 120 that is close to the lower surface 102 of the package structure 100), the bottom of the ladder-shaped pin 120 is not reduced. The length of contact with the circuit board. Thereby, the ladder-shaped pin 120 in the first embodiment can increase the area of the side surface that can be soldered while maintaining the connection strength between the bottom of the ladder-shaped pin 120 and the circuit board, so as to increase the life of the circuit board.

請配合參照第5圖與第6圖，第5圖繪示第1圖第一實施方式中封裝結構100於銲錫後的側面示意圖，第6圖繪示第5圖第一實施方式中封裝結構100於銲錫後的部分側面示意圖。電鍍面121的數量可為至少四，由第3圖至第6圖可知，第一實施方式中，電鍍面121的數量為五，但並不以此為限。接著，由第5圖與第6圖可知，封裝結構100的銲錫部140僅可設置於電鍍面121。藉此，當封裝結構100設置於電路板時，因側面可銲錫的面積增加，提升封裝結構100與電路板的銲接強度。Please refer to FIGS. 5 and 6 together. FIG. 5 shows a side view of the package structure 100 in the first embodiment in FIG. 1 after soldering, and FIG. 6 shows the package structure 100 in the first embodiment in FIG. 5 Partial side view after soldering. The number of the plating surfaces 121 can be at least four. It can be seen from FIGS. 3 to 6 that in the first embodiment, the number of the plating surfaces 121 is five, but it is not limited thereto. Next, it can be seen from FIGS. 5 and 6 that the solder portion 140 of the package structure 100 can only be provided on the plating surface 121. In this way, when the package structure 100 is disposed on a circuit board, the solderable area on the side surface is increased, which improves the welding strength between the package structure 100 and the circuit board.

請參照第7圖至第9圖，第7圖繪示依照本發明第二實施方式中封裝結構200的正面示意圖，第8圖繪示第7圖第二實施方式中封裝結構200的背面示意圖，第9圖繪示第7圖第二實施方式中封裝結構200的部分示意圖。由第7圖至第9圖可知，封裝結構200包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料230，其中導線架用以承載半導體晶片，塑膠封裝材料230設置於導線架上並覆蓋半導體晶片形成封裝結構200。Please refer to FIGS. 7-9. FIG. 7 is a schematic front view of the package structure 200 according to the second embodiment of the present invention, and FIG. 8 is a schematic back view of the package structure 200 in the second embodiment of FIG. 7. FIG. 9 is a partial schematic diagram of the package structure 200 in the second embodiment of FIG. 7. It can be seen from FIGS. 7 to 9 that the package structure 200 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 230. The lead frame is used to carry the semiconductor chip and the plastic package The material 230 is disposed on the lead frame and covers the semiconductor chip to form the package structure 200.

進一步來說，導線架包含一晶片座210與複數引腳，其中各引腳可為一梯狀引腳220，梯狀引腳220設置於晶片座210的四周，且梯狀引腳220包含複數電鍍面221與至少一無電鍍面222。半導體晶片設置於導線架的晶片座210上，而塑膠封裝材料230設置於導線架上，且梯狀引腳220突出於塑膠封裝材料230的外緣。藉此，突出的梯狀引腳220可提升封裝結構200的側面可銲接面積。Furthermore, the lead frame includes a die holder 210 and a plurality of pins. Each pin can be a ladder-shaped pin 220. The ladder-shaped pins 220 are arranged around the die holder 210, and the ladder-shaped pins 220 include a plurality of pins. The plating surface 221 and at least one electroless plating surface 222. The semiconductor chip is set on the chip holder 210 of the lead frame, and the plastic packaging material 230 is set on the lead frame, and the ladder-shaped pins 220 protrude from the outer edge of the plastic packaging material 230. In this way, the protruding ladder-shaped pins 220 can increase the solderable area of the side surface of the package structure 200.

第二實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構200。詳細來說，蝕刻步驟為於導線架的下表面進行蝕刻，模壓步驟為將塑膠封裝材料230設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料230與一部分導線架，電鍍步驟為設置電鍍面221於雷射步驟後無覆蓋塑膠封裝材料230的導線架表面，接著再以切割步驟形成封裝結構200，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the second embodiment, the package structure 200 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the lower surface of the lead frame, the molding step is to place the plastic packaging material 230 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. A part of the plastic packaging material 230 and a part of the lead frame, the electroplating step is to set the plating surface 221 after the laser step without covering the lead frame surface of the plastic packaging material 230, and then use a cutting step to form the packaging structure 200, where the laser step can be two It depends on the energy and parameters of the laser beam, but it is not limited to the above-mentioned process steps.

由第8圖可知，塑膠封裝材料230的長度為L，塑膠封裝材料230的寬度為W，引腳（第二實施方式為梯狀引腳220）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料230可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各梯狀引腳220的最大突出長度可為相同。藉此，封裝結構200四周的梯狀引腳220的可銲接面積可具有一致性，使後續封裝結構200銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Fig. 8 that the length of the plastic packaging material 230 is L, the width of the plastic packaging material 230 is W, and a maximum protruding length of the pin (the ladder pin 220 in the second embodiment) is L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 230 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each ladder-shaped lead 220 can be the same. Thereby, the solderable area of the stepped pins 220 around the package structure 200 can be consistent, so that when the subsequent package structure 200 is soldered to a circuit board (not shown in the figure), it is not easy to produce differences in soldering degree, and it can be installed stably On the circuit board.

具體而言，電鍍面221的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料230的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 221 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 230 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第9圖與第10圖，第10圖繪示第7圖第二實施方式中封裝結構200的側面示意圖。由第9圖與第10圖可知，梯狀引腳220靠近封裝結構200之一上表面201之一部分的一突出長度小於梯狀引腳220靠近封裝結構200之下表面202之另一部分的一突出長度。進一步來說，梯狀引腳220靠近封裝結構200之上表面201之部分未超出塑膠封裝材料230的邊緣。再者，因梯狀引腳220突出的寬度較寬，且梯狀引腳220的厚度較薄。因此，可降低毛邊的產生。Please refer to FIGS. 9 and 10. FIG. 10 is a schematic side view of the package structure 200 in the second embodiment in FIG. 7. It can be seen from FIGS. 9 and 10 that a protruding length of a part of the ladder-shaped pin 220 close to the upper surface 201 of the package structure 200 is smaller than that of another part of the ladder-shaped pin 220 close to the lower surface 202 of the package structure 200 length. Furthermore, the part of the ladder-shaped pin 220 close to the upper surface 201 of the packaging structure 200 does not exceed the edge of the plastic packaging material 230. Furthermore, because the protruding width of the ladder-shaped pin 220 is wider, and the thickness of the ladder-shaped pin 220 is relatively thin. Therefore, the generation of burrs can be reduced.

再者，因梯狀引腳220靠近封裝結構200之下表面202之另一部分的突出長度超出塑膠封裝材料230的邊緣。因此，第二實施方式中的梯狀引腳220可提升側面可銲錫的面積外，同時可維持梯狀引腳220底部與電路板的連接強度，以增加設置於電路板的壽命。Furthermore, the protruding length of another part of the ladder-shaped pin 220 close to the lower surface 202 of the packaging structure 200 exceeds the edge of the plastic packaging material 230. Therefore, the ladder-shaped pin 220 in the second embodiment can increase the area of the side surface that can be soldered, while maintaining the connection strength between the bottom of the ladder-shaped pin 220 and the circuit board, so as to increase the life of the circuit board.

請配合參照第11圖與第12圖，第11圖繪示第7圖第二實施方式中封裝結構200於銲錫後的側面示意圖，第12圖繪示第11圖第二實施方式中封裝結構200於銲錫後的部分側面示意圖。電鍍面221的數量可為至少四，由第9圖至第12圖可知，第二實施方式中，電鍍面221的數量為五，但並不以此為限。接著，由第11圖與第12圖可知，封裝結構200的銲錫部240僅可設置於電鍍面221。藉此，當封裝結構200設置於電路板時，因側面可銲錫的面積增加，提升封裝結構200與電路板的銲接強度。Please refer to FIGS. 11 and 12 together. FIG. 11 shows a side view of the package structure 200 in the second embodiment in FIG. 7 after soldering, and FIG. 12 shows the package structure 200 in the second embodiment in FIG. 11 Partial side view after soldering. The number of plating surfaces 221 can be at least four. It can be seen from FIGS. 9 to 12 that in the second embodiment, the number of plating surfaces 221 is five, but it is not limited thereto. Next, it can be seen from FIGS. 11 and 12 that the solder portion 240 of the package structure 200 can only be provided on the plating surface 221. In this way, when the package structure 200 is disposed on a circuit board, the solderable area on the side surface increases, which improves the soldering strength between the package structure 200 and the circuit board.

請參照第13圖至第15圖，第13圖繪示依照本發明第三實施方式中封裝結構300的正面示意圖，第14圖繪示第13圖第三實施方式中封裝結構300的背面示意圖，第15圖繪示第13圖第三實施方式中封裝結構300的部分示意圖。由第13圖至第15圖可知，封裝結構300包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料330，其中導線架用以承載半導體晶片，塑膠封裝材料330設置於導線架上並覆蓋半導體晶片形成封裝結構300。Please refer to FIGS. 13 to 15. FIG. 13 is a schematic front view of the package structure 300 according to the third embodiment of the present invention, and FIG. 14 is a schematic back view of the package structure 300 in the third embodiment of FIG. 13. FIG. 15 is a partial schematic diagram of the package structure 300 in the third embodiment in FIG. 13. It can be seen from FIGS. 13 to 15 that the package structure 300 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 330. The lead frame is used to carry the semiconductor chip and the plastic package The material 330 is disposed on the lead frame and covers the semiconductor chip to form the package structure 300.

進一步來說，導線架包含一晶片座310與複數引腳，其中各引腳可為一梯狀引腳320，梯狀引腳320設置於晶片座310的四周，且梯狀引腳320包含複數電鍍面321、至少一無電鍍面322及一凹陷部323，其中凹陷部323位於梯狀引腳320的一表面，且電鍍面321設置於梯狀引腳320與凹陷部323。半導體晶片設置於導線架的晶片座310上，而塑膠封裝材料330設置於導線架上，且梯狀引腳320突出於塑膠封裝材料330的外緣。藉此，突出的梯狀引腳320可提升封裝結構300的側面可銲接面積。Furthermore, the lead frame includes a die base 310 and a plurality of pins. Each pin can be a ladder-shaped pin 320. The ladder-shaped pins 320 are arranged around the die base 310, and the ladder-shaped pins 320 include a plurality of pins. The plating surface 321, at least one electroless plating surface 322 and a recess 323, wherein the recess 323 is located on a surface of the ladder pin 320, and the plating surface 321 is disposed on the ladder pin 320 and the recess 323. The semiconductor chip is arranged on the chip holder 310 of the lead frame, and the plastic packaging material 330 is arranged on the lead frame, and the ladder-shaped pins 320 protrude from the outer edge of the plastic packaging material 330. In this way, the protruding ladder pins 320 can increase the solderable area of the side surface of the package structure 300.

第三實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構300。詳細來說，蝕刻步驟為於導線架的下表面進行蝕刻，模壓步驟為將塑膠封裝材料330設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料330與一部分導線架，電鍍步驟為設置電鍍面321於雷射步驟後無覆蓋塑膠封裝材料330的導線架表面，接著再以切割步驟形成封裝結構300，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the third embodiment, the package structure 300 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the lower surface of the lead frame, the molding step is to place the plastic packaging material 330 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. A part of the plastic packaging material 330 and a part of the lead frame, the electroplating step is to set the plating surface 321 without covering the lead frame surface of the plastic packaging material 330 after the laser step, and then use a cutting step to form the packaging structure 300, where the laser step can be two It depends on the energy and parameters of the laser beam, but it is not limited to the above-mentioned process steps.

由第14圖可知，塑膠封裝材料330的長度為L，塑膠封裝材料330的寬度為W，引腳（第三實施方式為梯狀引腳320）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料330可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各梯狀引腳320的最大突出長度可為相同。藉此，封裝結構300四周的梯狀引腳320的可銲接面積可具有一致性，使後續封裝結構300銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Figure 14 that the length of the plastic packaging material 330 is L, the width of the plastic packaging material 330 is W, and a maximum protruding length of the pin (the ladder pin 320 in the third embodiment) is L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 330 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each ladder-shaped lead 320 may be the same. Thereby, the solderable area of the stepped pins 320 around the package structure 300 can be consistent, so that when the subsequent package structure 300 is soldered to a circuit board (not shown in the figure), it is not easy to produce a difference in soldering degree, and it can be installed stably On the circuit board.

具體而言，電鍍面321的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料330的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 321 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 330 may be epoxy resin, but is not limited to the above-mentioned material.

請參照第15圖與第16圖，第16圖繪示第13圖第三實施方式中封裝結構300的側面示意圖。由第15圖與第16圖可知，梯狀引腳320靠近封裝結構300之一上表面301之一部分的一突出長度小於梯狀引腳320靠近封裝結構300之下表面302之另一部分的一突出長度。進一步來說，梯狀引腳320的凹陷部323的凹陷深度可為梯狀引腳320靠近封裝結構300之下表面302的另一部分的厚度的一半。再者，因梯狀引腳320的厚度較薄，故可降低毛邊的產生。Please refer to FIGS. 15 and 16. FIG. 16 is a schematic side view of the package structure 300 in the third embodiment in FIG. 13. It can be seen from FIGS. 15 and 16, that a protruding length of a part of the ladder-shaped pin 320 close to the upper surface 301 of the package structure 300 is smaller than that of another part of the ladder-shaped pin 320 close to the lower surface 302 of the package structure 300 length. Furthermore, the recess depth of the recess 323 of the stepped lead 320 may be half the thickness of another part of the stepped lead 320 close to the lower surface 302 of the package structure 300. Furthermore, since the thickness of the stepped lead 320 is relatively thin, the generation of burrs can be reduced.

再者，因梯狀引腳320靠近封裝結構300之下表面302之另一部分的突出長度超出塑膠封裝材料330的邊緣。因此，第三實施方式中的梯狀引腳320可提升側面可銲錫的面積外，同時可維持梯狀引腳320底部與電路板的連接強度，以增加設置於電路板的壽命。Furthermore, the protruding length of another part of the ladder-shaped pin 320 close to the lower surface 302 of the packaging structure 300 exceeds the edge of the plastic packaging material 330. Therefore, the ladder-shaped pin 320 in the third embodiment can increase the area of the side surface that can be soldered while maintaining the connection strength between the bottom of the ladder-shaped pin 320 and the circuit board, so as to increase the life of the circuit board.

請配合參照第17圖與第18圖，第17圖繪示第13圖第三實施方式中封裝結構300於銲錫後的側面示意圖，第18圖繪示第17圖第三實施方式中封裝結構300於銲錫後的部分側面示意圖。電鍍面321的數量可為至少四，由第15圖至第18圖可知，第三實施方式中，電鍍面321的數量為八，但並不以此為限。接著，由第17圖與第18圖可知，封裝結構300的銲錫部340僅可設置於電鍍面321。藉此，當封裝結構300設置於電路板時，因側面可銲錫的面積增加，提升封裝結構300與電路板的銲接強度。Please refer to FIGS. 17 and 18 together. FIG. 17 shows a side view of the package structure 300 in the third embodiment in FIG. 13 after soldering. FIG. 18 shows the package structure 300 in the third embodiment in FIG. 17 Partial side view after soldering. The number of plating surfaces 321 can be at least four. As can be seen from FIGS. 15 to 18, in the third embodiment, the number of plating surfaces 321 is eight, but it is not limited thereto. Next, it can be seen from FIGS. 17 and 18 that the solder portion 340 of the package structure 300 can only be provided on the plating surface 321. Thereby, when the package structure 300 is disposed on the circuit board, the solderable area on the side surface is increased, and the welding strength between the package structure 300 and the circuit board is improved.

請參照第19圖至第21圖，第19圖繪示依照本發明第四實施方式中封裝結構400的正面示意圖，第20圖繪示第19圖第四實施方式中封裝結構400的背面示意圖，第21圖繪示第19圖第四實施方式中封裝結構400的部分示意圖。由第19圖至第21圖可知，封裝結構400包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料430，其中導線架用以承載半導體晶片，塑膠封裝材料430設置於導線架上並覆蓋半導體晶片形成封裝結構400。Please refer to FIGS. 19 to 21. FIG. 19 is a schematic front view of the package structure 400 according to the fourth embodiment of the present invention, and FIG. 20 is a back view of the package structure 400 in the fourth embodiment of FIG. 19. FIG. 21 is a partial schematic diagram of the package structure 400 in the fourth embodiment in FIG. 19. It can be seen from Figures 19 to 21 that the package structure 400 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 430. The lead frame is used to carry the semiconductor chip and the plastic package The material 430 is disposed on the lead frame and covers the semiconductor chip to form the package structure 400.

進一步來說，導線架包含一晶片座410與複數引腳，其中各引腳可為一梯狀引腳420，梯狀引腳420設置於晶片座410的四周，且梯狀引腳420包含複數電鍍面421與至少一無電鍍面422。半導體晶片設置於導線架的晶片座410上，而塑膠封裝材料430設置於導線架上，且梯狀引腳420突出於塑膠封裝材料430的外緣。藉此，突出的梯狀引腳420可提升封裝結構400的側面可銲接面積。Furthermore, the lead frame includes a die holder 410 and a plurality of pins. Each pin can be a ladder pin 420. The ladder pins 420 are arranged around the die holder 410, and the ladder pins 420 include a plurality of pins. The plating surface 421 and at least one electroless plating surface 422. The semiconductor chip is arranged on the chip holder 410 of the lead frame, and the plastic packaging material 430 is arranged on the lead frame, and the ladder-shaped pins 420 protrude from the outer edge of the plastic packaging material 430. In this way, the protruding ladder-shaped pins 420 can increase the solderable area of the side surface of the package structure 400.

第四實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構400。詳細來說，蝕刻步驟為於導線架的上表面進行蝕刻，模壓步驟為將塑膠封裝材料430設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料430，電鍍步驟為設置電鍍面421於雷射步驟後無覆蓋塑膠封裝材料430的導線架表面，接著再以切割步驟形成封裝結構400，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the fourth embodiment, the package structure 400 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the upper surface of the lead frame, the molding step is to place the plastic packaging material 430 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. For a part of the plastic packaging material 430, the electroplating step is to set the plating surface 421 after the laser step without covering the surface of the lead frame of the plastic packaging material 430, and then use a cutting step to form the packaging structure 400, where the laser step can be more than two. It depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第20圖可知，塑膠封裝材料430的長度為L，塑膠封裝材料430的寬度為W，引腳（第四實施方式為梯狀引腳420）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料430可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各梯狀引腳420的最大突出長度可為相同。藉此，封裝結構400四周的梯狀引腳420的可銲接面積可具有一致性，使後續封裝結構400銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Fig. 20 that the length of the plastic packaging material 430 is L, the width of the plastic packaging material 430 is W, and the pin (the ladder pin 420 in the fourth embodiment) has a maximum protruding length of L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 430 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each ladder-shaped lead 420 can be the same. Thereby, the solderable area of the stepped pins 420 around the package structure 400 can be consistent, so that when the subsequent package structure 400 is soldered to a circuit board (not shown in the figure), it is not easy to produce differences in soldering degree, and it can be installed stably On the circuit board.

具體而言，電鍍面421的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料430的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 421 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 430 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第21圖與第22圖，第22圖繪示第19圖第四實施方式中封裝結構400的側面示意圖。由第21圖與第22圖可知，梯狀引腳420靠近封裝結構400之一上表面401之一部分的一突出長度小於梯狀引腳420靠近封裝結構400之下表面402之另一部分的一突出長度。再者，因梯狀引腳420突出的寬度較寬，且梯狀引腳420的厚度較薄。因此，可降低毛邊的產生。Please refer to FIGS. 21 and 22. FIG. 22 is a schematic side view of the package structure 400 in the fourth embodiment in FIG. 19. It can be seen from FIGS. 21 and 22 that a protruding length of a part of the ladder-shaped pin 420 close to the upper surface 401 of the package structure 400 is smaller than that of another part of the ladder-shaped pin 420 close to the lower surface 402 of the package structure 400 length. Furthermore, because the protruding width of the ladder-shaped pin 420 is wider, and the thickness of the ladder-shaped pin 420 is relatively thin. Therefore, the generation of burrs can be reduced.

再者，因梯狀引腳420靠近封裝結構400之下表面402之另一部分的突出長度超出塑膠封裝材料430的邊緣。因此，第四實施方式中的梯狀引腳420可提升側面可銲錫的面積外，同時可維持梯狀引腳420底部與電路板的連接強度，以增加設置於電路板的壽命。Furthermore, the protruding length of the other part of the ladder-shaped pin 420 close to the lower surface 402 of the packaging structure 400 exceeds the edge of the plastic packaging material 430. Therefore, the ladder-shaped pin 420 in the fourth embodiment can increase the area of the side surface that can be soldered while maintaining the connection strength between the bottom of the ladder-shaped pin 420 and the circuit board, so as to increase the life of the circuit board.

請配合參照第23圖與第24圖，第23圖繪示第19圖第四實施方式中封裝結構400於銲錫後的側面示意圖，第24圖繪示第23圖第四實施方式中封裝結構400於銲錫後的部分側面示意圖。電鍍面421的數量可為至少四，由第21圖至第24圖可知，第四實施方式中，電鍍面421的數量為六，但並不以此為限。接著，由第23圖與第24圖可知，封裝結構400的銲錫部440僅可設置於電鍍面421。藉此，當封裝結構400設置於電路板時，因側面可銲錫的面積增加，提升封裝結構400與電路板的銲接強度。Please refer to FIG. 23 and FIG. 24 together. FIG. 23 shows a side view of the package structure 400 in the fourth embodiment in FIG. 19 after soldering. FIG. 24 shows the package structure 400 in the fourth embodiment in FIG. 23. Partial side view after soldering. The number of plating surfaces 421 may be at least four. It can be seen from FIGS. 21 to 24 that in the fourth embodiment, the number of plating surfaces 421 is six, but it is not limited thereto. Next, it can be seen from FIGS. 23 and 24 that the solder portion 440 of the package structure 400 can only be provided on the plating surface 421. Thereby, when the package structure 400 is disposed on the circuit board, the solderable area on the side surface is increased, and the welding strength between the package structure 400 and the circuit board is improved.

請參照第25圖至第27圖，第25圖繪示依照本發明第五實施方式中封裝結構500的正面示意圖，第26圖繪示第25圖第五實施方式中封裝結構500的背面示意圖，第27圖繪示第25圖第五實施方式中封裝結構500的部分示意圖。由第25圖至第27圖可知，封裝結構500包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料530，其中導線架用以承載半導體晶片，塑膠封裝材料530設置於導線架上並覆蓋半導體晶片形成封裝結構500。Please refer to FIGS. 25 to 27. FIG. 25 is a schematic front view of the package structure 500 according to the fifth embodiment of the present invention, and FIG. 26 is a back view of the package structure 500 in the fifth embodiment of FIG. 25. FIG. 27 is a partial schematic diagram of the package structure 500 in the fifth embodiment in FIG. 25. FIG. It can be seen from FIGS. 25 to 27 that the package structure 500 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 530. The lead frame is used to carry the semiconductor chip and the plastic package The material 530 is disposed on the lead frame and covers the semiconductor chip to form the package structure 500.

進一步來說，導線架包含一晶片座510與複數引腳，其中各引腳可為一梯狀引腳520，梯狀引腳520設置於晶片座510的四周，且梯狀引腳520包含複數電鍍面521與至少一無電鍍面522。半導體晶片設置於導線架的晶片座510上，而塑膠封裝材料530設置於導線架上，且梯狀引腳520突出於塑膠封裝材料530的外緣。藉此，突出的梯狀引腳520可提升封裝結構500的側面可銲接面積。Furthermore, the lead frame includes a die holder 510 and a plurality of pins. Each pin can be a ladder pin 520. The ladder pins 520 are arranged around the die holder 510, and the ladder pins 520 include a plurality of pins. The plating surface 521 and at least one electroless plating surface 522. The semiconductor chip is set on the chip holder 510 of the lead frame, and the plastic packaging material 530 is set on the lead frame, and the ladder-shaped pins 520 protrude from the outer edge of the plastic packaging material 530. In this way, the protruding stepped pins 520 can increase the solderable area of the side surface of the package structure 500.

第五實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構500。詳細來說，蝕刻步驟為於導線架的上表面進行蝕刻，模壓步驟為將塑膠封裝材料530設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料530與一部分導線架，電鍍步驟為設置電鍍面521於雷射步驟後無覆蓋塑膠封裝材料530的導線架表面，接著再以切割步驟形成封裝結構500，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the fifth embodiment, the package structure 500 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the upper surface of the lead frame, the molding step is to place the plastic packaging material 530 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. A part of the plastic packaging material 530 and a part of the lead frame, the electroplating step is to set the plating surface 521 on the surface of the lead frame without covering the plastic packaging material 530 after the laser step, and then use a cutting step to form the packaging structure 500, where the laser step can be two It depends on the energy and parameters of the laser beam, but it is not limited to the above-mentioned process steps.

由第26圖可知，塑膠封裝材料530的長度為L，塑膠封裝材料530的寬度為W，引腳（第五實施方式為梯狀引腳520）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料530可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各梯狀引腳520的最大突出長度可為相同。藉此，封裝結構500四周的梯狀引腳520的可銲接面積可具有一致性，使後續封裝結構500銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Fig. 26 that the length of the plastic packaging material 530 is L, the width of the plastic packaging material 530 is W, and the pin (the ladder pin 520 in the fifth embodiment) has a maximum protruding length of L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 530 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each ladder-shaped pin 520 can be the same. Thereby, the solderable area of the stepped pins 520 around the package structure 500 can be consistent, so that when the subsequent package structure 500 is soldered to a circuit board (not shown in the figure), it is not easy to produce differences in soldering degree, and can be installed stably On the circuit board.

具體而言，電鍍面521的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料530的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 521 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 530 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第27圖與第28圖，第28圖繪示第25圖第五實施方式中封裝結構500的側面示意圖。由第27圖與第28圖可知，梯狀引腳520靠近封裝結構500之一上表面501之一部分的一突出長度小於梯狀引腳520靠近封裝結構500之下表面502之另一部分的一突出長度。進一步來說，梯狀引腳520靠近封裝結構500之上表面501之部分未超出塑膠封裝材料530的邊緣，且梯狀引腳520靠近封裝結構500之下表面502之另一部分的突出長度至梯狀引腳520靠近封裝結構500之上表面501之部分的突出長度漸縮。再者，因梯狀引腳520突出的寬度較寬，且梯狀引腳520的厚度較薄。因此，可降低毛邊的產生。Please refer to FIG. 27 and FIG. 28. FIG. 28 is a side view of the package structure 500 in the fifth embodiment in FIG. 25. It can be seen from FIGS. 27 and 28 that a protrusion length of a part of the ladder pin 520 close to the upper surface 501 of the package structure 500 is smaller than that of another part of the ladder pin 520 close to the lower surface 502 of the package structure 500 length. Furthermore, the part of the ladder-shaped pin 520 close to the upper surface 501 of the package structure 500 does not exceed the edge of the plastic packaging material 530, and the protruding length of the other part of the ladder-shaped pin 520 close to the lower surface 502 of the package structure 500 is as high as The protruding length of the portion of the shaped lead 520 close to the upper surface 501 of the package structure 500 is gradually reduced. Furthermore, because the protruding width of the ladder-shaped pin 520 is relatively wide, and the thickness of the ladder-shaped pin 520 is relatively thin. Therefore, the generation of burrs can be reduced.

再者，因梯狀引腳520靠近封裝結構500之下表面502之另一部分的突出長度超出塑膠封裝材料530的邊緣。因此，第五實施方式中的梯狀引腳520可提升側面可銲錫的面積外，同時可維持梯狀引腳520底部與電路板的連接強度，以增加設置於電路板的壽命。Furthermore, the protruding length of another part of the ladder-shaped pin 520 close to the lower surface 502 of the packaging structure 500 exceeds the edge of the plastic packaging material 530. Therefore, the ladder-shaped pin 520 in the fifth embodiment can increase the area of the side surface that can be soldered while maintaining the connection strength between the bottom of the ladder-shaped pin 520 and the circuit board, so as to increase the life of the circuit board.

請配合參照第29圖與第30圖，第29圖繪示第25圖第五實施方式中封裝結構500於銲錫後的側面示意圖，第30圖繪示第29圖第五實施方式中封裝結構500於銲錫後的部分側面示意圖。電鍍面521的數量可為至少四，由第27圖至第30圖可知，第五實施方式中，電鍍面521的數量為七，但並不以此為限。接著，由第29圖與第30圖可知，封裝結構500的銲錫部540僅可設置於電鍍面521。藉此，當封裝結構500設置於電路板時，因側面可銲錫的面積增加，提升封裝結構500與電路板的銲接強度。Please refer to Figure 29 and Figure 30 together. Figure 29 shows a side view of the package structure 500 in the fifth embodiment in Figure 25 after soldering. Figure 30 shows the package structure 500 in Figure 29 in the fifth embodiment. Partial side view after soldering. The number of plating surfaces 521 can be at least four. It can be seen from FIGS. 27 to 30 that in the fifth embodiment, the number of plating surfaces 521 is seven, but it is not limited thereto. Next, it can be seen from FIGS. 29 and 30 that the solder portion 540 of the package structure 500 can only be provided on the plating surface 521. In this way, when the package structure 500 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the welding strength between the package structure 500 and the circuit board.

請參照第31圖至第33圖，第31圖繪示依照本發明第六實施方式中封裝結構600的正面示意圖，第32圖繪示第31圖第六實施方式中封裝結構600的背面示意圖，第33圖繪示第31圖第六實施方式中封裝結構600的部分示意圖。由第31圖至第33圖可知，封裝結構600包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料630，其中導線架用以承載半導體晶片，塑膠封裝材料630設置於導線架上並覆蓋半導體晶片形成封裝結構600。Please refer to FIGS. 31 to 33. FIG. 31 is a schematic front view of the package structure 600 according to the sixth embodiment of the present invention, and FIG. 32 is a schematic back view of the package structure 600 in the sixth embodiment of FIG. 31. FIG. 33 is a partial schematic diagram of the package structure 600 in the sixth embodiment in FIG. 31. It can be seen from FIGS. 31 to 33 that the package structure 600 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 630. The lead frame is used to carry the semiconductor chip and the plastic package The material 630 is disposed on the lead frame and covers the semiconductor chip to form the package structure 600.

進一步來說，導線架包含一晶片座610與複數引腳，其中各引腳可為一梯狀引腳620，梯狀引腳620設置於晶片座610的四周，且梯狀引腳620包含複數電鍍面621、至少一無電鍍面622及一凹陷部623，其中凹陷部623位於梯狀引腳620的一表面，且電鍍面621設置於梯狀引腳620與凹陷部623。半導體晶片設置於導線架的晶片座610上，而塑膠封裝材料630設置於導線架上，且梯狀引腳620突出於塑膠封裝材料630的外緣。藉此，突出的梯狀引腳620可提升封裝結構600的側面可銲接面積。Furthermore, the lead frame includes a die holder 610 and a plurality of pins. Each pin can be a ladder pin 620. The ladder pins 620 are arranged around the die holder 610, and the ladder pins 620 include a plurality of pins. The plating surface 621, at least one electroless plating surface 622 and a recess 623, wherein the recess 623 is located on a surface of the ladder pin 620, and the plating surface 621 is disposed on the ladder pin 620 and the recess 623. The semiconductor chip is set on the chip holder 610 of the lead frame, and the plastic packaging material 630 is set on the lead frame, and the ladder-shaped pins 620 protrude from the outer edge of the plastic packaging material 630. In this way, the protruding ladder-shaped pins 620 can increase the solderable area of the side surface of the package structure 600.

第六實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構600。詳細來說，蝕刻步驟為於導線架的上表面進行蝕刻，模壓步驟為將塑膠封裝材料630設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料630與一部分導線架，電鍍步驟為設置電鍍面621於雷射步驟後無覆蓋塑膠封裝材料630的導線架表面，接著再以切割步驟形成封裝結構600，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the sixth embodiment, the package structure 600 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the upper surface of the lead frame, the molding step is to place the plastic packaging material 630 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. A part of the plastic packaging material 630 and a part of the lead frame. The electroplating step is to set the plating surface 621 on the surface of the lead frame without covering the plastic packaging material 630 after the laser step, and then use a cutting step to form the packaging structure 600, where the laser step can be two It depends on the energy and parameters of the laser beam, but it is not limited to the above-mentioned process steps.

由第32圖可知，塑膠封裝材料630的長度為L，塑膠封裝材料630的寬度為W，引腳（第六實施方式為梯狀引腳620）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料630可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各梯狀引腳620的最大突出長度可為相同。藉此，封裝結構600四周的梯狀引腳620的可銲接面積可具有一致性，使後續封裝結構600銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Fig. 32 that the length of the plastic packaging material 630 is L, the width of the plastic packaging material 630 is W, and a maximum protruding length of the pin (the ladder pin 620 in the sixth embodiment) is L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 630 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each ladder-shaped lead 620 may be the same. Thereby, the solderable area of the ladder-shaped pins 620 around the package structure 600 can be consistent, so that the subsequent package structure 600 is less likely to have differences in soldering degree when soldering to a circuit board (not shown in the figure), and it can be installed stably On the circuit board.

具體而言，電鍍面621的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料630的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 621 can be tin alloy or nickel-gold alloy, where the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 630 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第33圖與第34圖，第34圖繪示第31圖第六實施方式中封裝結構600的側面示意圖。由第33圖與第34圖可知，梯狀引腳620靠近封裝結構600之一上表面601之一部分的一突出長度小於梯狀引腳620靠近封裝結構600之下表面602之另一部分的一突出長度。進一步來說，梯狀引腳620靠近封裝結構600之上表面601之部分未超出塑膠封裝材料630的邊緣，且梯狀引腳620靠近封裝結構600之下表面602之另一部分的突出長度至梯狀引腳620靠近封裝結構600之上表面602之部分的突出長度漸縮。再者，因梯狀引腳620突出的寬度較寬，且梯狀引腳620的厚度較薄。因此，可降低毛邊的產生。再者，梯狀引腳620的凹陷部623的凹陷深度可為梯狀引腳620靠近封裝結構600之下表面602的另一部分的厚度的一半。Please refer to FIG. 33 and FIG. 34. FIG. 34 is a side view of the package structure 600 in the sixth embodiment in FIG. 31. It can be seen from FIGS. 33 and 34 that a protruding length of a part of the ladder-shaped pin 620 close to the upper surface 601 of the package structure 600 is smaller than that of another part of the ladder-shaped pin 620 close to the lower surface 602 of the package structure 600 length. Furthermore, the part of the ladder-shaped pin 620 close to the upper surface 601 of the package structure 600 does not exceed the edge of the plastic packaging material 630, and the protruding length of the other part of the ladder-shaped pin 620 close to the lower surface 602 of the package structure 600 is as long as The protruding length of the portion of the shaped lead 620 close to the upper surface 602 of the package structure 600 is tapered. Furthermore, because the protruding width of the ladder-shaped pin 620 is wider, and the thickness of the ladder-shaped pin 620 is relatively thin. Therefore, the generation of burrs can be reduced. Furthermore, the recess depth of the recess 623 of the stepped lead 620 may be half the thickness of another part of the stepped lead 620 close to the lower surface 602 of the package structure 600.

再者，因梯狀引腳620靠近封裝結構600之下表面602之另一部分的突出長度超出塑膠封裝材料630的邊緣。因此，第六實施方式中的梯狀引腳620可提升側面可銲錫的面積外，同時可維持梯狀引腳620底部與電路板的連接強度，以增加設置於電路板的壽命。Furthermore, the protruding length of another part of the ladder-shaped pin 620 close to the lower surface 602 of the packaging structure 600 exceeds the edge of the plastic packaging material 630. Therefore, the ladder-shaped pin 620 in the sixth embodiment can increase the area of the side surface that can be soldered while maintaining the connection strength between the bottom of the ladder-shaped pin 620 and the circuit board, so as to increase the life of the circuit board.

請配合參照第35圖與第36圖，第35圖繪示第31圖第六實施方式中封裝結構600於銲錫後的側面示意圖，第36圖繪示第35圖第六實施方式中封裝結構600於銲錫後的部分側面示意圖。電鍍面621的數量可為至少四，由第33圖至第36圖可知，第六實施方式中，電鍍面621的數量為十，但並不以此為限。接著，由第35圖與第36圖可知，封裝結構600的銲錫部640僅可設置於電鍍面621。藉此，當封裝結構600設置於電路板時，因側面可銲錫的面積增加，提升封裝結構600與電路板的銲接強度。Please refer to FIGS. 35 and 36 together. FIG. 35 shows a side view of the package structure 600 in the sixth embodiment in FIG. 31 after soldering, and FIG. 36 shows the package structure 600 in the sixth embodiment in FIG. 35 Partial side view after soldering. The number of electroplating surfaces 621 may be at least four. It can be seen from FIGS. 33 to 36 that in the sixth embodiment, the number of electroplating surfaces 621 is ten, but it is not limited thereto. Next, it can be seen from FIGS. 35 and 36 that the solder portion 640 of the package structure 600 can only be provided on the plating surface 621. Thereby, when the package structure 600 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the welding strength between the package structure 600 and the circuit board.

請參照第37圖至第39圖，第37圖繪示依照本發明第七實施方式中封裝結構700的正面示意圖，第38圖繪示第37圖第七實施方式中封裝結構700的背面示意圖，第39圖繪示第37圖第七實施方式中封裝結構700的部分示意圖。由第37圖至第39圖可知，封裝結構700包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料730，其中導線架用以承載半導體晶片，塑膠封裝材料730設置於導線架上並覆蓋半導體晶片形成封裝結構700。Please refer to FIGS. 37 to 39. FIG. 37 is a schematic front view of the package structure 700 according to the seventh embodiment of the present invention, and FIG. 38 is a back view of the package structure 700 in the seventh embodiment of FIG. 37. FIG. 39 is a partial schematic diagram of the package structure 700 in the seventh embodiment in FIG. 37. FIG. It can be seen from FIGS. 37 to 39 that the package structure 700 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 730. The lead frame is used to carry the semiconductor chip and the plastic package The material 730 is disposed on the lead frame and covers the semiconductor chip to form the package structure 700.

進一步來說，導線架包含一晶片座710與複數引腳，其中各引腳可為一突出引腳720，突出引腳720設置於晶片座710的四周，且突出引腳720包含複數電鍍面721與至少一無電鍍面722，其中電鍍面721設置於突出引腳720。半導體晶片設置於導線架的晶片座710上，而塑膠封裝材料730設置於導線架上，且突出引腳720突出於塑膠封裝材料730的外緣。藉此，突出引腳720可提升封裝結構700的側面可銲接面積。Furthermore, the lead frame includes a die holder 710 and a plurality of pins, where each pin can be a protruding pin 720, the protruding pin 720 is disposed around the die holder 710, and the protruding pin 720 includes a plurality of plating surfaces 721 And at least one electroless plating surface 722, wherein the plating surface 721 is disposed on the protruding pin 720. The semiconductor chip is set on the chip holder 710 of the lead frame, and the plastic packaging material 730 is set on the lead frame, and the protruding pins 720 protrude from the outer edge of the plastic packaging material 730. In this way, the protruding pins 720 can increase the solderable area of the side surface of the package structure 700.

第七實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構700。詳細來說，蝕刻步驟為於導線架的上表面進行蝕刻，模壓步驟為將塑膠封裝材料730設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料730，電鍍步驟為設置電鍍面721於雷射步驟後無覆蓋塑膠封裝材料730的導線架表面，接著再以切割步驟形成封裝結構700，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the seventh embodiment, the package structure 700 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the upper surface of the lead frame, the molding step is to place the plastic packaging material 730 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. For a part of the plastic packaging material 730, the electroplating step is to set the plating surface 721 without covering the surface of the lead frame of the plastic packaging material 730 after the laser step, and then use a cutting step to form the packaging structure 700, where the laser step can be more than two. It depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第38圖可知，塑膠封裝材料730的長度為L，塑膠封裝材料730的寬度為W，引腳（第七實施方式為突出引腳720）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料730可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各突出引腳720的最大突出長度可為相同。藉此，封裝結構700四周的突出引腳720的可銲接面積可具有一致性，使後續封裝結構700銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Fig. 38 that the length of the plastic packaging material 730 is L, the width of the plastic packaging material 730 is W, and the pin (the protruding pin 720 in the seventh embodiment) has a maximum protruding length of L2, which can meet the following conditions ：W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 730 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each protruding pin 720 can be the same. Thereby, the solderable area of the protruding pins 720 around the package structure 700 can be consistent, so that when the subsequent package structure 700 is soldered to a circuit board (not shown in the figure), it is not easy to produce differences in soldering degree, and it can be firmly placed on Circuit board.

具體而言，電鍍面721的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料730的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 721 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 730 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第39圖與第40圖，第40圖繪示第37圖第七實施方式中封裝結構700的側面示意圖。由第39圖與第40圖可知，突出引腳720靠近封裝結構700之一上表面701之一部分的一突出長度小於突出引腳720靠近封裝結構700之下表面702之另一部分的一突出長度。再者，因突出引腳720突出的寬度較寬，且突出引腳720的厚度較薄。因此，可降低毛邊的產生。Please refer to FIG. 39 and FIG. 40. FIG. 40 is a side view of the package structure 700 in the seventh embodiment in FIG. 37. It can be seen from FIGS. 39 and 40 that a protruding length of a part of the protruding pin 720 close to the upper surface 701 of the package structure 700 is smaller than a protruding length of another part of the protruding pin 720 close to the lower surface 702 of the package structure 700. Furthermore, the protruding pin 720 has a wider protruding width, and the protruding pin 720 has a thinner thickness. Therefore, the generation of burrs can be reduced.

由第38圖可知，突出引腳720突出塑膠封裝材料730的邊緣之外，突出引腳720於封裝結構700的下表面702更包含一部分的電鍍面721。請配合參照第41圖，第41圖繪示第40圖第七實施方式中封裝結構700沿剖線41-41的剖面示意圖。進一步來說，由第41圖可得知，突出引腳720於突出塑膠封裝材料730與塑膠封裝材料730所覆蓋的部分呈現類似鷗翼形(gull-wing shape)。藉此，突出引腳720可具有一定韌性以增加板級(board level)的可靠度，當塑膠封裝材料730覆蓋封裝結構700時，突出引腳720更具有機械強度。再者，提升突出引腳720的側面可銲錫面積的同時，更可保留半導體晶片與突出引腳720之間銲線的連接強度。It can be seen from FIG. 38 that the protruding pins 720 protrude beyond the edge of the plastic packaging material 730, and the protruding pins 720 further include a part of the plating surface 721 on the lower surface 702 of the packaging structure 700. Please refer to FIG. 41 together. FIG. 41 is a schematic cross-sectional view of the package structure 700 in the seventh embodiment in FIG. 40 along the section line 41-41. Furthermore, it can be seen from FIG. 41 that the protruding pin 720 is similar to a gull-wing shape at the portion covered by the protruding plastic packaging material 730 and the plastic packaging material 730. Thereby, the protruding pins 720 can have a certain degree of toughness to increase the reliability of the board level. When the plastic packaging material 730 covers the packaging structure 700, the protruding pins 720 have more mechanical strength. Furthermore, while increasing the solderable area of the side surface of the protruding pin 720, the connection strength of the bonding wire between the semiconductor chip and the protruding pin 720 can be maintained.

請配合參照第42圖與第43圖，第42圖繪示第37圖第七實施方式中封裝結構700於銲錫後的側面示意圖，第43圖繪示第42圖第七實施方式中封裝結構700於銲錫後的部分側面示意圖。電鍍面721的數量可為至少四，由第42圖至第43圖可知，第七實施方式中，電鍍面721的數量為七，但並不以此為限。接著，由第42圖與第43圖可知，封裝結構700的銲錫部740僅可設置於電鍍面721。藉此，當封裝結構700設置於電路板時，因側面可銲錫的面積增加，提升封裝結構700與電路板的銲接強度。Please refer to FIGS. 42 and 43 together. FIG. 42 shows a side view of the package structure 700 in the seventh embodiment in FIG. 37 after soldering, and FIG. 43 shows the package structure 700 in the seventh embodiment in FIG. 42 Partial side view after soldering. The number of plating surfaces 721 may be at least four. It can be seen from FIGS. 42 to 43 that, in the seventh embodiment, the number of plating surfaces 721 is seven, but it is not limited thereto. Next, it can be seen from FIGS. 42 and 43 that the solder portion 740 of the package structure 700 can only be provided on the plating surface 721. Thereby, when the package structure 700 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the soldering strength of the package structure 700 and the circuit board.

請參照第44圖至第46圖，第44圖繪示依照本發明第八實施方式中封裝結構800的正面示意圖，第45圖繪示第44圖第八實施方式中封裝結構800的背面示意圖，第46圖繪示第44圖第八實施方式中封裝結構800的部分示意圖。由第44圖至第46圖可知，封裝結構800包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料830，其中導線架用以承載半導體晶片，塑膠封裝材料830設置於導線架上並覆蓋半導體晶片形成封裝結構800。Please refer to FIGS. 44 to 46. FIG. 44 is a schematic front view of the package structure 800 according to the eighth embodiment of the present invention, and FIG. 45 is a back view of the package structure 800 in the eighth embodiment of FIG. 44. FIG. 46 is a partial schematic diagram of the package structure 800 in the eighth embodiment in FIG. 44. FIG. It can be seen from Figures 44 to 46 that the package structure 800 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 830. The lead frame is used to carry the semiconductor chip and the plastic package The material 830 is disposed on the lead frame and covers the semiconductor chip to form the package structure 800.

進一步來說，導線架包含一晶片座810與複數引腳，其中各引腳可為一梯狀引腳820，梯狀引腳820設置於晶片座810的四周，且梯狀引腳820包含複數電鍍面821與至少一無電鍍面822。半導體晶片設置於導線架的晶片座810上，而塑膠封裝材料830設置於導線架上，且梯狀引腳820突出於塑膠封裝材料830的外緣。藉此，突出的梯狀引腳820可提升封裝結構800的側面可銲接面積。Furthermore, the lead frame includes a die holder 810 and a plurality of pins. Each pin can be a ladder pin 820. The ladder pins 820 are arranged around the die holder 810, and the ladder pins 820 include a plurality of pins. The plating surface 821 and at least one electroless plating surface 822. The semiconductor chip is set on the chip holder 810 of the lead frame, and the plastic packaging material 830 is set on the lead frame, and the ladder-shaped pins 820 protrude from the outer edge of the plastic packaging material 830. Thereby, the protruding ladder-shaped pins 820 can increase the solderable area of the side surface of the package structure 800.

第八實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構800。詳細來說，蝕刻步驟為於導線架的上表面進行蝕刻，模壓步驟為將塑膠封裝材料830設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料830，電鍍步驟為設置電鍍面821於雷射步驟後無覆蓋塑膠封裝材料830的導線架表面，接著再以切割步驟形成封裝結構800，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the eighth embodiment, the package structure 800 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the upper surface of the lead frame, the molding step is to place the plastic packaging material 830 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. Part of the plastic packaging material 830, the electroplating step is to set the electroplating surface 821 after the laser step without covering the surface of the lead frame of the plastic packaging material 830, and then use a cutting step to form the packaging structure 800, where the laser step can be more than two. It depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第45圖可知，塑膠封裝材料830的長度為L，塑膠封裝材料830的寬度為W，引腳（第八實施方式為梯狀引腳820）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料830可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各梯狀引腳820的最大突出長度可為相同。藉此，封裝結構800四周的梯狀引腳820的可銲接面積可具有一致性，使後續封裝結構800銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Figure 45 that the length of the plastic packaging material 830 is L, the width of the plastic packaging material 830 is W, and a maximum protruding length of the pin (the ladder pin 820 in the eighth embodiment) is L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 830 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each ladder-shaped lead 820 can be the same. Thereby, the solderable area of the ladder-shaped pins 820 around the package structure 800 can be consistent, so that when the subsequent package structure 800 is soldered to a circuit board (not shown), it is not easy to produce a difference in soldering degree, and it can be installed stably On the circuit board.

具體而言，電鍍面821的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料830的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 821 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 830 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第46圖與第47圖，第47圖繪示第44圖第八實施方式中封裝結構800的側面示意圖。由第46圖與第47圖可知，梯狀引腳820靠近封裝結構800之一上表面801之一部分的一突出長度小於梯狀引腳820靠近封裝結構800之下表面802之另一部分的一突出長度。再者，因梯狀引腳820突出的寬度較寬，且梯狀引腳820的厚度較薄。因此，可降低毛邊的產生。Please refer to FIGS. 46 and 47. FIG. 47 is a side view of the package structure 800 in the eighth embodiment in FIG. 44. It can be seen from FIGS. 46 and 47 that a protruding length of a part of the ladder-shaped pin 820 close to the upper surface 801 of the package structure 800 is smaller than that of another part of the ladder-shaped pin 820 close to the lower surface 802 of the package structure 800 length. Furthermore, because the protruding width of the ladder-shaped pin 820 is wider, and the thickness of the ladder-shaped pin 820 is relatively thin. Therefore, the generation of burrs can be reduced.

請配合參照第48圖，第48圖繪示第47圖第八實施方式中封裝結構800沿剖線48-48的剖面示意圖。由第48圖可得知，梯狀引腳820於突出塑膠封裝材料830與塑膠封裝材料830所覆蓋的部分呈現類似鷗翼形。藉此，梯狀引腳820可具有一定韌性以增加板級的可靠度，當塑膠封裝材料830覆蓋封裝結構800時，梯狀引腳820更具有機械強度。再者，提升梯狀引腳820的側面可銲錫面積的同時，更可保留半導體晶片與梯狀引腳820之間銲線的連接強度。Please refer to FIG. 48 in conjunction. FIG. 48 is a schematic cross-sectional view of the package structure 800 in the eighth embodiment in FIG. 47 along the section line 48-48. It can be seen from FIG. 48 that the ladder-shaped pin 820 is similar to a gull-wing shape at the part covered by the protruding plastic packaging material 830 and the plastic packaging material 830. Thereby, the ladder-shaped pins 820 can have a certain degree of toughness to increase the reliability of the board level. When the plastic packaging material 830 covers the packaging structure 800, the ladder-shaped pins 820 have more mechanical strength. Furthermore, while increasing the solderable area of the side surface of the ladder-shaped pin 820, the connection strength of the bonding wire between the semiconductor chip and the ladder-shaped pin 820 can be maintained.

請配合參照第49圖與第50圖，第49圖繪示第44圖第八實施方式中封裝結構800於銲錫後的側面示意圖，第50圖繪示第49圖第八實施方式中封裝結構800於銲錫後的部分側面示意圖。電鍍面821的數量可為至少四，由第49圖至第50圖可知，第八實施方式中，電鍍面821的數量為六，但並不以此為限。接著，由第49圖與第50圖可知，封裝結構800的銲錫部840僅可設置於電鍍面821。藉此，當封裝結構800設置於電路板時，因側面可銲錫的面積增加，提升封裝結構800與電路板的銲接強度。Please refer to Figure 49 and Figure 50 together. Figure 49 shows a side view of the package structure 800 in the eighth embodiment in Figure 44 after soldering. Figure 50 shows the package structure 800 in the eighth embodiment in Figure 49. Partial side view after soldering. The number of plating surfaces 821 can be at least four. It can be seen from FIGS. 49 to 50 that in the eighth embodiment, the number of plating surfaces 821 is six, but it is not limited thereto. Next, it can be seen from FIGS. 49 and 50 that the solder portion 840 of the package structure 800 can only be provided on the plating surface 821. Thereby, when the package structure 800 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the soldering strength between the package structure 800 and the circuit board.

請參照第51圖至第53圖，第51圖繪示依照本發明第九實施方式中封裝結構900的正面示意圖，第52圖繪示第51圖第九實施方式中封裝結構900的背面示意圖，第53圖繪示第51圖第九實施方式中封裝結構900的部分示意圖。由第51圖至第53圖可知，封裝結構900包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料930，其中導線架用以承載半導體晶片，塑膠封裝材料930設置於導線架上並覆蓋半導體晶片形成封裝結構900。Please refer to FIG. 51 to FIG. 53, FIG. 51 is a front view of the package structure 900 according to the ninth embodiment of the present invention, and FIG. 52 is a back view of the package structure 900 in the ninth embodiment of FIG. 51, FIG. 53 is a partial schematic diagram of the package structure 900 in the ninth embodiment in FIG. 51. FIG. It can be seen from FIGS. 51 to 53, that the package structure 900 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 930. The lead frame is used to carry the semiconductor chip and the plastic package The material 930 is arranged on the lead frame and covers the semiconductor chip to form the package structure 900.

進一步來說，導線架包含一晶片座910與複數引腳，其中各引腳可為一突出引腳920，突出引腳920設置於晶片座910的四周，且突出引腳920包含複數電鍍面921與至少一無電鍍面922，其中電鍍面921設置於突出引腳920。半導體晶片設置於導線架的晶片座910上，而塑膠封裝材料930設置於導線架上，且突出引腳920突出於塑膠封裝材料930的外緣。藉此，突出引腳920可提升封裝結構900的側面可銲接面積。More specifically, the lead frame includes a die holder 910 and a plurality of pins. Each pin can be a protruding pin 920. The protruding pin 920 is disposed around the die holder 910, and the protruding pin 920 includes a plurality of plating surfaces 921 And at least one electroless plating surface 922, wherein the plating surface 921 is disposed on the protruding pin 920. The semiconductor chip is set on the chip holder 910 of the lead frame, and the plastic packaging material 930 is set on the lead frame, and the protruding pins 920 protrude from the outer edge of the plastic packaging material 930. Thereby, the protruding pin 920 can increase the solderable area of the side surface of the package structure 900.

第九實施方式中，可透過蝕刻步驟、模壓步驟、二道雷射步驟、電鍍步驟及切割步驟得到封裝結構900。詳細來說，蝕刻步驟為於導線架的上表面進行蝕刻，模壓步驟為將塑膠封裝材料930設置於導線架上並覆蓋半導體晶片，二道雷射步驟則是分別於導線架的上表面與下表面以雷射光束去除一部分塑膠封裝材料930，電鍍步驟為設置電鍍面921於雷射步驟後無覆蓋塑膠封裝材料930的導線架表面，接著再以切割步驟形成封裝結構900，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the ninth embodiment, the package structure 900 can be obtained through an etching step, a molding step, two laser steps, an electroplating step, and a cutting step. In detail, the etching step is to etch the upper surface of the lead frame, the molding step is to set the plastic packaging material 930 on the lead frame and cover the semiconductor chip, and the two laser steps are respectively on the upper surface and the lower surface of the lead frame. A part of the plastic packaging material 930 is removed from the surface with a laser beam. The electroplating step is to set the plating surface 921 without covering the lead frame surface of the plastic packaging material 930 after the laser step, and then use a cutting step to form the packaging structure 900, where the laser step can It is more than two, which depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第52圖可知，塑膠封裝材料930的長度為L，塑膠封裝材料930的寬度為W，引腳（第九實施方式為突出引腳920）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料930可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各突出引腳920的最大突出長度可為相同。藉此，封裝結構900四周的突出引腳920的可銲接面積可具有一致性，使後續封裝結構900銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Fig. 52 that the length of the plastic packaging material 930 is L, the width of the plastic packaging material 930 is W, and the pin (the protruding pin 920 in the ninth embodiment) has a maximum protruding length of L2, which can meet the following conditions ：W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 930 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each protruding pin 920 can be the same. Thereby, the solderable area of the protruding pins 920 around the package structure 900 can be consistent, so that when the subsequent package structure 900 is soldered to a circuit board (not shown), it is not easy to produce differences in soldering degree, and it can be firmly set on Circuit board.

具體而言，電鍍面921的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料930的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the electroplating surface 921 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 930 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第53圖與第54圖，第54圖繪示第51圖第九實施方式中封裝結構900的側面示意圖。由第53圖與第54圖可知，突出引腳920靠近封裝結構900之一上表面901之一部分的一突出長度小於突出引腳920靠近封裝結構900之下表面902之另一部分的一突出長度。再者，因突出引腳920突出的寬度較寬，且突出引腳920的厚度較薄。因此，可降低毛邊的產生。Please refer to FIG. 53 and FIG. 54. FIG. 54 is a side view of the package structure 900 in the ninth embodiment in FIG. 51. It can be seen from FIGS. 53 and 54 that a protruding length of a portion of the protruding pin 920 close to the upper surface 901 of the package structure 900 is smaller than a protruding length of another portion of the protruding pin 920 close to the lower surface 902 of the package structure 900. Furthermore, the protruding pin 920 has a wider protruding width, and the protruding pin 920 has a thinner thickness. Therefore, the generation of burrs can be reduced.

由第52圖可知，突出引腳920突出塑膠封裝材料930的邊緣之外，突出引腳920於封裝結構900的下表面902更包含一部分的電鍍面921。請配合參照第55圖，第55圖繪示第54圖第九實施方式中封裝結構900沿剖線55-55的剖面示意圖。進一步來說，由第53圖至第55圖可得知，突出引腳920於突出塑膠封裝材料930與塑膠封裝材料930所覆蓋的部分呈現類似鷗翼形。藉此，突出引腳920可具有一定韌性以增加板級的可靠度，當塑膠封裝材料930覆蓋封裝結構900時，突出引腳920更具有機械強度。再者，提升突出引腳920的側面可銲錫面積的同時，更可保留半導體晶片與突出引腳920之間銲線的連接強度。It can be seen from FIG. 52 that the protruding pin 920 protrudes beyond the edge of the plastic packaging material 930, and the protruding pin 920 further includes a part of the electroplating surface 921 on the lower surface 902 of the packaging structure 900. Please refer to FIG. 55 in conjunction. FIG. 55 is a schematic cross-sectional view of the package structure 900 in the ninth embodiment in FIG. 54 along the section line 55-55. Furthermore, it can be seen from FIGS. 53 to 55 that the protruding pin 920 is similar to a gull-wing shape at the portion covered by the protruding plastic packaging material 930 and the plastic packaging material 930. Thereby, the protruding pins 920 can have a certain degree of toughness to increase the reliability of the board level. When the plastic packaging material 930 covers the packaging structure 900, the protruding pins 920 have more mechanical strength. Furthermore, while increasing the solderable area of the side surface of the protruding pin 920, the connection strength of the bonding wire between the semiconductor chip and the protruding pin 920 can be maintained.

請配合參照第56圖與第57圖，第56圖繪示第51圖第九實施方式中封裝結構900於銲錫後的側面示意圖，第57圖繪示第56圖第九實施方式中封裝結構900於銲錫後的部分側面示意圖。電鍍面921的數量可為至少四，由第56圖至第57圖可知，第九實施方式中，電鍍面921的數量為九，但並不以此為限。接著，由第56圖與第57圖可知，封裝結構900的銲錫部940僅可設置於電鍍面921。藉此，當封裝結構900設置於電路板時，因側面可銲錫的面積增加，提升封裝結構900與電路板的銲接強度。Please refer to FIGS. 56 and 57 together. FIG. 56 shows a side view of the package structure 900 in the ninth embodiment in FIG. 51 after soldering. FIG. 57 shows the package structure 900 in the ninth embodiment in FIG. 56. Partial side view after soldering. The number of plating surfaces 921 may be at least four. It can be seen from FIGS. 56 to 57 that in the ninth embodiment, the number of plating surfaces 921 is nine, but it is not limited thereto. Next, it can be seen from FIGS. 56 and 57 that the solder portion 940 of the package structure 900 can only be provided on the plating surface 921. Therefore, when the package structure 900 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the welding strength between the package structure 900 and the circuit board.

請參照第58圖至第60圖，第58圖繪示依照本發明第十實施方式中封裝結構1000的正面示意圖，第59圖繪示第58圖第十實施方式中封裝結構1000的背面示意圖，第60圖繪示第58圖第十實施方式中封裝結構1000的部分示意圖。由第58圖至第60圖可知，封裝結構1000包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料1030，其中導線架用以承載半導體晶片，塑膠封裝材料1030設置於導線架上並覆蓋半導體晶片形成封裝結構1000。Please refer to FIGS. 58 to 60. FIG. 58 is a schematic front view of the package structure 1000 according to the tenth embodiment of the present invention, and FIG. 59 is a back view of the package structure 1000 in the tenth embodiment of FIG. 58. FIG. 60 is a partial schematic diagram of the package structure 1000 in the tenth embodiment in FIG. 58. It can be seen from Figures 58 to 60 that the package structure 1000 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure) and a plastic packaging material 1030. The lead frame is used to carry the semiconductor chip and the plastic package The material 1030 is arranged on the lead frame and covers the semiconductor chip to form the package structure 1000.

進一步來說，導線架包含一晶片座1010與複數引腳，其中各引腳可為一突出引腳1020，突出引腳1020設置於晶片座1010的四周，且突出引腳1020包含複數電鍍面1021與至少一無電鍍面1022，其中電鍍面1021設置於突出引腳1020。半導體晶片設置於導線架的晶片座1010上，而塑膠封裝材料1030設置於導線架上，且突出引腳1020突出於塑膠封裝材料1030的外緣。藉此，突出引腳1020可提升封裝結構1000的側面可銲接面積。More specifically, the lead frame includes a die holder 1010 and a plurality of pins, where each pin can be a protruding pin 1020, the protruding pin 1020 is disposed around the die holder 1010, and the protruding pin 1020 includes a plurality of plating surfaces 1021 And at least one electroless plating surface 1022, wherein the plating surface 1021 is disposed on the protruding pin 1020. The semiconductor chip is set on the chip holder 1010 of the lead frame, and the plastic packaging material 1030 is set on the lead frame, and the protruding pins 1020 protrude from the outer edge of the plastic packaging material 1030. In this way, the protruding pins 1020 can increase the solderable area of the side surface of the package structure 1000.

第十實施方式中，可透過蝕刻步驟、模壓步驟、二道雷射步驟、電鍍步驟及切割步驟得到封裝結構1000。詳細來說，蝕刻步驟為於導線架的上表面進行蝕刻，模壓步驟為將塑膠封裝材料1030設置於導線架上並覆蓋半導體晶片，二道雷射步驟則是分別於導線架的上表面與下表面以雷射光束去除一部分塑膠封裝材料1030，電鍍步驟為設置電鍍面1021於雷射步驟後無覆蓋塑膠封裝材料1030的導線架表面，接著再以切割步驟形成封裝結構1000，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the tenth embodiment, the package structure 1000 can be obtained through an etching step, a molding step, two laser steps, an electroplating step, and a cutting step. In detail, the etching step is to etch the upper surface of the lead frame, the molding step is to set the plastic packaging material 1030 on the lead frame and cover the semiconductor chip, and the two laser steps are respectively on the upper surface and the lower surface of the lead frame. A laser beam is used to remove part of the plastic packaging material 1030 on the surface. The electroplating step is to set the plating surface 1021 without covering the lead frame surface of the plastic packaging material 1030 after the laser step, and then use a cutting step to form the packaging structure 1000, where the laser step can be It is more than two, which depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第59圖可知，塑膠封裝材料1030的長度為L，塑膠封裝材料1030的寬度為W，引腳（第十實施方式為突出引腳1020）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料1030可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各突出引腳1020的最大突出長度可為相同。藉此，封裝結構1000四周的突出引腳1020的可銲接面積可具有一致性，使後續封裝結構1000銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Figure 59 that the length of the plastic packaging material 1030 is L, the width of the plastic packaging material 1030 is W, and a maximum protruding length of the lead (protruding lead 1020 in the tenth embodiment) is L2, which can meet the following conditions ：W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 1030 can be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above conditions. Furthermore, the maximum protruding length of each protruding pin 1020 can be the same. Thereby, the solderable area of the protruding pins 1020 around the package structure 1000 can be consistent, so that when the subsequent package structure 1000 is soldered to a circuit board (not shown in the figure), it is not easy to produce a difference in soldering degree, and it can be firmly placed on Circuit board.

具體而言，電鍍面1021的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料1030的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 1021 can be tin alloy or nickel-gold alloy, where the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 1030 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第60圖與第61圖，第61圖繪示第58圖第十實施方式中封裝結構的側面示意圖。由第60圖與第61圖可知，突出引腳1020靠近封裝結構1000之一上表面1001之一部分的一突出長度小於突出引腳1020靠近封裝結構1000之下表面1002之另一部分的一突出長度。再者，因突出引腳1020突出的寬度較寬，且突出引腳1020的厚度較薄。因此，可降低毛邊的產生。Please refer to FIGS. 60 and 61. FIG. 61 is a schematic side view of the package structure in the tenth embodiment in FIG. 58. It can be seen from FIGS. 60 and 61 that a protruding length of a part of the protruding pin 1020 close to the upper surface 1001 of the package structure 1000 is smaller than a protruding length of another part of the protruding pin 1020 close to the lower surface 1002 of the package structure 1000. Furthermore, because the protruding pin 1020 has a wider protruding width, and the protruding pin 1020 has a thinner thickness. Therefore, the generation of burrs can be reduced.

請配合參照第62圖，第62圖繪示第61圖第十實施方式中封裝結構1000沿剖線62-62的剖面示意圖。由第62圖可得知，突出引腳1020於突出塑膠封裝材料1030與塑膠封裝材料1030所覆蓋的部分呈現類似鷗翼形。藉此，突出引腳1020可具有一定韌性以增加板級的可靠度，當塑膠封裝材料1030覆蓋封裝結構1000時，突出引腳1020更具有機械強度。再者，提升突出引腳1020的側面可銲錫面積的同時，更可保留半導體晶片與突出引腳1020之間銲線的連接強度。Please refer to FIG. 62 together. FIG. 62 is a schematic cross-sectional view of the package structure 1000 along the section line 62-62 in the tenth embodiment in FIG. 61. It can be seen from FIG. 62 that the protruding pin 1020 presents a gull-wing-like shape at the portion covered by the protruding plastic packaging material 1030 and the plastic packaging material 1030. In this way, the protruding pins 1020 can have a certain degree of toughness to increase board-level reliability. When the plastic packaging material 1030 covers the packaging structure 1000, the protruding pins 1020 have more mechanical strength. Furthermore, while increasing the solderable area of the side surface of the protruding pin 1020, the connection strength of the bonding wire between the semiconductor chip and the protruding pin 1020 can be maintained.

請配合參照第63圖與第64圖，第63圖繪示第58圖第十實施方式中封裝結構1000於銲錫後的側面示意圖，第64圖繪示第63圖第十實施方式中封裝結構1000於銲錫後的部分側面示意圖。電鍍面1021的數量可為至少四，由第63圖至第64圖可知，第十實施方式中，電鍍面1021的數量為八，但並不以此為限。接著，由第63圖與第64圖可知，封裝結構1000的銲錫部1040僅可設置於電鍍面1021。藉此，當封裝結構1000設置於電路板時，因側面可銲錫的面積增加，提升封裝結構1000與電路板的銲接強度。Please refer to Fig. 63 and Fig. 64 together. Fig. 63 shows a side view of the package structure 1000 in the tenth embodiment in Fig. 58 after soldering. Fig. 64 shows the package structure 1000 in the tenth embodiment in Fig. 63. Partial side view after soldering. The number of the plating surface 1021 may be at least four. It can be seen from FIGS. 63 to 64 that in the tenth embodiment, the number of the plating surface 1021 is eight, but it is not limited thereto. Next, it can be seen from FIGS. 63 and 64 that the solder portion 1040 of the package structure 1000 can only be provided on the plating surface 1021. Thereby, when the package structure 1000 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the welding strength between the package structure 1000 and the circuit board.

請參照第65圖至第67圖，第65圖繪示依照本發明第十一實施方式中封裝結構1100的正面示意圖，第66圖繪示第65圖第十一實施方式中封裝結構1100的背面示意圖，第67圖繪示第65圖第十一實施方式中封裝結構1100的部分示意圖。由第65圖至第67圖可知，封裝結構1100包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料1130，其中導線架用以承載半導體晶片，塑膠封裝材料1130設置於導線架上並覆蓋半導體晶片形成封裝結構1100。Please refer to FIGS. 65 to 67. FIG. 65 shows a front view of the package structure 1100 in the eleventh embodiment of the present invention, and FIG. 66 shows the back side of the package structure 1100 in the eleventh embodiment of FIG. 65. Schematic diagram, FIG. 67 is a partial schematic diagram of the package structure 1100 in the eleventh embodiment in FIG. 65. It can be seen from FIGS. 65 to 67 that the package structure 1100 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 1130. The lead frame is used to carry the semiconductor chip and the plastic package The material 1130 is disposed on the lead frame and covers the semiconductor chip to form a package structure 1100.

進一步來說，導線架包含一晶片座1110與複數引腳，其中各引腳可為一突出引腳1120，突出引腳1120設置於晶片座1110的四周，且突出引腳1120包含複數電鍍面1121與至少一無電鍍面1122，其中電鍍面1121設置於突出引腳1120。半導體晶片設置於導線架的晶片座1110上，而塑膠封裝材料1130設置於導線架上，且突出引腳1120突出於塑膠封裝材料1130的外緣。藉此，突出引腳1120可提升封裝結構1100的側面可銲接面積。Furthermore, the lead frame includes a die holder 1110 and a plurality of pins, wherein each pin can be a protruding pin 1120, the protruding pin 1120 is disposed around the die holder 1110, and the protruding pin 1120 includes a plurality of plating surfaces 1121 And at least one electroless plating surface 1122, wherein the plating surface 1121 is disposed on the protruding pin 1120. The semiconductor chip is arranged on the chip holder 1110 of the lead frame, and the plastic packaging material 1130 is arranged on the lead frame, and the protruding pins 1120 protrude from the outer edge of the plastic packaging material 1130. In this way, the protruding pins 1120 can increase the solderable area of the side surface of the package structure 1100.

第十一實施方式中，可透過蝕刻步驟、模壓步驟、二道雷射步驟、電鍍步驟及切割步驟得到封裝結構1100。詳細來說，蝕刻步驟為於導線架的下表面進行蝕刻，模壓步驟為將塑膠封裝材料1130設置於導線架上並覆蓋半導體晶片，二道雷射步驟則是分別於導線架的上表面與下表面以雷射光束去除一部分塑膠封裝材料1130，電鍍步驟為設置電鍍面1121於雷射步驟後無覆蓋塑膠封裝材料1130的導線架表面，接著再以切割步驟形成封裝結構1100，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the eleventh embodiment, the package structure 1100 can be obtained through an etching step, a molding step, two laser steps, an electroplating step, and a cutting step. In detail, the etching step is to etch the lower surface of the lead frame, the molding step is to place the plastic packaging material 1130 on the lead frame and cover the semiconductor chip, and the two laser steps are respectively on the upper surface and the lower surface of the lead frame. A laser beam is used to remove a part of the plastic packaging material 1130 on the surface. The electroplating step is to set the plating surface 1121 without covering the lead frame surface of the plastic packaging material 1130 after the laser step, and then use a cutting step to form the packaging structure 1100, where the laser step can be It is more than two, which depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第66圖可知，塑膠封裝材料1130的長度為L，塑膠封裝材料1130的寬度為W，引腳（第十一實施方式為突出引腳1120）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料1130可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各突出引腳1120的最大突出長度可為相同。藉此，封裝結構1100四周的突出引腳1120的可銲接面積可具有一致性，使後續封裝結構1100銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Figure 66 that the length of the plastic packaging material 1130 is L, the width of the plastic packaging material 1130 is W, and a maximum protruding length of the pin (the protruding pin 1120 in the eleventh embodiment) is L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 1130 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above-mentioned conditions. Furthermore, the maximum protruding length of each protruding pin 1120 can be the same. Thereby, the solderable area of the protruding pins 1120 around the package structure 1100 can be consistent, so that when the subsequent package structure 1100 is soldered to a circuit board (not shown in the figure), it is not easy to produce differences in soldering degree, and can be firmly set on Circuit board.

具體而言，電鍍面1121的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料1130的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 1121 can be tin alloy or nickel-gold alloy, where the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 1130 can be epoxy resin, but it is not limited to the above-mentioned material.

請參照第67圖與第68圖，第68圖繪示第65圖第十一實施方式中封裝結構1100的側面示意圖。由第67圖與第68圖可知，突出引腳1120突出的寬度較寬。因此，可降低毛邊的產生。Please refer to FIG. 67 and FIG. 68. FIG. 68 is a side view of the package structure 1100 in the eleventh embodiment in FIG. 65. It can be seen from FIGS. 67 and 68 that the protruding pin 1120 has a wider protruding width. Therefore, the generation of burrs can be reduced.

請配合參照第69圖，第69圖繪示第68圖第十一實施方式中封裝結構1100沿剖線69-69的剖面示意圖。由第69圖可得知，突出引腳1120於突出塑膠封裝材料1130與塑膠封裝材料1130所覆蓋的部分呈現類似鷗翼形。藉此，突出引腳1120可具有一定韌性以增加板級的可靠度，當塑膠封裝材料1130覆蓋封裝結構1100時，突出引腳1120更具有機械強度。再者，提升突出引腳1120的側面可銲錫面積的同時，更可保留半導體晶片與突出引腳1120之間銲線的連接強度。Please refer to FIG. 69 in conjunction. FIG. 69 is a schematic cross-sectional view of the package structure 1100 along the section line 69-69 in the eleventh embodiment in FIG. 68. It can be seen from FIG. 69 that the protruding pin 1120 is similar to a gull-wing shape at the portion covered by the protruding plastic packaging material 1130 and the plastic packaging material 1130. Thereby, the protruding pins 1120 can have a certain degree of toughness to increase the reliability of the board level. When the plastic packaging material 1130 covers the packaging structure 1100, the protruding pins 1120 have more mechanical strength. Furthermore, while increasing the solderable area of the side surface of the protruding pin 1120, the connection strength of the bonding wire between the semiconductor chip and the protruding pin 1120 can be maintained.

請配合參照第70圖與第71圖，第70圖繪示第65圖第十一實施方式中封裝結構1100於銲錫後的側面示意圖，第71圖繪示第70圖第十一實施方式中封裝結構1100於銲錫後的部分側面示意圖。電鍍面1121的數量可為至少四，由第70圖至第71圖可知，第十一實施方式中，電鍍面1121的數量為六，但並不以此為限。接著，由第70圖與第71圖可知，封裝結構1100的銲錫部1140僅可設置於電鍍面1121。藉此，當封裝結構1100設置於電路板時，因側面可銲錫的面積增加，提升封裝結構1100與電路板的銲接強度。Please refer to Figures 70 and 71 together. Figure 70 shows a side view of the package structure 1100 in the eleventh embodiment in Figure 65 after soldering. Figure 71 shows the package in the eleventh embodiment in Figure 70. A partial side view of the structure 1100 after soldering. The number of plating surfaces 1121 can be at least four. It can be seen from FIGS. 70 to 71 that in the eleventh embodiment, the number of plating surfaces 1121 is six, but it is not limited thereto. Next, it can be seen from FIGS. 70 and 71 that the solder portion 1140 of the package structure 1100 can only be provided on the plating surface 1121. Thereby, when the package structure 1100 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the welding strength of the package structure 1100 and the circuit board.

請參照第72圖至第74圖，第72圖繪示依照本發明第十二實施方式中封裝結構1200的正面示意圖，第73圖繪示第72圖第十二實施方式中封裝結構1200的背面示意圖，第74圖繪示第72圖第十二實施方式中封裝結構1200的部分示意圖。由第72圖至第74圖可知，封裝結構1200包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料1230，其中導線架用以承載半導體晶片，塑膠封裝材料1230設置於導線架上並覆蓋半導體晶片形成封裝結構1200。Please refer to FIG. 72 to FIG. 74. FIG. 72 shows a front view of the package structure 1200 in the twelfth embodiment of the present invention, and FIG. 73 shows the back side of the package structure 1200 in the twelfth embodiment in FIG. 72. Schematic diagram, FIG. 74 is a partial schematic diagram of the package structure 1200 in the twelfth embodiment in FIG. 72. It can be seen from Figures 72 to 74 that the package structure 1200 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 1230. The lead frame is used to carry the semiconductor chip and the plastic package The material 1230 is arranged on the lead frame and covers the semiconductor chip to form the package structure 1200.

進一步來說，導線架包含一晶片座1210與複數引腳，其中各引腳可為一突出引腳1220，突出引腳1220設置於晶片座1210的四周，且突出引腳1220包含複數電鍍面1221與至少一無電鍍面1222，其中電鍍面1221設置於突出引腳1220。半導體晶片設置於導線架的晶片座1210上，而塑膠封裝材料1230設置於導線架上，且突出引腳1220突出於塑膠封裝材料1230的外緣。藉此，突出引腳1220可提升封裝結構1200的側面可銲接面積。More specifically, the lead frame includes a die holder 1210 and a plurality of pins. Each pin can be a protruding pin 1220. The protruding pins 1220 are arranged around the die holder 1210, and the protruding pins 1220 include a plurality of plating surfaces 1221 And at least one electroless plating surface 1222, wherein the plating surface 1221 is disposed on the protruding pin 1220. The semiconductor chip is set on the chip holder 1210 of the lead frame, and the plastic packaging material 1230 is set on the lead frame, and the protruding pins 1220 protrude from the outer edge of the plastic packaging material 1230. In this way, the protruding pins 1220 can increase the solderable area of the side surface of the package structure 1200.

第十二實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構1200。詳細來說，蝕刻步驟為於導線架的下表面進行蝕刻，模壓步驟為將塑膠封裝材料1230設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料1230，電鍍步驟為設置電鍍面1221於雷射步驟後無覆蓋塑膠封裝材料1230的導線架表面，接著再以切割步驟形成封裝結構1200，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the twelfth embodiment, the package structure 1200 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the lower surface of the lead frame, the molding step is to place the plastic packaging material 1230 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. Part of the plastic packaging material 1230, the electroplating step is to set the plating surface 1221 after the laser step without covering the surface of the lead frame of the plastic packaging material 1230, and then use a cutting step to form the packaging structure 1200, where the laser step can be more than two. It depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第73圖可知，塑膠封裝材料1230的長度為L，塑膠封裝材料1230的寬度為W，引腳（第十二實施方式為突出引腳1220）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料1230可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各突出引腳1220的最大突出長度可為相同。藉此，封裝結構1200四周的突出引腳1220的可銲接面積可具有一致性，使後續封裝結構1200銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Figure 73 that the length of the plastic packaging material 1230 is L, the width of the plastic packaging material 1230 is W, and the pin (the protruding pin 1220 in the twelfth embodiment) has a maximum protruding length of L2, which can satisfy the following Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 1230 may be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above conditions. Furthermore, the maximum protruding length of each protruding pin 1220 can be the same. Thereby, the solderable area of the protruding pins 1220 around the package structure 1200 can be consistent, so that when the subsequent package structure 1200 is soldered to a circuit board (not shown), it is not easy to produce a difference in soldering degree, and it can be firmly placed on Circuit board.

具體而言，電鍍面1221的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料1230的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 1221 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 1230 can be epoxy resin, but it is not limited to the above-mentioned material.

請參照第74圖與第75圖，第75圖繪示第72圖第十二實施方式中封裝結構1200的側面示意圖。由第74圖與第75圖可知，突出引腳1220突出的寬度較寬。因此，可降低毛邊的產生。Please refer to FIG. 74 and FIG. 75. FIG. 75 is a side view of the package structure 1200 in the twelfth embodiment in FIG. 72. It can be seen from FIGS. 74 and 75 that the protruding pin 1220 has a wider protruding width. Therefore, the generation of burrs can be reduced.

請配合參照第76圖，第76圖繪示第75圖第十二實施方式中封裝結構1200沿剖線76-76的剖面示意圖。由第76圖可得知，突出引腳1220於突出塑膠封裝材料1230與塑膠封裝材料1230所覆蓋的部分呈現類似鷗翼形。藉此，突出引腳1220可具有一定韌性以增加板級的可靠度，當塑膠封裝材料1230覆蓋封裝結構1200時，突出引腳1220更具有機械強度。再者，提升突出引腳1220的側面可銲錫面積的同時，更可保留半導體晶片與突出引腳1220之間銲線的連接強度。Please refer to FIG. 76 in conjunction. FIG. 76 is a schematic cross-sectional view of the package structure 1200 along the section line 76-76 in the twelfth embodiment in FIG. 75. It can be seen from FIG. 76 that the protruding pin 1220 is similar to a gull-wing shape at the portion covered by the protruding plastic packaging material 1230 and the plastic packaging material 1230. Thereby, the protruding pins 1220 can have a certain degree of toughness to increase the reliability of the board level. When the plastic packaging material 1230 covers the packaging structure 1200, the protruding pins 1220 have more mechanical strength. Furthermore, while increasing the solderable area of the side surface of the protruding pin 1220, the connection strength of the bonding wire between the semiconductor chip and the protruding pin 1220 can be maintained.

請配合參照第77圖與第78圖，第77圖繪示第72圖第十二實施方式中封裝結構1200於銲錫後的側面示意圖，第78圖繪示第77圖第十二實施方式中封裝結構1200於銲錫後的部分側面示意圖。電鍍面1221的數量可為至少四，由第77圖至第78圖可知，第十二實施方式中，電鍍面1221的數量為四，但並不以此為限。接著，由第77圖與第78圖可知，封裝結構1200的銲錫部1240僅可設置於電鍍面1221。藉此，當封裝結構1200設置於電路板時，因側面可銲錫的面積增加，提升封裝結構1200與電路板的銲接強度。Please refer to Figures 77 and 78 together. Figure 77 shows a side view of the package structure 1200 in the twelfth embodiment in Figure 72 after soldering. Figure 78 shows the package in the twelfth embodiment in Figure 77. A partial side view of the structure 1200 after soldering. The number of the plating surface 1221 can be at least four. It can be seen from FIGS. 77 to 78 that in the twelfth embodiment, the number of the plating surface 1221 is four, but it is not limited thereto. Next, it can be seen from FIGS. 77 and 78 that the solder portion 1240 of the package structure 1200 can only be provided on the plating surface 1221. Therefore, when the package structure 1200 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the welding strength between the package structure 1200 and the circuit board.

請參照第79圖至第81圖，第79圖繪示依照本發明第十三實施方式中封裝結構1300的正面示意圖，第80圖繪示第79圖第十三實施方式中封裝結構1300的背面示意圖，第81圖繪示第79圖第十三實施方式中封裝結構1300的部分示意圖。由第79圖至第81圖可知，封裝結構1300包含一導線架（圖未標示）、一半導體晶片（圖未繪示）及一塑膠封裝材料1330，其中導線架用以承載半導體晶片，塑膠封裝材料1330設置於導線架上並覆蓋半導體晶片形成封裝結構1300。Please refer to FIG. 79 to FIG. 81. FIG. 79 shows a front view of the package structure 1300 in the thirteenth embodiment of the present invention, and FIG. 80 shows the back side of the package structure 1300 in the thirteenth embodiment of FIG. 79. Schematic diagram, FIG. 81 is a partial schematic diagram of the package structure 1300 in the thirteenth embodiment in FIG. 79. It can be seen from Figures 79 to 81 that the package structure 1300 includes a lead frame (not shown in the figure), a semiconductor chip (not shown in the figure), and a plastic packaging material 1330. The lead frame is used to carry the semiconductor chip and the plastic package The material 1330 is arranged on the lead frame and covers the semiconductor chip to form the package structure 1300.

進一步來說，導線架包含一晶片座1310與複數引腳，其中各引腳可為一突出引腳1320，突出引腳1320設置於晶片座1310的四周，且突出引腳1320包含複數電鍍面1321、至少一無電鍍面1322及一凹陷部1323，其中凹陷部1323位於突出引腳1320的一表面，且電鍍面1321設置於突出引腳1320與凹陷部1323。半導體晶片設置於導線架的晶片座1310上，而塑膠封裝材料1330設置於導線架上，且突出引腳1320突出於塑膠封裝材料1330的外緣。藉此，突出引腳1320可提升封裝結構1300的側面可銲接面積。Furthermore, the lead frame includes a die holder 1310 and a plurality of pins. Each pin can be a protruding pin 1320. The protruding pins 1320 are arranged around the die holder 1310, and the protruding pins 1320 include a plurality of plating surfaces 1321 At least one electroless plating surface 1322 and a recess 1323, wherein the recess 1323 is located on a surface of the protruding pin 1320, and the electroplating surface 1321 is disposed on the protruding pin 1320 and the recess 1323. The semiconductor chip is arranged on the chip holder 1310 of the lead frame, and the plastic packaging material 1330 is arranged on the lead frame, and the protruding pins 1320 protrude from the outer edge of the plastic packaging material 1330. In this way, the protruding pins 1320 can increase the solderable area of the side surface of the package structure 1300.

第十三實施方式中，可透過蝕刻步驟、模壓步驟、雷射步驟、電鍍步驟及切割步驟得到封裝結構1300。詳細來說，蝕刻步驟為於導線架的下表面進行蝕刻，模壓步驟為將塑膠封裝材料1330設置於導線架上並覆蓋半導體晶片，雷射步驟則是於導線架的上表面以雷射光束去除一部分塑膠封裝材料1330，電鍍步驟為設置電鍍面1321於雷射步驟後無覆蓋塑膠封裝材料1330的導線架表面，接著再以切割步驟形成封裝結構1300，其中雷射步驟可為二道以上，其取決於雷射光束的能量與參數，但並不以上述的製程步驟為限。In the thirteenth embodiment, the package structure 1300 can be obtained through an etching step, a molding step, a laser step, an electroplating step, and a cutting step. In detail, the etching step is to etch the lower surface of the lead frame, the molding step is to place the plastic packaging material 1330 on the lead frame and cover the semiconductor chip, and the laser step is to remove the upper surface of the lead frame with a laser beam. Part of the plastic packaging material 1330, the electroplating step is to set the plating surface 1321 after the laser step without covering the surface of the lead frame of the plastic packaging material 1330, and then use a cutting step to form the packaging structure 1300, where the laser step can be more than two. It depends on the energy and parameters of the laser beam, but is not limited to the above-mentioned process steps.

由第80圖可知，塑膠封裝材料1330的長度為L，塑膠封裝材料1330的寬度為W，引腳（第十三實施方式為突出引腳1320）的一最大突出長度為L2，其可滿足下列條件：W ≤ L，0.01 W ≤ L2，及L2 ≤ 0.5 L。具體而言，塑膠封裝材料1330可為正方形或長方形，且最大突出長度取決於電路板的配置，並不以上述的條件為限。再者，各突出引腳1320的最大突出長度可為相同。藉此，封裝結構1300四周的突出引腳1320的可銲接面積可具有一致性，使後續封裝結構1300銲接於電路板（圖未繪示）時不易產生銲接程度的差異，且可穩固地設置於電路板。It can be seen from Figure 80 that the length of the plastic packaging material 1330 is L, the width of the plastic packaging material 1330 is W, and the pin (the protruding pin 1320 in the thirteenth embodiment) has a maximum protruding length of L2, which can meet the following requirements Conditions: W ≤ L, 0.01 W ≤ L2, and L2 ≤ 0.5 L. Specifically, the plastic packaging material 1330 can be square or rectangular, and the maximum protrusion length depends on the configuration of the circuit board, and is not limited to the above conditions. Furthermore, the maximum protruding length of each protruding pin 1320 can be the same. Thereby, the solderable area of the protruding pins 1320 around the package structure 1300 can be consistent, so that when the subsequent package structure 1300 is soldered to a circuit board (not shown in the figure), it is not easy to produce differences in soldering degree, and it can be firmly set on Circuit board.

具體而言，電鍍面1321的材質可為錫合金或鎳金合金，其中鎳金合金可為鎳鈀金、鎳鈀銀金或鎳金，導線架的材質可為鐵鎳合金或銅合金，且塑膠封裝材料1330的材質可為環氧樹脂，但並不以上述的材質為限。Specifically, the material of the plating surface 1321 can be tin alloy or nickel-gold alloy, wherein the nickel-gold alloy can be nickel-palladium-gold, nickel-palladium-silver-gold or nickel-gold, and the material of the lead frame can be iron-nickel alloy or copper alloy, and The material of the plastic packaging material 1330 can be epoxy resin, but is not limited to the above-mentioned material.

請參照第81圖與第82圖，第82圖繪示第79圖第十三實施方式中封裝結構1300的側面示意圖。由第81圖與第82圖可知，突出引腳1320突出的寬度較寬。因此，可降低毛邊的產生。再者，突出引腳1320的凹陷部1323的凹陷深度可小於突出引腳1320的厚度的一半。Please refer to FIG. 81 and FIG. 82. FIG. 82 is a schematic side view of the package structure 1300 in the thirteenth embodiment in FIG. 79. It can be seen from Fig. 81 and Fig. 82 that the protruding pin 1320 has a wider protruding width. Therefore, the generation of burrs can be reduced. Furthermore, the recess depth of the recess 1323 of the protruding pin 1320 may be less than half of the thickness of the protruding pin 1320.

請配合參照第83圖，第83圖繪示第82圖第十三實施方式中封裝結構1300沿剖線83-83的剖面示意圖。由第83圖可得知，突出引腳1320於突出塑膠封裝材料1330與塑膠封裝材料1330所覆蓋的部分呈現類似鷗翼形。藉此，突出引腳1320可具有一定韌性以增加板級的可靠度，當塑膠封裝材料1330覆蓋封裝結構1300時，突出引腳1320更具有機械強度。再者，提升突出引腳1320的側面可銲錫面積的同時，更可保留半導體晶片與突出引腳1320之間銲線的連接強度。Please refer to FIG. 83 together. FIG. 83 is a schematic cross-sectional view of the package structure 1300 along the section line 83-83 in the thirteenth embodiment in FIG. 82. It can be seen from FIG. 83 that the protruding pin 1320 is similar to a gull-wing shape at the part covered by the protruding plastic packaging material 1330 and the plastic packaging material 1330. Thereby, the protruding pins 1320 can have a certain degree of toughness to increase the reliability of the board level. When the plastic packaging material 1330 covers the packaging structure 1300, the protruding pins 1320 have more mechanical strength. Furthermore, while increasing the solderable area of the side surface of the protruding pin 1320, the connection strength of the bonding wire between the semiconductor chip and the protruding pin 1320 can be maintained.

請配合參照第84圖與第85圖，第84圖繪示第79圖第十三實施方式中封裝結構1300於銲錫後的側面示意圖，第85圖繪示第84圖第十三實施方式中封裝結構1300於銲錫後的部分側面示意圖。電鍍面1321的數量可為至少四，由第84圖至第85圖可知，第十三實施方式中，電鍍面1321的數量為八，但並不以此為限。接著，由第84圖與第85圖可知，封裝結構1300的銲錫部1340僅可設置於電鍍面1321。藉此，當封裝結構1300設置於電路板時，因側面可銲錫的面積增加，提升封裝結構1300與電路板的銲接強度。Please refer to Fig. 84 and Fig. 85 together. Fig. 84 shows a side view of the package structure 1300 in the thirteenth embodiment in Fig. 79 after soldering. Fig. 85 shows the package in Fig. 84 and the thirteenth embodiment. A partial side view of the structure 1300 after soldering. The number of the plating surface 1321 may be at least four. It can be seen from FIG. 84 to FIG. 85 that, in the thirteenth embodiment, the number of the plating surface 1321 is eight, but it is not limited thereto. Next, it can be seen from FIGS. 84 and 85 that the solder portion 1340 of the package structure 1300 can only be provided on the plating surface 1321. Thereby, when the package structure 1300 is disposed on the circuit board, the solderable area on the side surface is increased, which improves the welding strength between the package structure 1300 and the circuit board.

綜上所述，本發明的封裝結構可提升可銲接面積，進而提升與電路板的銲接強度。並且，銲接後可穩定地設置於電路板上，故可增加設置於電路板的壽命以增加板級的可靠度。In summary, the package structure of the present invention can increase the solderable area, thereby increasing the soldering strength with the circuit board. In addition, it can be stably installed on the circuit board after soldering, so the service life of the installation on the circuit board can be increased to increase the reliability of the board level.

雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100,200,300,400,500,600,700,800,900,1000,1100,1200,1300:封裝結構 101,201,301,401,501,601,701,801,901,1001:上表面 102,202,302,402,502,602,702,802,902,1002:下表面 110,210,310,410,510,610,710,810,910,1010,1110,1210,1310:晶片座 120,220,320,420,520,620,820:梯狀引腳 720,920,1020,1120,1220,1320:突出引腳 121,221,321,421,521,621,721,821,921,1021,1121,1221,1321:電鍍面 122,222,322,422,522,622,722,822,922,1022,1122,1222,1322:無電鍍面 323,623,1323:凹陷部 130,230,330,430,530,630,730,830,930,1030,1130,1230,1330:塑膠封裝材料 140,240,340,440,540,640,740,840,940,1040,1140,1240,1340:銲錫部 L:塑膠封裝材料的長度 W:塑膠封裝材料的寬度 L2:引腳的最大突出長度100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300: package structure 101,201,301,401,501,601,701,801,901,1001: upper surface 102,202,302,402,502,602,702,802,902,1002: bottom surface 110,210,310,410,510,610,710,810,910,1010,1110,1210,1310: chip holder 120, 220, 320, 420, 520, 620, 820: ladder pins 720, 920, 1020, 1120, 1220, 1320: protruding pins 121,221,321,421,521,621,721,821,921,1021,1121,1221,1321: Plating surface 122,222,322,422,522,622,722,822,922,1022,1122,1222,1322: electroless surface 323,623,1323: Depressed part 130,230,330,430,530,630,730,830,930,1030,1130,1230,1330: plastic packaging materials 140,240,340,440,540,640,740,840,940,1040,1140,1240,1340: Solder part L: Length of plastic packaging material W: Width of plastic packaging material L2: The maximum protruding length of the pin

第1圖繪示依照本發明第一實施方式中封裝結構的正面示意圖； 第2圖繪示第1圖第一實施方式中封裝結構的背面示意圖； 第3圖繪示第1圖第一實施方式中封裝結構的部分示意圖； 第4圖繪示第1圖第一實施方式中封裝結構的側面示意圖； 第5圖繪示第1圖第一實施方式中封裝結構於銲錫後的側面示意圖； 第6圖繪示第5圖第一實施方式中封裝結構於銲錫後的部分側面示意圖； 第7圖繪示依照本發明第二實施方式中封裝結構的正面示意圖； 第8圖繪示第7圖第二實施方式中封裝結構的背面示意圖； 第9圖繪示第7圖第二實施方式中封裝結構的部分示意圖； 第10圖繪示第7圖第二實施方式中封裝結構的側面示意圖； 第11圖繪示第7圖第二實施方式中封裝結構於銲錫後的側面示意圖； 第12圖繪示第11圖第二實施方式中封裝結構於銲錫後的部分側面示意圖； 第13圖繪示依照本發明第三實施方式中封裝結構的正面示意圖； 第14圖繪示第13圖第三實施方式中封裝結構的背面示意圖； 第15圖繪示第13圖第三實施方式中封裝結構的部分示意圖； 第16圖繪示第13圖第三實施方式中封裝結構的側面示意圖； 第17圖繪示第13圖第三實施方式中封裝結構於銲錫後的側面示意圖； 第18圖繪示第17圖第三實施方式中封裝結構於銲錫後的部分側面示意圖； 第19圖繪示依照本發明第四實施方式中封裝結構的正面示意圖； 第20圖繪示第19圖第四實施方式中封裝結構的背面示意圖； 第21圖繪示第19圖第四實施方式中封裝結構的部分示意圖； 第22圖繪示第19圖第四實施方式中封裝結構的側面示意圖； 第23圖繪示第19圖第四實施方式中封裝結構於銲錫後的側面示意圖； 第24圖繪示第23圖第四實施方式中封裝結構於銲錫後的部分側面示意圖； 第25圖繪示依照本發明第五實施方式中封裝結構的正面示意圖； 第26圖繪示第25圖第五實施方式中封裝結構的背面示意圖； 第27圖繪示第25圖第五實施方式中封裝結構的部分示意圖； 第28圖繪示第25圖第五實施方式中封裝結構的側面示意圖； 第29圖繪示第25圖第五實施方式中封裝結構於銲錫後的側面示意圖； 第30圖繪示第29圖第五實施方式中封裝結構於銲錫後的部分側面示意圖； 第31圖繪示依照本發明第六實施方式中封裝結構的正面示意圖； 第32圖繪示第31圖第六實施方式中封裝結構的背面示意圖； 第33圖繪示第31圖第六實施方式中封裝結構的部分示意圖； 第34圖繪示第31圖第六實施方式中封裝結構的側面示意圖； 第35圖繪示第31圖第六實施方式中封裝結構於銲錫後的側面示意圖； 第36圖繪示第35圖第六實施方式中封裝結構於銲錫後的部分側面示意圖； 第37圖繪示依照本發明第七實施方式中封裝結構的正面示意圖； 第38圖繪示第37圖第七實施方式中封裝結構的背面示意圖； 第39圖繪示第37圖第七實施方式中封裝結構的部分示意圖； 第40圖繪示第37圖第七實施方式中封裝結構的側面示意圖； 第41圖繪示第40圖第七實施方式中封裝結構沿剖線41-41的剖面示意圖； 第42圖繪示第37圖第七實施方式中封裝結構於銲錫後的側面示意圖； 第43圖繪示第42圖第七實施方式中封裝結構於銲錫後的部分側面示意圖； 第44圖繪示依照本發明第八實施方式中封裝結構的正面示意圖； 第45圖繪示第44圖第八實施方式中封裝結構的背面示意圖； 第46圖繪示第44圖第八實施方式中封裝結構的部分示意圖； 第47圖繪示第44圖第八實施方式中封裝結構的側面示意圖； 第48圖繪示第47圖第八實施方式中封裝結構沿剖線48-48的剖面示意圖； 第49圖繪示第44圖第八實施方式中封裝結構於銲錫後的側面示意圖； 第50圖繪示第49圖第八實施方式中封裝結構於銲錫後的部分側面示意圖； 第51圖繪示依照本發明第九實施方式中封裝結構的正面示意圖； 第52圖繪示第51圖第九實施方式中封裝結構的背面示意圖； 第53圖繪示第51圖第九實施方式中封裝結構的部分示意圖； 第54圖繪示第51圖第九實施方式中封裝結構的側面示意圖； 第55圖繪示第54圖第九實施方式中封裝結構沿剖線55-55的剖面示意圖； 第56圖繪示第51圖第九實施方式中封裝結構於銲錫後的側面示意圖； 第57圖繪示第56圖第九實施方式中封裝結構於銲錫後的部分側面示意圖； 第58圖繪示依照本發明第十實施方式中封裝結構的正面示意圖； 第59圖繪示第58圖第十實施方式中封裝結構的背面示意圖； 第60圖繪示第58圖第十實施方式中封裝結構的部分示意圖； 第61圖繪示第58圖第十實施方式中封裝結構的側面示意圖； 第62圖繪示第61圖第十實施方式中封裝結構沿剖線62-62的剖面示意圖； 第63圖繪示第58圖第十實施方式中封裝結構於銲錫後的側面示意圖； 第64圖繪示第63圖第十實施方式中封裝結構於銲錫後的部分側面示意圖； 第65圖繪示依照本發明第十一實施方式中封裝結構的正面示意圖； 第66圖繪示第65圖第十一實施方式中封裝結構的背面示意圖； 第67圖繪示第65圖第十一實施方式中封裝結構的部分示意圖； 第68圖繪示第65圖第十一實施方式中封裝結構的側面示意圖； 第69圖繪示第68圖第十一實施方式中封裝結構沿剖線69-69的剖面示意圖； 第70圖繪示第65圖第十一實施方式中封裝結構於銲錫後的側面示意圖； 第71圖繪示第70圖第十一實施方式中封裝結構於銲錫後的部分側面示意圖； 第72圖繪示依照本發明第十二實施方式中封裝結構的正面示意圖； 第73圖繪示第72圖第十二實施方式中封裝結構的背面示意圖； 第74圖繪示第72圖第十二實施方式中封裝結構的部分示意圖； 第75圖繪示第72圖第十二實施方式中封裝結構的側面示意圖； 第76圖繪示第75圖第十二實施方式中封裝結構沿剖線76-76的剖面示意圖； 第77圖繪示第72圖第十二實施方式中封裝結構於銲錫後的側面示意圖； 第78圖繪示第77圖第十二實施方式中封裝結構於銲錫後的部分側面示意圖； 第79圖繪示依照本發明第十三實施方式中封裝結構的正面示意圖； 第80圖繪示第79圖第十三實施方式中封裝結構的背面示意圖； 第81圖繪示第79圖第十三實施方式中封裝結構的部分示意圖； 第82圖繪示第79圖第十三實施方式中封裝結構的側面示意圖； 第83圖繪示第82圖第十三實施方式中封裝結構沿剖線83-83的剖面示意圖； 第84圖繪示第79圖第十三實施方式中封裝結構於銲錫後的側面示意圖；以及 第85圖繪示第84圖第十三實施方式中封裝結構於銲錫後的部分側面示意圖。Figure 1 is a schematic front view of the package structure according to the first embodiment of the present invention; FIG. 2 is a schematic diagram of the backside of the package structure in the first embodiment in FIG. 1; FIG. 3 is a partial schematic diagram of the package structure in the first embodiment in FIG. 1; FIG. 4 is a schematic side view of the package structure in the first embodiment in FIG. 1; Fig. 5 is a schematic side view of the package structure after soldering in the first embodiment of Fig. 1; FIG. 6 is a partial side view of the package structure after soldering in the first embodiment of FIG. 5; FIG. 7 is a schematic front view of the package structure according to the second embodiment of the present invention; FIG. 8 is a schematic back view of the package structure in the second embodiment of FIG. 7; FIG. 9 is a partial schematic diagram of the package structure in the second embodiment of FIG. 7; FIG. 10 is a schematic side view of the package structure in the second embodiment in FIG. 7; FIG. 11 is a schematic side view of the package structure after soldering in the second embodiment in FIG. 7; FIG. 12 is a partial side view of the package structure after soldering in the second embodiment in FIG. 11; FIG. 13 is a schematic front view of the package structure according to the third embodiment of the present invention; FIG. 14 is a schematic back view of the package structure in the third embodiment in FIG. 13; FIG. 15 is a partial schematic diagram of the package structure in the third embodiment in FIG. 13; FIG. 16 is a schematic side view of the package structure in the third embodiment of FIG. 13; Figure 17 is a schematic side view of the package structure after soldering in the third embodiment of Figure 13; FIG. 18 is a partial side view of the package structure after soldering in the third embodiment in FIG. 17; Figure 19 is a schematic front view of the package structure according to the fourth embodiment of the present invention; FIG. 20 is a schematic back view of the package structure in the fourth embodiment in FIG. 19; FIG. 21 is a partial schematic diagram of the package structure in the fourth embodiment in FIG. 19; FIG. 22 is a schematic side view of the package structure in the fourth embodiment in FIG. 19; FIG. 23 is a schematic side view of the package structure after soldering in the fourth embodiment in FIG. 19; FIG. 24 is a partial side view of the package structure after soldering in the fourth embodiment of FIG. 23; FIG. 25 is a schematic front view of the package structure according to the fifth embodiment of the present invention; FIG. 26 is a schematic back view of the package structure in the fifth embodiment in FIG. 25; FIG. 27 is a partial schematic diagram of the package structure in the fifth embodiment in FIG. 25; FIG. 28 is a schematic side view of the package structure in the fifth embodiment in FIG. 25; FIG. 29 is a schematic side view of the package structure after soldering in the fifth embodiment in FIG. 25; FIG. 30 is a partial side view of the package structure after soldering in the fifth embodiment in FIG. 29; FIG. 31 is a schematic front view of the package structure according to the sixth embodiment of the present invention; FIG. 32 is a schematic back view of the package structure in the sixth embodiment in FIG. 31; FIG. 33 is a partial schematic diagram of the package structure in the sixth embodiment in FIG. 31; FIG. 34 is a schematic side view of the package structure in the sixth embodiment in FIG. 31; 35 is a schematic side view of the package structure after soldering in the sixth embodiment in FIG. 31; FIG. 36 is a partial side view of the package structure after soldering in the sixth embodiment in FIG. 35; FIG. 37 is a schematic front view of the package structure according to the seventh embodiment of the present invention; FIG. 38 is a schematic back view of the package structure in the seventh embodiment in FIG. 37; FIG. 39 is a partial schematic diagram of the package structure in the seventh embodiment in FIG. 37; FIG. 40 is a schematic side view of the package structure in the seventh embodiment in FIG. 37; FIG. 41 is a schematic cross-sectional view of the package structure in the seventh embodiment in FIG. 40 along the section line 41-41; FIG. 42 is a schematic side view of the package structure after soldering in the seventh embodiment in FIG. 37; FIG. 43 is a partial side view of the package structure after soldering in the seventh embodiment in FIG. 42; FIG. 44 is a schematic front view of the package structure according to the eighth embodiment of the present invention; FIG. 45 is a schematic back view of the package structure in the eighth embodiment in FIG. 44; FIG. 46 is a partial schematic diagram of the package structure in the eighth embodiment in FIG. 44; FIG. 47 is a schematic side view of the package structure in the eighth embodiment in FIG. 44; FIG. 48 is a schematic cross-sectional view of the package structure in the eighth embodiment in FIG. 47 along the section line 48-48; FIG. 49 is a schematic side view of the package structure after soldering in the eighth embodiment in FIG. 44; FIG. 50 is a partial side view of the package structure after soldering in the eighth embodiment in FIG. 49; 51 is a schematic front view of the package structure according to the ninth embodiment of the present invention; FIG. 52 is a schematic back view of the package structure in the ninth embodiment in FIG. 51; FIG. 53 is a partial schematic diagram of the package structure in the ninth embodiment in FIG. 51; FIG. 54 is a schematic side view of the package structure in the ninth embodiment in FIG. 51; FIG. 55 is a schematic cross-sectional view of the package structure in the ninth embodiment in FIG. 54 along the section line 55-55; Figure 56 is a schematic side view of the package structure after soldering in the ninth embodiment in Figure 51; FIG. 57 is a partial side view of the package structure after soldering in the ninth embodiment in FIG. 56; FIG. 58 is a schematic front view of the package structure according to the tenth embodiment of the present invention; FIG. 59 is a schematic back view of the package structure in the tenth embodiment in FIG. 58; FIG. 60 is a partial schematic diagram of the package structure in the tenth embodiment in FIG. 58; FIG. 61 is a schematic side view of the package structure in the tenth embodiment in FIG. 58; Fig. 62 is a schematic cross-sectional view of the package structure along the section line 62-62 in the tenth embodiment in Fig. 61; FIG. 63 is a schematic side view of the package structure after soldering in the tenth embodiment in FIG. 58; Fig. 64 shows a partial side view of the package structure after soldering in the tenth embodiment shown in Fig. 63; FIG. 65 is a schematic front view of the package structure according to the eleventh embodiment of the present invention; FIG. 66 is a schematic back view of the package structure in the eleventh embodiment in FIG. 65; FIG. 67 is a partial schematic diagram of the package structure in the eleventh embodiment in FIG. 65; FIG. 68 is a schematic side view of the package structure in the eleventh embodiment in FIG. 65; FIG. 69 is a schematic cross-sectional view of the package structure in the eleventh embodiment in FIG. 68 along the section line 69-69; FIG. 70 is a schematic side view of the package structure after soldering in the eleventh embodiment in FIG. 65; FIG. 71 is a partial side view of the package structure after soldering in the eleventh embodiment in FIG. 70; FIG. 72 is a schematic front view of the package structure according to the twelfth embodiment of the present invention; Fig. 73 is a schematic back view of the package structure in the twelfth embodiment in Fig. 72; FIG. 74 is a partial schematic diagram of the package structure in the twelfth embodiment in FIG. 72; FIG. 75 is a schematic side view of the package structure in the twelfth embodiment in FIG. 72; FIG. 76 is a schematic cross-sectional view of the package structure along the line 76-76 in the twelfth embodiment in FIG. 75; FIG. 77 is a schematic side view of the package structure after soldering in the twelfth embodiment in FIG. 72; FIG. 78 is a partial side view of the package structure after soldering in the twelfth embodiment in FIG. 77; 79 is a schematic front view of the package structure in accordance with the thirteenth embodiment of the present invention; FIG. 80 is a schematic back view of the package structure in the thirteenth embodiment in FIG. 79; FIG. 81 is a partial schematic diagram of the package structure in the thirteenth embodiment in FIG. 79; FIG. 82 is a schematic side view of the package structure in the thirteenth embodiment in FIG. 79; FIG. 83 is a schematic cross-sectional view of the package structure in the thirteenth embodiment in FIG. 82 along the section line 83-83; FIG. 84 is a schematic side view of the package structure after soldering in the thirteenth embodiment in FIG. 79; and FIG. 85 is a partial side view of the package structure after soldering in the thirteenth embodiment in FIG. 84. FIG.

100:封裝結構100: Package structure

120:梯狀引腳120: Ladder pin

121:電鍍面121: Plating surface

122:無電鍍面122: electroless surface

130:塑膠封裝材料130: plastic packaging materials

Claims (13)

一種封裝結構，包含： 一導線架，包含： 一晶片座；及 複數引腳，設置於該晶片座的四周，且各該引腳包含： 複數電鍍面； 一半導體晶片，設置於該導線架的該晶片座上；以及 一塑膠封裝材料，設置於該導線架上； 其中，各該引腳突出於該塑膠封裝材料的外緣。A packaging structure that includes: A lead frame, including: A chip holder; and Plural pins are arranged around the chip holder, and each of the pins includes: Multiple plating surfaces; A semiconductor chip arranged on the chip holder of the lead frame; and A plastic packaging material arranged on the lead frame; Wherein, each of the pins protrudes from the outer edge of the plastic packaging material. 如請求項1所述之封裝結構，其中各該引腳更包含一凹陷部，位於各該引腳的一表面，且該些電鍍面設置於該凹陷部。The package structure according to claim 1, wherein each of the pins further includes a recessed portion located on a surface of each of the pins, and the plating surfaces are disposed in the recessed portion. 如請求項1所述之封裝結構，其中該些電鍍面的材質為錫合金或鎳金合金。The package structure according to claim 1, wherein the material of the plating surface is tin alloy or nickel-gold alloy. 如請求項1所述之封裝結構，其中各該引腳更包含至少一無電鍍面。The package structure according to claim 1, wherein each of the pins further includes at least one electroless plating surface. 如請求項1所述之封裝結構，其中該封裝結構的一長度為L，該封裝結構的一寬度為W，各該引腳的一最大突出長度為L2，其滿足下列條件： W ≤ L； 0.01 W ≤ L2；以及 L2 ≤ 0.5 L。The package structure according to claim 1, wherein a length of the package structure is L, a width of the package structure is W, and a maximum protruding length of each pin is L2, which meets the following conditions: W ≤ L; 0.01 W ≤ L2; and L2 ≤ 0.5 L. 如請求項5所述之封裝結構，其中各該引腳的該最大突出長度為相同。The package structure according to claim 5, wherein the maximum protruding length of each pin is the same. 如請求項1所述之封裝結構，其中該導線架的材質為鐵鎳合金或銅合金，且該塑膠封裝材料的材質為環氧樹脂。The packaging structure according to claim 1, wherein the material of the lead frame is iron-nickel alloy or copper alloy, and the material of the plastic packaging material is epoxy resin. 如請求項1所述之封裝結構，其中該些電鍍面的數量為至少四。The package structure according to claim 1, wherein the number of the plating surfaces is at least four. 如請求項1所述之封裝結構，其中各該引腳為一梯狀引腳。The package structure according to claim 1, wherein each of the pins is a ladder-shaped pin. 如請求項9所述之封裝結構，其中各該梯狀引腳靠近該封裝結構之一上表面之一部分的一突出長度小於各該梯狀引腳靠近該封裝結構之一下表面之另一部分的一突出長度。The package structure according to claim 9, wherein a protruding length of a portion of each of the ladder-shaped pins close to an upper surface of the package structure is smaller than a protruding length of a portion of each of the ladder-shaped pins close to another portion of a lower surface of the package structure Protruding length. 如請求項9所述之封裝結構，其中各該梯狀引腳靠近該封裝結構之一下表面之一部分的一突出長度小於各該梯狀引腳靠近該封裝結構之一上表面之另一部分的一突出長度。The package structure according to claim 9, wherein a protruding length of a portion of each of the ladder pins close to a lower surface of the package structure is smaller than a protruding length of a portion of each of the ladder pins close to another portion of the upper surface of the package structure Protruding length. 如請求項1所述之封裝結構，其中各該引腳為一突出引腳。The package structure according to claim 1, wherein each of the pins is a protruding pin. 如請求項12所述之封裝結構，其中各該突出引腳靠近該封裝結構之一上表面之一部分的一突出長度小於各該突出引腳靠近該封裝結構之一下表面之另一部分的一突出長度。The package structure according to claim 12, wherein a protruding length of a portion of each of the protruding pins close to an upper surface of the package structure is smaller than a protruding length of another portion of each of the protruding pins close to a lower surface of the package structure .
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