CN109478544B - Universal surface mount semiconductor package - Google Patents

Universal surface mount semiconductor package Download PDF

Info

Publication number
CN109478544B
CN109478544B CN201680040633.2A CN201680040633A CN109478544B CN 109478544 B CN109478544 B CN 109478544B CN 201680040633 A CN201680040633 A CN 201680040633A CN 109478544 B CN109478544 B CN 109478544B
Authority
CN
China
Prior art keywords
package
foot
plastic
usmp
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201680040633.2A
Other languages
Chinese (zh)
Other versions
CN109478544A (en
Inventor
K.威廉士 理察
林耿弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chuangyantang International Co ltd
Original Assignee
Chuangyantang International Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/797,056 external-priority patent/US9576932B2/en
Application filed by Chuangyantang International Co ltd filed Critical Chuangyantang International Co ltd
Publication of CN109478544A publication Critical patent/CN109478544A/en
Application granted granted Critical
Publication of CN109478544B publication Critical patent/CN109478544B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92162—Sequential connecting processes the first connecting process involving a wire connector
    • H01L2224/92166—Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

In the manufacture of semiconductor packages, a lead frame is formed by etching metal sheets from both sides through a mask and a plastic block is formed by incorporating a plurality of chips attached to a chip pad on the lead frame. While a first laser beam is used to form individual plastic capsules for each package and a second laser beam is used to sever the metal conductors, tie bars and inter-package frames to form cut-to-single packages. Many different types of packages, ranging from gull-wing foot packages to leadless packages, with exposed or isolated die pads, can be manufactured simply by varying the pattern of openings in the mask layer and the width of the plastic trench created by the first laser beam.

Description

Universal surface mount semiconductor package
Technical Field
The present invention relates to semiconductor packages including methods and apparatus designs for manufacturing and using surface mount packages in printed circuit board assembly.
Background
Semiconductor components and Integrated Circuits (ICs) are typically included in semiconductor packages that include protective coatings or encapsulating materials to prevent damage to the components during handling and assembly, during shipping, and during mounting of the components to printed circuit boards. For cost reasons, the encapsulating material is usually made of plastic. The plastic "molding compound" is injected in a liquid state into the surrounding elements that rise to an elevated temperature and which communicate with each other in the mold cavity before being uncooled and solidified into a solid plastic. Such packages are commonly referred to as "transfer molding".
The interconnection of the devices is performed by means of a metal lead frame, typically made of copper, conducting electrical current and heat from the semiconductor device or chip into and around the printed circuit board. The connection between the chip and the leadframe typically includes adhering the chip to the "die pad" of the leadframe with an electrically conductive or insulating epoxy, and the wire bonds, typically made of gold, copper or aluminum, are connected from the surface of the chip to the leadframe. Other alternatives, such as solder balls, gold bumps, or copper pillars, may be used directly on the top surface of the chip for adhesive attachment to the leadframe.
Although the metal lead frame serves as both an electrical and thermal conductor in the finished product, the lead frame will temporarily hold the components during manufacture until the plastic hardens. After the plastic is cured, the packaged chip is separated or "diced" from other molded packages on the same leadframe by mechanical dicing or mechanical punching. The metal leadframe is cut or punched out and in some cases the hardened plastic is also cut.
In "pin" semiconductor packages, i.e. portions of the package where metal pins or "pins" protrude beyond the plastic, the pins are bent by mechanical molding to set them into a final shape, in other cases where contact of the metal to the semiconductor occurs through conductors accessible only on the underside of the package. Such components are known as "leadless" packages. Whether a pin or no-pin configuration, the final finished product is packaged into tape and reel after manufacture as a ready for packaging to customer printed circuit boards (printed circuit boards, hereinafter PCBs).
Pin package the cross-sectional view shown in fig. 1A is an example of a conventional pin package in which the metal lead frame, typically copper, includes at least two conductors 1A and 1B electrically isolated from each other and secured together by a molded plastic 6. The conductor 1A, to which the semiconductor chip 4 is attached and to which mechanical and electrical connections are to be made, typically comprising epoxy, conductive epoxy or solder, by means of the chip attach layer 10. The chip pad includes conductors 1A and then the conductive pins extending out of the molded plastic 6 are mechanically bent to form bent portions 2A and flat portions 3A. Solder 8A covers the flat portion 3A and electrically connects the conductor 1A and the semiconductor chip 4 to the conductive path 7A formed by the printed circuit board PCB 9.
The surface of the semiconductor chip 4 comprises one or more exposed metallized areas (not shown) for electrical connection by means of bond wires 5 and possibly others (not shown) comprising gold, copper, aluminum or a conductive metal alloy. In the above example, the bonding wire 5 connects a part of the semiconductor chip 4 to the conductor 1B. The conductor 1B extends laterally out of the molded plastic 6 and through the curved portion 2B and the flat portion 3B onto the conductive path 7B of the PCB 9. Solder 8B electrically and mechanically connects the flat portion 3B of the conductor 1B to the PCB conductive path 7B.
The manufacture of the component involves mechanically bending the pins to form bent portions 2A and 2B such that the bottoms of flat portions 3A and 3B are coplanar for adhesion over a flat surface, i.e. PCB9. Packages with bent pins at two or more edges of the package are commonly referred to as "gull-wing" packages because of their shape of the bent pins. Unfortunately, machining is imperfect and subject to unavoidable variations. Attempts to scale down gull-wing packages to thin dimensions, i.e., to make thin gull-wing packages, fail to a height below 1 millimeter due to mechanical variations and an intolerable percentage of the total package height. Therefore, gull-wing packages cannot be used in thin product markets and such packages have been completely excluded from cellular and tablet designs. Due to its relatively low cost gull-wing packaging still exists in other products, however, the inability to miniaturize is due in part to the limitation of the minimum height by gull-wing packaging.
In addition to the problem of shrinking gull-wing packages to less than 0.8 mm for thin applications, such as IC packages, typically do not include a thick exposed die pad to act as a heat sink and have no special design modifications, and therefore cannot consume any significant power and dissipate heat effectively. Despite the limitations in profile height, poor pin coplanarity, and lack of heat sinks, a great advantage of gull-wing packaging is compatibility with low cost "wave soldering" PCB assembly methods. Wave soldering based PCB fabrication is easier and cheaper than reflow assembly for high-tech PCB factories for cell phones and flat panels, providing a cost advantage over reflow assembly per 2X to 4X PCB area. In large PCBs of consumer electronics, such as those used for HDTV backlights, PCB cost per board area is a major economic consideration or limitation of pin coplanarity, package height, and power consumption suffered by gull-wing packages.
Gull wing packages include small outline or "SO" packages such as 8 pin SOP8, 16 pin SOP16, etc.; 3-pin small outline transistors or "" SOT "" packages such as SOT23; a low profile package or TSOP package such as a 6 pin TSOP6: a slim ultra-low profile package such as a 16-pin TSSOP16, a quad flat package such as a 24-pin QFP24, and a slim quad flat package such as a 28-pin LQFP. The term "thin" is historically compared to other gull-wing packages at the time and still requires a minimum height of at least 2mm, i.e. thin as presently used means that the package height is not thin at the level of between 0.4mm and 0.8 mm.
Fig. 1B shows a cross-sectional view of another type of surface mount package that cannot be scaled to a thin size. The package is referred TO as a transistor outline or "TO" package, and is used for power packages that require dissipation and heat dissipation from a power semiconductor device or voltage regulator TO a printed circuit board. Popular TO packages include a pin TO-220 for through hole adhesion and its surface-mount version, also known as DPAK and TO-263 or D2PAK. The power package uses the exposed chip pad 1C on the back side of as a heat dissipation pad to achieve the purposes of heat dissipation, increased power consumption and reduced thermal resistance. Also known as a heat sink pad, the chip pad 1C may include an additional heat sink pad 1D extending laterally from the chip pad 1C beyond the molded plastic 6. Typically comprising conductive epoxy or solder, attaches the power semiconductor chip 4 to the chip pad 1C using a chip attach 10.
Unlike the previously illustrated integrated circuit packages, in power applications, current and heat are conducted out of the package from the bottom of the semiconductor 4. Thus, the back side of semiconductor 4 typically includes a trimetallic interlayer of a back side metal such as titanium, nickel and silver or gold to form a solderable back side. The trimetallic interlayer is placed on the back side of the chip after mechanical and chemical thinning and substrate roughening during wafer fabrication. Roughening, i.e. lowering the contact resistance between the metal and the semiconductor, is necessary in order to have good adhesion and to ensure good ohmic contact.
As in the IC package shown in fig. 1B, the surface of the semiconductor chip 4 comprises one or more metal areas exposed for electrical connection (not shown), electrically connected to the conductive pins 1B by bond wires 5 and possibly other (not shown), including gold, copper, aluminum or conductive metal alloys. In this example, the bonding wire 5 connects a portion of the semiconductor chip 4 to the conductor 1B. The conductor 1B extends laterally out of the molded plastic 6 and through the bent portion 2B and the flat portion 3B onto the conductive path 7B of the PCB9. Solder 8B electrically and mechanically connects the flat portion 3B of the conductor 1B to the PCB conductive path 7B. The manufacture of the component involves mechanically bending the pins to form the bent portion 2B and others (not shown) such that the bottom of the flat portion 3B and the exposed bottom surface of the chip pad 1C are coplanar for adhesion to the flat surface, i.e. the PCB9. Unfortunately, the machining is imperfect and subject to unavoidable variations, resulting in an unmatched bottom of the flat portion 3B and the chip pad 1C.
In PCB9 assembly, solder 8B is typically formed by wave soldering to easily cover the package leads flat 3B but as shown solder 8A cannot cover the heat sink pad 1D, with the result that a layer of adhesive solder 11 must be placed on the PCB conductors 7A before the adhesive power package is wave soldered, placing the solder on the PCB typically using a pick and place machine, or in a low cost factory, performing one package at a time with a low cost factory worker manual operation, except that it has poor coplanarity at the bottom of the leads and the back of the exposed die pad and cannot be reduced to a slim package profile, which is another disadvantage of conventional surface mount power packages.
Fig. 2 illustrates a process flow diagram for manufacturing a pin surface mount package, both of which begin with a copper sheet 20. The width of the copper sheet is matched to the mechanical width used for handling and processing during the encapsulation process. The thickness of copper typically used for ICs is 200 μm and 500 μm for power packaging. In the case of ICs, a photomask etch is optionally performed on one side to define the die pads, leads and to secure everything together during processing using the leadframe frame and tie bars, as shown in step 21B. In the case of power packages, the lead frame must be optionally thinned to distinguish pins from the thick die pad, as shown in step 21A. A second etch is then required to define the die pad, leads, and attach everything together during subsequent processing using the leadframe frame and tie bars. As an alternative, stamping may be used to define the die pad, pins and support, and then a die may optionally be used to squeeze the localized metal to thin it. This machining process, while faster than etching, creates problems. First, the mechanical stress exhibited by the compressed metal is not present in the etched leadframe, and the stress may cause plastic cracking or silicon die contact with the stressed metal. Further, the leads are thinned by mechanical stamping, and the excess metal on the sides of the thinned leads must be removed by trimming.
In either case, the lead frame is etched or mechanically molded to prepare a die attach 22, including any of the epoxy used for ICs or conductive epoxy or solder used for power packaging. After die attach (step 22), wire bonding 23A is performed using gold or copper wire bonds in ICs and copper or aluminum wire bonds in power packages. In addition, for the power device, after bonding the gate wire at step 23A, the clip pins are attached at step 23B in order to connect the high current to the upper portion of the device.
At step 24, lead frame specific molding 24 is performed, i.e., each lead frame needs to have its own custom lead frame film cavity design to ensure that plastic is only placed in specific areas including semiconductor, wire bond and lead frame portions, but not including lead extensions, bond bars and lead frame. After the plastic melts to form individual packages, the desmear operation at step 25 removes excess plastic using mechanical or chemical means. Next, in order to improve solderability and prevent oxidation of the copper lead frame, the molded leadframe is electroplated with tin, nickel, zinc or palladium, and then chemically etched to remove any excess plating material (step 26). Finally, in step 27, the leads are bent and cut, and each package die pad and its corresponding leads are singulated from other fabrications on the same leadframe. This final step, also known as singulation or trimming and de-taping, results in individual packaged ICs or power elements being ready for electrical testing. The remainder of the leadframe, including the tie bars, frames, etc., is then recycled to recycle copper for future use.
One major drawback of pin encapsulation technology is that each package requires its own die, typically requiring over $100,000 for initial investment. Manufacturers must consider this initial cost, i.e., how much time is needed to reclaim their investment, in performing calculations regarding their investment in the ROI and the expected economic returns on TTR. An unexpected consequence of the high initial investment is that businesses become more careful when pushing new packages into the market, new packaging technologies and capabilities become commercially available at slower speeds, slowing innovation and advancement to snails. These factors explain why power packaging has progressed very little over the past fifty years.
Another consideration in manufacturing is the impact of unit cost per hour of throughput, unit or UPH, including material and labor costs plus initial investment divided by UPH, both high initial investment and low UPH contributing adversely to product cost. While the UPH of the molding machine is high, productivity is sacrificed each time the factory switches packages. The tooling for the mold machine must be taken out of service and its mold cavities from one package to another, and the tooling steel blocks used to define the plastic locations must be manually modified. The molding machine must be reheated and often recalibrated with some pilot run before any production material is run through it to ensure that it is functioning well. The downtime for changing the mold may be one hour or more. The average throughput is reduced and the net cost per unit production is increased. Even at the expense of customer service, the factory management layer may choose to avoid changing molds during a work shift, delaying production for a particular customer by one to multiple shifts, even days, to the detriment of the maximized production capacity of the factory.
Fig. 3A shows an example of the lead surface of the lead-mounted package lead frame before and after molding. Photo 30A illustrates that IC lead frame 33A includes conductive leads 33A and die pad 33B prior to molding. The lead frame shown in the example includes 22 leads on each side of the plastic body and thus includes 44 leads, also referred to as 44-pins, for surface mount packages. After molding, the die pad, semiconductor die and bond wires are encapsulated by plastic, leaving only the outer portions of conductive leads 33B exposed, as shown in photograph 30B. During the manufacturing process, each chip pad is covered by its own individual molded plastic, defined by a unique mold cavity tool for a particular package type. After dicing into individual packages, i.e., packages separated from the leadframe, a perspective view of the resulting package is shown in fig. 31A and 31B. The number of conductive pins may vary widely, with two to seven dozen pins on each side of the dual sided package. The common double sided package includes a total of 3,4,6,8, 12, 16, 18, 20, 24, 28, 32, 36, 40, 44, and 48 pins.
Fig. 3B shows a small form factor or "SO" type package, including several examples of ubiquitous SO-8, a small form factor package with 8 pins 33E, shown in top perspective view 31E and bottom perspective view 32E, package 31F having 10 pins 33F and package 31G including 16 pins 33G. The package shows that the top perspective view 31D includes 20 pins 33D. A bottom perspective view of the same package, 32D, illustrates the exposed die pad 34D for improved heat conduction. However, there remains a problem in manufacturing to ensure coplanarity between the exposed die pad 34D and the bottom of the pin 33D. Most SO-type packages, such as 36 pin packages, do not include one exposed chip pad as shown in top and bottom perspective views 31C and 32C, and are not used for power applications.
Low pin count packages such as those shown in fig. 3C are typically used for single transistor, dual transistor or small analog integrated circuits such as voltage regulators, where the power consumption of the device is limited. Such packages include a small form factor transistor or SOT23 package 31K with three pins 33K, the thin small form factor package or TSOP includes 5 pin version 33H showing top and bottom perspective views 31H and 32H,6 pin version 33L showing top perspective view 31L, and the improved area efficiency J-pin wide package is referred to as TSOP-JW showing top and bottom perspective views 31J and 32J. Pins 33J flex under the package to accommodate a larger package body and chip area than conventional gull-wing packages. As the name implies, when the package pins have a J-shape, the pins actually flex during the mechanical process creating reverse gull-wings, essentially the same as other gull-wing packages except that the pins flex under the package body, rather than.
High pin count packages employ gull-wing pins disposed on four sides of the package and are therefore referred to as pin quad flat packages or LQFP packages. The top and bottom perspective views 31M and 32M as shown in fig. 3D illustrate that 32 pins LQFP have 8 gull-wing pins 33M on each side of the package, and the top and bottom perspective views 31N and 32N illustrate that 64 pins LQFP have 16 gull-wing pins 33N on each side of the package. Top and bottom perspective views 31O and 32O illustrate the LQFP having gull-wing pins 33O and exposing die pad 34O. As described in the previous SO package, maintaining the bottom coplanarity of the exposed die pad 34O and pin 33O is problematic because the calibration is entirely mechanical and subject to unavoidable manufacturing variations. This variation is particularly acute in thin packages, so LQFP packages with exposed die pads are typically 1 millimeter or more in height.
Another type of package includes bent and stamped metal lead frames that are used in power packages such as DPAK and D2PAK described above for transistor profiles or "TO" as shown in top perspective views 31P and 35P and top view 31Q in fig. 3E. During fabrication, conductive pins 33P and 33Q are bent to the desired position to be coplanar with the bottom of heat sink pad 36Q. As shown for pin 33Q, the variation in width is slightly wider in the middle of the pin. The extra metal is left over from the connecting bars used to secure the lead frames together during the manufacturing process. The leadframe structure of fig. 30R is shown before trimming and singulation to illustrate the connection of the locations of the connecting bars 37R to the leads 33R and the die pad 34R and the heat sink pad 36R. While the top view shows co-planarity, the actual leadframe is mechanically stamped into a multi-planar structure shown in top perspective view 30S, wherein the die pad 34S and heat sink pad 36S are stamped and compressed to a height below the leads 33S and connecting bars 37S.
With respect to the previous description of conventional DPAK and D2PAK, fig. 3F illustrates various alternative packages including a combination profile similar to that of a DPAK heat spreader design and an 8-pin package similar to SOP 8. In the top view 38A, the power element is connected to pin 4 a on the chip pad and is connected to pin 3 by bonding wire 39A on the chip surface metal to carry high current and the other pin is used to connect the gate or input of the transistor. In the upper view 38B, the power element is connected to the 4-pin 40B on the die pad and to the gate input pin with bond wires but the power load wire has been replaced by a braze clip 39B. The top views 38C and 38E illustrate alternative designs for the solder clip pins 39C and 39E. The top view 38D illustrates the use of a large amount of gold or braze wire 39D to reduce package resistance while eliminating the need for large diameter wire bonds or clips. The final top perspective view 38F illustrates another solder clip pin design 39F in which the set forth pin is connected by a solder clip. Even as clearly illustrated in the solder clip design, the solder clip includes a pin that is mechanically bent at portion 41F such that the bottom of solder clip pin 40F is designed to be coplanar with the back surface of heat sink pad 42F.
However, in manufacturing, maintaining coplanarity remains a problem, particularly in thin package designs. The coplanar problem is illustrated in the SEM cross-section, as shown in fig. 3G, where the backside of the exposed die pad and the heat sink pad 42F should be coplanar with the flat portion 40F of the bent leads 41F. Excessive bending will cause the leads 41F and flat portions 40F thereof to continue to extend under the chip pad and heat sink pad, while too little bending will have the opposite effect, causing the leads 41F and flat portions 40F thereof to bottom under the chip pad and heat sink pad 42F. As shown, solder 44F wets the sides of the leads 41F, but the solder cannot fully cover the leads due to the thickness of the leads 40F and the flat portions 41F. Such additional solder 43F must be manually placed on the PCB prior to mounting the pins to ensure that the solder 43F solder pins 41F and exposed chip pads and heat sink pads are soldered to the board. An example of an SOP-type low power package is shown in the photograph of fig. 3H to illustrate that bottom view 45G and 4-pin 40G of the package are not connected to the die pad and exposed die pad 42G with a connecting heat sink pad. Bottom view 45H illustrates a design in which exposed die pad 42H is not connected to a heat sink pad but to an additional 4 pins, however the remaining pins 40H are also not connected to die pad 42H.
The final fig. 3I shows a display of pin power packages such as TO220 and their heterogeneous numbers. Although these packages are not surface mount components, the package pins are not soldered flat to the PCB in this regard and the heat sink pads for additional cooling may be attached or surface mounted to the heat sink. An upper perspective view 45J and a lower perspective view 46J illustrate such a package with a through hole and 2 pins 40J. A similar package is shown in its top perspective view 45N and bottom perspective view 46N. Fig. 45K is a top perspective view illustrating another package with a through hole and 2 long leads 40K and a heat sink pad 42K. An upper perspective view 45L and a lower perspective view 46L illustrate such a package with through holes and 3 long pins 40L and heat sink pad 42L. Fig. 45O is a top perspective view illustrating a long pin package with 7 pins 40O and a heat sink pad 42O. Top perspective views 46P and 45O reveal packages with heat pads 42P and complex pin bends so that two different rows of bends are formed in pin 40P. The adhesion of the package with two rows of flex leads is shown in a side perspective view 45M where the power package is adhered to a PCB.
Leadless packages another type of surface mount semiconductor package is a "leadless" or "leadless" package. Unlike pin packages, in which conductors connect the semiconductor chip to the outside world protruding from both sides of the package-protecting plastic body, in leadless packages, conductors connected to components or ICs can only be connected to the PCB with the bottom side of the package, rather than through pins protruding from the package.
Because no pins protrude from the package, leadless packages have several unique properties, some of which are advantageous and some of which are limiting. At no-pins, the area efficiency of a no-pin package is significantly improved over a pin package. The package area efficiency, the maximum chip size is divided by the external base area, i.e. which of the lateral extent of the pins or plastic is larger is detrimental to the pin packaging, because too much space is wasted in bending the pins down to the PCB surface. Package area efficiencies of 20% to 30% or less are common for small packages such as SOT and TSOP packages, where a substantial portion of the package area and volume is wasted by plastic and metal used for the chip pads. In contrast, leadless packages may have area efficiencies as high as 70% to 80%. Moreover, because no metal extends from the sides of the leadless package, there is less risk of electrical shorting to adjacent components. Since other components on the PCB may be placed closer to the leadless package than the leadless itself, i.e., the leadless package does not require as much reserved area on the PCB. The benefit of a smaller "reserved area" is a higher PCB area efficiency, which means that it is possible to accommodate more semiconductor chip area in the same PCB space. Therefore, leadless packages provide better package area efficiency and PCB area efficiency than do leaded packages.
Another benefit of leadless packages is that they are coplanar in nature. As an artifact of its manufacturing process, the bottom of each electrical connection appears on the bottom surface of the leadless package, by definition, all being identical in the same geometric plane because they are made of the same piece of copper. No pin bending is involved in pin formation so that the exposed conductors of the package are also free of mechanical variations in formation, also known as outer pins or "lands".
In addition, since the chip pad is formed of a common copper sheet of uniform thickness, as if the exposed conductors included electrical connections or conductor lands of the package, the bottom of the chip pad is substantially coplanar with the connections of all packages. Thus, the leadless packaged die pad is naturally exposed to the bottom surface of the package, i.e., is not separated from the PCB, as is an unavoidable artifact in the manufacturing process. If it is desired that the die pad be separated or exposed, additional steps in the leadless package manufacturing sequence are necessary to ensure that the die pad is completely encapsulated by the plastic during the molding process.
The cross-section of leadframe 50 illustrated in the top half of fig. 4 shows that multiple products are fabricated simultaneously. As shown, semiconductor chip 54A is attached to exposed die pad 51A using a conductive or insulating epoxy. The bonding wire 55A electrically connects the semiconductor chip 54A to the conductive land 51B, and the bonding wire 55B electrically connects the semiconductor chip 54A to the conductive land 51C. The entire device, including the lead frame, die, and bond wires, are encapsulated in molded plastic 56. In the region adjacent to leadframe 50, semiconductor die 54B is attached to exposed die pad 51D and electrically connected to the conductive pad by bond wires 55C and other connections (only portions shown). The individual products are defined by cut lines 59 so that although conductive lands 51B and 51E, and similar conductive lands 51C and 51F, actually comprise a common copper block, they are separated into different products during the cutting process.
During dicing into individual pieces, dicing, or optional mechanical stamping, dicing is the separation of the molded plastic 56 and copper leadframe from its neighbors into individual products, and the cutting away of any connections to the leadframe frame and connecting bars. An example of a singulated product is shown in the bottom half of fig. 4, where the product contains a semiconductor chip 54A. Because the cut cuts the copper and plastic along line 51B, the lateral extension of conductive land 51B and molded plastic 56 coincide with vertical cut lines 59, forming vertical sidewalls for the leadless package. No pins can protrude laterally beyond the plastic due to its manufacturing process, so the package is given its description "no pins".
The solder or solder paste layer 61 is applied to the surface of the printed circuit board prior to placing the package on the PCB, and electrically connects the conductive pads 51C and 51B and exposes the die pad 51A to the PCB conductive paths 7. This means that solder or paste 61 must be printed or coated onto the PCB at selected locations as part of PCB manufacture. After the product is placed on top of the solder paste, the PCB is passed through a "reflow oven" or ribbon oven to heat the solder paste beyond its melting point and electrically and mechanically connect the conductive lands 51C and 51B of the product and the conductive paths 7 exposing the die pads 51A to the PCB. However, since solder paste must be applied to the PCB in advance and an expensive temperature regulator is necessary in a reflow oven or a ribbon oven, the manufacturing cost of reflow PCB manufacture can be two to four times that of simple wave soldering, where simple dipping of the PCB and components into the solder is required. This higher assembly cost represents one of the major drawbacks of leadless packages.
Fig. 5 is a flow chart illustrating a process for manufacturing a leadless package, wherein a copper sheet (step 60) may be etched or stamped (step 61) to define the die pad, conductive pad, connecting bars and frame of the leadframe, and then a solderable metal such as tin, nickel, etc. is electroplated to inhibit copper oxidation. Once the leadframe is ready, the manufacture of the product may begin including die attach (step 63), wire bonding (step 64), molding (step 65), dicing, die cutting or singulation (step 66), and desmear etching (step 67) to remove the plastic material remaining from the dicing or die cutting.
Unlike pin packages, where each individual part must be isolated from a predefined mold cavity from the individual parts surrounding the plastic, the entire matrix or product array is fabricated in a leadless package and then molded into a common plastic block. This process is shown in fig. 6A, where a common leadframe 70A prior to molding includes a die pad and conductive pads having hundreds of different and individual products 71A on a single leadframe. However, the molded leadframe 72A includes only a few large molded plastic blocks 73A, each of which includes tens of products separated by cutting or die cutting, which are of different sizes, can be simply produced by replacing the leadframe and without replacing the molding machine or mold cavity jig. This feature, the ability to produce products of different sizes in leadless package fabrication represents a significant benefit and attractive advantages explain the wide success and popularity of packaging today.
Various quad no-lead packages made using the above method are shown in fig. 6B. One nomenclature borrowed from quad-leaded packages, namely LQFP or quad-leaded flat packages, quad-no-lead packages are known as quad-flat no-lead packages or QFN packages. The term four sides or sides means that electrical connections are present at four edges of the package, but are not necessarily limited to having the same number of conductive lands on each side. For example, the QFN shown in bottom perspective view 75B has a total of 20 conductive lands 76B including 6 conductive lands on two edges and 4 conductive lands on the other two edges. It also has an exposed die pad 77B that is electrically connectable to one of the conductive pads.
The top perspective view 74B clearly reveals that no pins are apparent on the package or protrude from its sides. The only metal die is cut flush with the plastic package sidewall, exposing the conductive platform location. Although constituting a clearly identifiable feature, the exposed metal at the vertical side walls of the package is insufficient in the area for soldering. Instead, electrical connections must be made under the package, directly to conductive platform 76B. Likewise, bottom perspective view 75C shows a package with 64 conductive landing pads 76C, 16 on each edge, and one exposed chip pad 77C. The top perspective view 74C shows that the presence of conductive pins is not highlighted. Bottom perspective view 75D illustrates a bottom perspective view of a QFN type leadless package exposing chip pad 77D and 40 conductive lands 76D, 10 conductive lands per edge and their corresponding top perspective views. Another QFN package design is shown in bottom perspective view 75E with 40 conductive lands 76E, except that die pad 77E is larger than die pad 77D of the previous design.
The quad QFN leadless packages commercially available are all in fixed millimeter increments, such as 2 x 2,3 x 3,4 x 4,5 x 5,6 x 6, etc. Although package size may be standardized, there is no corresponding standardized size for the exposed chip pad. For example, bottom perspective view 74F in fig. 6C illustrates a package with 64 landing pads 76F, sixteen on each side of the four sides, but with exposed chip pads 77F comprising only a small portion of the total package area and bottom area. Variations in chip-pad design are particularly evident in smaller QFN packages, such as bottom perspective view 75L of a package with a large chip pad 77L with 16 conductive lands, as compared to bottom perspective view 75J of a package with a relatively large chip pad 77J with 12 conductive lands.
As shown in fig. 6D, leadless packages may also be used to select versions of rectangles, typically having low aspect ratios, such as 2 x 3,3 x 5, etc. For example, the rectangular QFN shown in top perspective view 74Q and bottom perspective view 75Q includes 38 conductive lands 76Q, in combination with 12 conductive lands positioned along the long side of the package and 7 conductive lands positioned at the short side. The exposed die pad 77Q may be electrically connected to one or more conductive lands or electrically insulated, thereby enabling the package to be used to support 39 different electrical connections.
Another variation in the leadless package design is that the conductive lands are located only on two sides of the package, not on all four sides. Such packages are referred to as DFN packages, where DFN is an abbreviation for double sided flat leadless packages. Examples include the DFN package shown in bottom perspective view 75P comprising an elongated die pad 77P and six conductive lands 76P, and the package shown in bottom perspective view 75T further comprising 6 conductive lands 76T and an alternating shape of die pad 77T. As in the previous example, the die pad 77T may be shorted to one or more conductive pads, or may be stand alone. In the design shown in bottom perspective view 75R, a rectangular DFN includes exposed die pad 77R with 7 conductive lands on each long side edge of the package.
In the extreme case, the DFN design may be modified to require only 2 conductive lands 76K, shown in a bottom perspective view 75K of the package, as shown in fig. 6E. Exposing the die pad 77K functions as a third electrical polarity so that the package is suitable for use in a single transistor package, such as in the perspective view of fig. 74K. Another leadless package for transistors is shown in bottom perspective view 75S as including two conductive lands 76S and a chiplet pad 77S.
QFN and DFN leadless package fabrication may also support a dual chip design for two separate chip pads as illustrated by the rectangular package shown in fig. 6F. For example, a qfn package includes two different exposed die pads 77G in top perspective view 74G and a corresponding bottom perspective view 75G, six equally spaced conductive lands 76G on two short sides of the package and seven unequally spaced conductive lands on two long sides thereof. Despite its unique dual chip pad design, top perspective view 74G shows that it is identical to a single chip electrical package of the same size. Another dual-chip pad package is shown in the top and bottom perspective views 74H and 75H described above with two different exposed chip pads 77H and 6 conductive lands 76H, three on each edge. The longer aspect ratio design is shown in bottom perspective view 75U by way of a package with 8 conductive lands 76U and two separate die pads 77U. Care must be taken in PCB assembly to ensure adequate spacing to prevent shorting between the two die pads.
As shown in fig. 6G, leadless packages may also be manufactured without any exposed die pad. For example, the DFN package bottom perspective view 75N includes 4 of each of the eight conductive lands 76N on opposite sides, while bottom perspective view 75O represents the package with 10 conductive lands 76O. As previously described, in this leadless fabrication sequence description, additional processing steps must be included to eliminate the exposed die pad.
Finally, QFN with curved edges is shown in fig. 6H, where conductive platform 76M and bottom perspective view 75M view the width of its package substrate larger than the package surface size seen in top perspective view 74M. Such packages cannot be manufactured with standard methods described in QFN and DFN manufacturing because all plastic and metal deslagging is a result of cutting or die cutting the sidewalls of perfectly vertical edges via dicing lines, which is unavoidable. In contrast, such packages require each unique package to have its own mold cavity tool, much like the fabrication of pin packages such as SOP, SOT and DPAK. The method of manufacture defines the plastic position by molding rather than cutting, eliminating the custom package-specific mold cavity tool, one of the major advantages of leadless package manufacture.
Conclusion leadless packages offer unique advantages in flexible package fabrication, coplanarity, thin capability, and elimination of the need for expensive special package mold cavity fixtures. One major disadvantage of QFN/DFN leadless packages, in all of its advantages, is that it cannot be used in wave soldering plants. Because there are no metal pins protruding laterally from the package, wave soldering cannot penetrate under the package to solder the die pads and conductive lands on the PCB conductors. Instead, the solder must be coated on the PCB using a photomask before the components are placed. Furthermore, the solder flow must be done in an expensive reflow oven or ribbon oven to make the entire PCB assembly process 2 to 4 times more expensive than a simple wave soldering factory based production. Furthermore, visual inspection of the leadless packages soldered to the PCB is not possible using a simple automated camera, as the solder cannot be confirmed from this top view. Replacement with expensive X-ray inspection equipment is necessary, increasing the cost and safety risk of reflow PCB manufacture.
In contrast, packaging such as SOP and SOT pins provides a cost advantage in PCB assembly because they are wave soldering compatible and easily assembled to low cost PCB factories, a fully collapsed PCB factory can go back to 1950 s. However, despite its manufacturing benefits in PCBs, pin packages suffer from a number of problems in practical package manufacturing, including poor pin coplanarity, poor manufacturing control during pin bending, risk of plastic cracking during pin bending, risk of plastic-to-pin delamination, and inability to scale to thin packages, particularly for heights of packages below 1 millimeter.
Poor coplanarity also makes it difficult to heat sink a lead package with an exposed die pad because the bent leads of the package are not consistently aligned with the bottom of the die pad or heat sink pad. Because longer pin sizes are required to clamp when performing pin bending, the length of the conductive pins results in poor package and PCB area efficiency and excessive pin inductance, adversely affecting switching performance, especially in power applications. The adhesion of the power components is a particularly troublesome problem because special two-step soldering is necessary, first soldering the exposed die pad and heat sink pad to the PCB, and then wave soldering the pins. Variability between solder thicknesses placed under the die pad, in combination with natural random variations during pin bending, leads to unpredictable deviations between the bottom of the bent pins and the PCB conductors, resulting in poor connections, cold pads, intermittent contacts, and degradation of reliability.
Another disadvantage of pin packages is their manufacturing flexibility. Several manufacturing steps required for pin package production require the use of specialized machinery and equipment, including package specific mold cavity fixtures, package specific leadframe trimming and bending machinery, package specific specialized processing machines, package specific resist and de-weft equipment, and more. While the equipment may generally be converted to accommodate different packages, the result is a factory outage to convert the production line from one package to another, resulting in a loss of productivity and lower UPH, thereby increasing manufacturing costs per unit.
These and other considerations are summarized in the following table in comparison to the prior art packaging.
Packaging type Pin IC package Pin power package Leadless package
Example Package LQFP、SOP、TSOP、SOT TO(DPAK、D2PAK) QFN、DFN
Package fabrication Special packaging Special packaging Flexible and interchangeable
Height Thickness of%>1mm) Very thick%>2mm) Thin type<0.8mm)
Pin coplanarity Difficult to get Difficult to get Excellent (excellent)
Power consumption Difference of difference Excellent (excellent) Good (good)
PCB factory Wave soldering Reflow soldering
PCB cost Low and low Medium and medium High height
Inspection of Optical camera Optics, some X-rays Requiring X-rays
From the above, it is apparent that no existing package meets the comprehensive needs of the market. Furthermore, each type of surface mount package in use today requires a completely different semiconductor packaging factory to manufacture, forcing packaging companies to have little opportunity to expand new markets without incurring significant additional capital costs.
What is needed is a single package design and manufacturing process that allows for flexible assembly for wave soldering and reflow for surface mount packages, facilitates superior coplanarity between the die pad and the conductive leads, achieves low package height, provides good thermal power consumption, reduces package inductance, and eliminates the need for package specific equipment such as mold cavity fixtures and lead equipment.
Disclosure of Invention
The method of the present invention is fabricated using a preferred but not necessary leadframe according to the method described in the above-referenced U.S. application Ser. No.14/056,287. The lead frame includes a plurality of die pads and leads. Each die pad and its associated pin typically correspond to a finished package, although some packages may include two or more die pads. Some of the pins and die pads are connected together, the pins included in adjacent packages may be connected together across dicing lanes where the packages are ultimately separated, and for additional stability, both the connecting bars and the frame may be used to interconnect the die pads and pins during manufacturing.
The pins may be Z-shaped when viewing the vertical cross section, and if so they each include a vertical post section, a cantilever section and a foot. The cantilever section is positioned above the vertical column section of the chip pad and protrudes horizontally inwards, and the bottom of the cantilever section is positioned at the bottom of the vertical column section and protrudes horizontally outwards. The vertical column section generally forms right and acute angles with the cantilever section and the foot. The bottom surface of the foot is coplanar with the bottom surface of the foot of the other pin and with the bottom surface of the chip pad, if exposed. In other embodiments, the pin does not include a foot, and it is possible that the pin does not include a cantilever section. The pins may be attached to the chip pad. In some embodiments, a heat sink pad extends from the die pad to improve heat transfer, which may terminate in a foot.
The leadframe may be manufactured using a process including forming a first mask layer on the back side of the metal sheet and then partially etching the metal sheet at the area where the cantilever sections of the leads are disposed through the openings of the first mask layer, with the gaps between the leads and the die pad and between the leads themselves being disposed and in the area between adjacent packages. If the chip pad is to be separated, there is also an opening in the first mask layer where the chip pad is located. If the chip pad is exposed, the mask layer covers where the chip pad is located and these areas are not etched. The metal thin layer is maintained in the etched region by etching at the opening portion of the first mask layer without cutting the entire metal sheet.
The process further includes forming a second mask layer over the front side of the metal sheet, the openings of the second mask layer covering the gaps between the die pad and the leads and between the leads, the foot regions of the leads, if any, to be located, and the regions between adjacent packages.
The metal foil is then etched through the openings in the second mask layer. The etching continues until the gaps between the die pads and the leads and the areas between the leads are provided and the metal is completely removed in the areas separating adjacent packages, but the metal is only partially removed, if any, at the feet of the leads. The openings in the first mask layer are under the cantilever segments of the pins and the second mask layer covers the feet of the pins, if any, the post segments created by the cantilever segments and feet being offset from each other in the vertical direction between the metal sheets are not affected by the etching process. These unetched segments will become vertical column segments of the pins. If the chip pad is exposed, the area within the chip pad will be formed remains unetched.
In addition, a metal stamping process may be used instead of the etching process described above. A first metal stamp is applied to a first side of the metal sheet to compress and thin the metal sheet, wherein the cantilever segments of the leads and the gaps between the die pad and the leads, as well as the locations between adjacent packages (and optionally the locations where the die pads are placed). A second metal stamp is applied to the second side of the metal sheet to sever the metal sheet, wherein the gap between the die pad and the leads, as well as the locations where adjacent packages are placed and the feet of the leads used to compress and thin the metal sheet, if any, are to be positioned.
Whether an etching or stamping process is used, the result is typically a leadframe having multiple die pads, each associated with multiple pins. If the package has leads on only two opposite sides of the die pad (a "dual" package), the die pad is typically mounted on the leadframe by at least one connecting bar. Typically the pins extend outwardly across the "streets" on adjacent sides of adjacent packages where the packages are to be separated or "singulated" and are typically connected together by a frame. If the package has pins on four sides of the chip pad (a "quad" package), the chip pad sometimes has at least one connected pin that remains connected, i.e., no gap is formed between the chip pad and the at least one connected pin during the etching or stamping process described above. The die pad remains connected to the leadframe, either by a connecting bar, an attached pin, or both.
The semiconductor die are then bonded to their respective die pads and appropriate electrical connections are made between the die and the leads, typically using wire bonding or flip chip techniques. The back side of the die may or may not be electrically and/or thermally connected to the chip pad.
According to the present invention, the plurality of die pads, each encapsulated in the leadframe, and their associated leads, the connecting bars and the frame are formed as a single plastic block using a single mold, rather than using separate molds to form the plastic capsule. The package is then singulated using one or more laser beams.
In many embodiments, each package is a plastic block separated into plastic protective capsules using a first laser beam, a series of parallel adjacent scans of which, typically, move the area between the packages. Typically, the scans are performed in two sets, orthogonal to each other, to separate the plastic into individual capsules.
After the plastic mass has been separated into capsules in each package, a second laser beam is typically used to remove the metal conductors connecting adjacent packages and any frames that may connect the metal conductors together. Again, a series of parallel adjacent scans, typically performed "streets" between packages.
By varying the aggregate, the combined laser scan width of the first laser beam can be manufactured in a variety of different width types of packages. For example, if the laser scan of the first laser beam extends to the top surface of the cantilever section of the lead, the side wall of the plastic capsule will be located there and the lead will protrude from the side wall of the plastic capsule. If the laser scan of the first laser beam extends to the top surface of the post segment of the lead, the wall of the plastic capsule will be located there and the outer side wall of the post segment will remain exposed. If the laser scan of the first laser beam extends to the top surface of the foot of the lead, the side wall of the plastic capsule will be there and the foot will extend from the side wall of the plastic capsule, but the outer side wall of the leg segment will remain covered by the plastic capsule. If the scan of the first laser beam only covers the "street" formed by the scan of the second laser beam, the sidewalls of the plastic capsule will be coplanar with the ends of the leads and a leadless package will be formed.
Preferably, the wavelength and other characteristics of the first laser beam will be such that damage to the metal conductors embedded in or underlying the plastic mass is minimized in the first laser beam.
According to another aspect of the invention, a solder layer is printed on the bottom surface of the chip pad, if exposed, and/or the bottom surface of the pins. After singulation, the package treated in this way by merely placing the package on top of the PCB and heating the package and PCB to melt the solder layer may be attached to the PCB. The package may also be subjected to a wave soldering process to attach pins to the non-formed solder layer in the appropriate path or contact PCT contacts, if desired.
Thus, the techniques of the present invention allow a variety of different types and sizes of semiconductor packages to be manufactured without the need for specialized equipment. This is achieved by substantially varying the pattern of mask layer openings applied to the back and front sides of the metal sheet and by varying the combined width of the laser scans to separate the plastic mass on each package into capsules. In using a foot package, the bottom surface of the foot is guaranteed to be coplanar and avoids the difficulties inherent in bending the pins to form a gull-wing package.
Thus, semiconductor package manufacturers can produce packages after design to meet customer specific needs in terms of economy and without unnecessary delays.
The invention discloses a method for manufacturing a semiconductor package by matching a lead frame , wherein the lead frame comprises a plurality of chip pads, a first semiconductor chip adhered to a first chip pad and a second semiconductor chip adhered to a second chip pad, and the method comprises the following steps: forming a plastic block covering the first and second semiconductor chips; and removing a portion of the plastic block from the first laser beam with respect to the plastic block to thereby form a first plastic capsule and a second plastic capsule, the first plastic capsule covering the first semiconductor chip and the second plastic capsule covering the second semiconductor chip.
Preferably, directing the first laser beam at the plastic mass includes moving the first laser beam through a series of parallel adjacent scans, each scan removing a slice of the plastic mass.
Preferably, the lead frame further comprises a metal conductor extending between the first and the second plastic capsules.
Preferably, the first laser beam has a first wavelength such that the metal conductor absorbs less of the first laser beam than the plastic mass.
Preferably, the second laser beam is directed at the metal conductor to remove a portion of the metal conductor thereby forming a first lead and a second lead separated by street, the first lead extending under the first plastic capsule and the second lead extending under the second plastic capsule.
Preferably, directing a second laser beam at the metal conductor includes moving the second laser beam through a series of parallel adjacent scans.
Preferably, the second laser beam has a second wavelength such that the second laser beam is more easily absorbed by the metal conductor than the first laser beam.
Preferably, the first pin comprises a foot section, a post section and a cantilever section.
Preferably, the first laser beam is directed against the plastic block such that a side edge of the first plastic capsule is positioned over one of the post segments and the cantilever segment of the first lead, thereby leaving the exposed first lead on the side wall of the post segment.
Preferably, the first laser beam is performed with respect to the plastic block such that a side edge of the first plastic capsule is positioned over the first leg section, thus leaving both side walls of the column covered by the first plastic capsule.
Preferably, the second laser beam is performed with respect to the metal conductor such that the side edges of the street are vertically aligned with the side edges of the first plastic capsule so as to form a leadless semiconductor package.
Preferably, the second laser beam is performed with respect to the metal conductor such that the sides of the street are vertically aligned with the side edges of the first plastic capsule so as to form a leadless semiconductor package.
Preferably, the second laser beam is directed against the connecting bar remaining under the metal conductor extending from the first plastic capsule, and the method further comprises cutting the third laser beam against the connecting bar so that the connecting bar is flush with the side wall of the first plastic capsule.
Preferably, directing a third laser beam at the connecting rod includes moving the third laser beam through a series of parallel adjacent scans.
Preferably, the lead frame formed by metal sheets comprises: a partial etch is performed in the back of the metal sheet at the first location so as to form a cantilever section of the pin.
Preferably, forming the lead frame further includes: the front surface of the metal sheet is partially etched in a second position spaced horizontally from the first position so as to form a leg of the pin, and the first and second positions are spaced by a third position, wherein the metal sheet is not etched so as to form a post of the pin.
Preferably, forming the lead frame further includes: in the fourth position, a full etch is performed in the metal sheet so that the pins are separated from the die pad.
Preferably, forming the lead frame further includes: the die pad is etched from the back side of the metal sheet so as to form an isolated die pad.
Preferably, forming the lead frame further includes: in the fourth position the metal sheet is etched completely so that the pins are separated from the die pad.
Preferably, a solder layer is printed on the back surface of the first chip pad, so that the first chip pad and the guide pattern on the PCB are assembled by wave crest soldering of flowing, wherein the first plastic glue bag comprises a first chip pad and guide pattern on the PCB. .
Drawings
In the drawings listed below, generally similar elements are given the same reference numerals.
Fig. 1A is a cross-sectional view of a pin IC surface mount package.
Fig. 1B is a cross-sectional view of a pin surface mount power package with a heat sink pad.
Fig. 2 is a flow chart of a pin surface mount package manufacturing process.
Fig. 3A includes top views of the lead frame before and after molding of the lead frame and package.
Fig. 3B includes top and bottom perspective views of various double-sided pin IC surface mount packages.
Fig. 3C includes top and bottom perspective views of various double-sided bottom pin count pin IC surface mount packages.
Fig. 3D includes top and bottom perspective views of various quad side LQFP pin surface mount packages.
Fig. 3E includes a top view of a lead surface mount power package and a leadframe.
Fig. 3F includes a top perspective view of an IC surface mount leadframe suitable for power applications.
Fig. 3G is a side view of a surface mount IC leadframe suitable for power applications.
Fig. 3H includes top and bottom views of an IC surface mount package suitable for power applications.
Fig. 3I includes a top perspective view of various pin power packages.
Fig. 4 is a cross-sectional comparison of the leadless package before and after singulation.
Fig. 5 is a flow chart of the leadless surface mount package fabrication.
Fig. 6A includes top views of a leadless surface mount leadframe and package before and after molding.
Fig. 6B includes top and bottom perspective views of a QFN quad flat no-lead surface mount package.
Fig. 6C includes top and bottom perspective views of various alternative QFN quad flat no-lead surface mount packages.
Fig. 6D is a top and bottom perspective view of a surface mount package including various alternative elongated leadless surfaces.
Fig. 6E is a top and bottom perspective view of a leadless surface mount package including various alternative low pin count packages.
Fig. 6F is a top and bottom perspective view of a leadless surface mount package including various alternatives with a plurality of exposed die pads.
Fig. 6G is a top and bottom perspective view of a dual sided leadless surface mount package including various alternative DFNs.
Fig. 6H is a top and bottom perspective view of a leadless surface mount package using a dedicated QFN nest tool.
Fig. 7A is a cross-sectional view of a Universal Surface Mount Package (USMP) leadframe region during a double-sided etching process.
Fig. 7B is a possible flow chart for USMP leadframe fabrication.
Fig. 8A is a cross-sectional view illustrating a leadframe fabrication process that may be implemented using a single USMP.
Fig. 8B is a cross-sectional view illustrating a leadframe fabrication process using a problematic USMP.
Fig. 9A illustrates a cross-sectional view of a geometric leadframe device for various two to three regions resulting from the disclosed USMP leadframe fabrication sequence.
Fig. 9B illustrates a cross-sectional view of a geometric leadframe device for various three regions resulting from the disclosed USMP leadframe fabrication sequence.
Fig. 9C shows a cross-sectional view of various USMP geometric leadframe elements including fully etched portions.
Fig. 9D shows a cross-sectional view of a portion of various USMP geometric leadframe elements including complete etching.
Fig. 10A is a top view of a USMP IC leadframe prior to molding.
Fig. 10B is a top view of a molded lead frame for an IC.
Fig. 10C is a cut-away view of a lead IC leadframe after a molding process.
Fig. 10D is a top view of the lead frame of the IC after being molded by split molding; fig. 10E is a top view of the USMP DPAK leadframe prior to molding.
Fig. 10F is a top view of a molded DPAK lead frame.
Fig. 10G is a cut-away view of a DPAK lead frame after one molding.
Fig. 10H is a top view of the DPAK leadframe after being molded in divided blocks.
Fig. 11A is a cross-sectional view of a foot package illustrating a USMP package street fabrication step.
Fig. 11B is a cross-sectional view illustrating a USMP package street fabrication step in a leadless package.
Fig. 11C is a cross-sectional view illustrating the USMP package street fabrication in an alternative foot package.
Fig. 12A is a cross-sectional view illustrating USMP laser cut single and footing formation.
Fig. 12B is a spectral plot of optical absorption of various metals.
Fig. 12C is a schematic diagram of a laser system for USMP street fabrication.
Fig. 12D is a diagram illustrating a leadframe manufactured by USMP horizontal streets.
Fig. 12E illustrates a leadframe manufactured by USMP vertical street.
Fig. 12F is a schematic diagram of a USMP street fabrication laser scan pattern for removing plastic and metal.
Fig. 12G is a top view of the USMP manufacturing foot package.
FIG. 12H is a schematic illustration of a laser scan pattern for eliminating a tie-bar process in lieu of USMP street fabrication.
Fig. 13 is a USMP flow chart for foot and leadless package fabrication.
Fig. 14A is a cross-sectional view illustrating the beginning of the USMP foot package being fabricated on a copper sheet.
Fig. 14B is a cross-sectional view illustrating the fabrication of the USMP foot package on the back side of the leadframe etching mask.
Fig. 14C is a cross-sectional view illustrating the fabrication of the USMP foot package in the front side etching mask of the leadframe.
Fig. 14D is a cross-sectional view illustrating the USMP foot package after the front side of the leadframe is etched.
Fig. 14E is a cross-sectional view illustrating the USMP foot package after fabrication of the lead frame die attach.
Fig. 14F is a cross-sectional view illustrating the USMP foot package after fabrication of the leadframe wire bond.
Fig. 14G is a cross-sectional view illustrating the USMP foot package after molding of the lead frame.
Fig. 14H is a cross-sectional view illustrating the USMP foot package after laser plastic removal from the lead frame.
Fig. 14I is a cross-sectional view illustrating the fabrication of the USMP foot package after laser dicing of the leadframe into individual and foot formations.
Fig. 14J is a cross-sectional view illustrating how the foot package is converted to a leadless package.
Fig. 15A is a cross-sectional view of a USMP package comparing the foot and no-lead package types.
Fig. 15B is a cross-sectional view of an alternative type of USMP package, comparing a foot and no-pin package.
Fig. 15C is a cross-sectional view of a USMP package comparing a foot with a separate chip pad and a leadless package type.
Fig. 15D is a cross-sectional view of a comparative different type of pin USMP power package.
Fig. 15E is a cross-sectional view of the USMP process for manufacturing the pin power package.
Fig. 15F is a cross-sectional view of a pin surface mount power package with the USMP process instead of a gull wing package.
Fig. 16 is a perspective view of the USMP process for manufacturing the foot package in a lead structure.
Fig. 17A is a plurality of views including a foot USMP package.
Fig. 17B is a plurality of views of an alternative embodiment including a foot USMP package.
Fig. 17C is a plurality of views including the USMP process for manufacturing a leadless package.
Fig. 17D is a plurality of views of an alternative embodiment including the USMP process for leadless package manufacturing.
Fig. 17E is a plurality of views of another alternative embodiment including the USMP process for leadless package manufacture.
Fig. 18A is a plurality of views including the USMP process for manufacturing the lead package.
Fig. 18B is a plurality of views including the USMP process for manufacturing the pin surface mount package.
Fig. 18C is a plurality of views including the USMP process for manufacturing the power package heat sink.
Fig. 19A is a cross-sectional view of the exposed and isolated die pad including the USMP leadframe along a cut line through a die pad connection foot and an isolated foot.
Fig. 19B is a cross-sectional view of the exposed and isolated die pad including the USMP leadframe along a symmetrical cut line through the die pad and the connecting bars.
Fig. 19C is a cross-sectional view of the exposed and isolated die pad including the USMP leadframe along a symmetrical cut line through the die pad connection foot.
Fig. 19D is a cross-sectional view of the exposed die pad including the USMP leadframe through the heat spreader pad and the foot along a cut line.
Fig. 19E is a cross-sectional view of the exposed die pad including the USMP leadframe along a cut line through the heat spreader pad and the connecting bars.
Fig. 19F is a cross-section of the exposed and isolated die pad including the USMP leadframe along a symmetrical scribe line with no bond to the die pad.
Fig. 19G is a cross-sectional view of the exposed and isolated die pad including the USMP leadframe along a symmetrical cut line through the die pad.
Fig. 19H is a cross-sectional view of an exposed die pad including a USMP leadframe along a symmetrical cut line, with or without a connecting bar.
Fig. 19I is a cross-sectional view of an isolated die pad including a USMP leadframe along a symmetrical cut line, with or without a connecting bar.
Fig. 19J is a cross-sectional view of a dual-die pad with or without connecting bars along a symmetrical cut line including a USMP leadframe.
Fig. 19K is a cross-sectional view of the isolated die pad including the USMP leadframe along a symmetrical cut line through the dual die pad and die pad attach foot.
Fig. 19L is a cross-sectional and bottom view including Z-shaped feet without connection to the chip pad.
Fig. 20A is various views including a 2-foot USMP with isolated and exposed die pads.
FIG. 20B is various views of an alternative embodiment including a 2-foot USMP with isolated and exposed die pads.
Fig. 20C is various views including a 2-foot USMP with isolated and exposed die pad and a three-sided foot.
Fig. 20D is various views of an alternative embodiment including a 2-foot USMP with isolated and exposed die pads and a three-sided foot.
Fig. 21A is various views including a 3-foot USMP with isolated and exposed chip pads.
Fig. 21B is various views including a 3-foot USMP with isolated and exposed chip pads and a three-sided foot.
Fig. 21C is various views of a USMP power USMP with heat sink pad including a 3-foot USMP.
Fig. 21D is various views of an alternative embodiment including a 3-foot USMP power USMP with a heat sink pad.
Fig. 22A is various views including a 4-foot USMP with isolated and exposed die pads.
Fig. 22B is various views including a 6-foot USMP with isolated and exposed die pads.
Fig. 22C is a bottom view of the 18-foot USMP with the exposed chip pad including 8, 12, and 18-foot USMP.
Fig. 22D is a bottom view of the USMP with isolated die pad including 8, 12, and 18-feet.
Fig. 23A is a bottom view of a 16-foot USMP with single and double exposed die pads.
Fig. 23B is a bottom view of an alternative embodiment including a 16-foot USMP with two exposed die pads.
Fig. 23C is a bottom view of a 16-foot USMP with two isolated chip pads.
Fig. 23D is a bottom view of a integrated isolation and exposed chip pad including 16-foot USMP.
Fig. 24A is a bottom view of a dual-exposure chip pad including 16-foot USMP in combination with an increased pad-to-pad spacing.
Fig. 24B is a bottom view of an alternative embodiment including a 16-foot USMP in combination with two exposed chip pads and increasing pad-to-pad spacing.
Fig. 24C is a cross-sectional view including a 16-foot USMP in combination with two exposed chip pads and increasing pad-to-pad spacing.
Fig. 24D is a cross-sectional view of an alternative embodiment including a 16-foot USMP in combination with two exposed chip pads and increasing pad-to-pad spacing.
Fig. 24E is a cross-sectional view of an alternative embodiment including a 16-foot USMP in combination with two exposed chip pads and increasing pad-to-pad spacing.
Fig. 24F is a cross-sectional view of an alternative embodiment including a 16-foot USMP in combination with two exposed chip pads and increasing pad-to-pad spacing.
Fig. 24G is a cross-sectional view of a cantilever pin extension including a 16-foot USMP in combination with a single exposed chip pad.
Fig. 24H is a cross-sectional view including 16-foot USMP in combination with an exposed die pad, an isolated die pad, and a cantilever pin extension.
FIG. 24I is a cross-sectional view of an alternative embodiment including 16-foot USMP in combination with an exposed die pad, an isolated die pad, and a cantilever pin extension.
Fig. 24J is a cross-sectional view of an alternative embodiment including 16-foot USMP in combination with an exposed die pad, an isolated die pad, and a cantilevered pin extension.
FIG. 25A is a bottom view of an interconnect between a bond exposed chip pad and a spacer including a 16-foot USMP.
FIG. 25B is a bottom view of an alternative embodiment including 16-foot USMP in combination with two exposed die pad and spacer interconnections.
Fig. 26A is a perspective view of a quad USMP including 16-feet.
Fig. 26B is a bottom view of a quad USMP including 16-feet with one exposed chip pad.
Fig. 26C is a bottom view of a quad USMP including 16-feet with an isolated chip pad.
Fig. 27A is a bottom view of a quad USMP including 4 and 6 feet with an exposed die pad.
FIG. 27B is a bottom view of the four-foot USMP including 8 and 10-feet with one exposed and isolated chip pad.
Fig. 27C is a bottom view of a quad USMP including 8-feet with an exposed and isolated chip pad and chip pad attached to the feet.
Fig. 27D is a bottom view of a four sided USMP including 8 and 10-foot rectangles with an exposed and isolated chip pad.
Fig. 28A is a bottom view of a quad USMP including 12-feet with an exposed and isolated chip pad.
Fig. 28B is a bottom view of a four sided USMP including a 16-foot rectangle with one exposed and isolated chip pad.
Fig. 29A is a bottom view of a four sided USMP including a 20-foot rectangle with one exposed chip pad.
Fig. 29B is a bottom view of a quad USMP including a 20-foot rectangle with an isolated chip pad.
Fig. 30A is a bottom view of a quad USMP including a 48-foot rectangle with an exposed die pad.
Fig. 30B is a bottom view of a quad USMP including a 48-foot rectangle with an isolated chip pad.
Fig. 30C is a bottom view of an alternative embodiment including a 48-foot rectangular quad USMP with an isolated chip pad.
Fig. 31 includes various views of a power USMP combined multi-foot package with extended diffusion heat spreader.
Fig. 32A is various views including a USMP having an inner pin connecting bar.
Fig. 32B is various views including a USMP leadframe having inner lead connecting bars.
Fig. 32C illustrates the execution of the main laser path for package pin definition and singulation of quad USMP.
Fig. 32D is a bottom view of a package including a USMP having inner lead connecting bars cut into individual pieces.
Fig. 32E is a bottom view illustrating the laser removal of the four sided USMP connecting bar.
Fig. 33A is a bottom view of a dual pad with inner pin connecting bars included in USMP.
Fig. 33B includes a bottom view of an alternative embodiment of the dual pad interconnection in the USMP using an inner pin connecting bar and spacer pads.
Fig. 34A is a bottom view of a thermal comb comprising a peak solder pad in a power USMP.
Fig. 34B is a bottom view of a wave soldering heat pad comprising a heat comb in a power USMP leadframe.
Fig. 34C is a main laser path for power USMP package pin definition with heat sink pad and dicing into singulated implementations.
Fig. 35A is a bottom view of an alternative embodiment including a thermal comb for a peak solder heat pad in a power USMP.
Fig. 35B is a bottom view of an alternative embodiment including a thermal comb for wave soldering heat pads in a power USMP leadframe.
Fig. 35C is a bottom view that includes an illustration of the USMP power package forming a thermal comb via a laser.
Fig. 36A is a bottom view of a heat sink pad with one bolt hole including peak welding in power USMP.
Fig. 36B illustrates the formation of bolt holes in the wave soldering heat sink pad in the laser path in the power USMP.
Fig. 37 is a block diagram illustrating various manufacturing processes for USMP leadframe plating.
Fig. 38 is a cross-sectional view illustrating a USMP pre-plated power package leadframe.
Fig. 39 is a cross-sectional view illustrating USMP formed using electroplating after molding.
Fig. 40 is a continuous cross-sectional view illustrating USMP fabrication including selective lead frame plating.
Fig. 41A is a continuous cross-sectional view illustrating a PCB assembly printed with PCB solder.
Fig. 41B is a cross-sectional view illustrating potential manufacturing issues including die tilt during USMP assembly.
Fig. 42A is a block diagram illustrating various manufacturing flows for USMP manufacturing, including solder printing.
Fig. 42B is a USMP cross-sectional view illustrating the use of USMP pre-plated solder for power and exposed chip pad IC packages.
Fig. 43A is a cross-sectional view representation illustrating a PCB USMP assembly step utilizing USMP preplating solder.
Fig. 43B is a cross-sectional view representation illustrating pre-PCB assembly to wave soldering, including both USMP power packages and USMP IC packages.
Fig. 43C is a cross-sectional view representation including both a USMP power package and a USMP IC package after the PCB is assembled in wave soldering.
Fig. 44A illustrates a USMP power package with uniform and patterned preprinted solder.
Fig. 44B illustrates a USMP integrated circuit quad-package with uniform and patterned USMP preprinted solder.
Fig. 44C illustrates the use of preprinted solder for test probe placement for USMP manufacturing packages.
Fig. 45 is a cross-sectional view illustrating the need for a customized heater block for the singulated die pad in USMP manufacturing.
Fig. 46 is a cross-sectional view illustrating the isolation of USMP die pads in two different ways using thermally conductive electrically insulating pre-molded compounds.
Fig. 47 is a flow chart illustrating the fabrication of the isolated die pad USMP with thermally conductive, electrically insulating pre-molded compound.
Fig. 48 is a diagram illustrating an alternative embodiment of the manufacture of an isolated die pad USMP utilizing thermally conductive electrically insulating pre-molded compound.
Fig. 49A is a top view illustrating the cut QFN3 x 3-12L leadframe and its corresponding foot USMP equivalent.
Fig. 49B is a top view illustrating the cut QFN4 x 4-16L leadframe and its corresponding foot USMP equivalent.
Fig. 49C is a top view illustrating die cut QFN4 x 4-24L lead frames and their corresponding foot USMP equivalents.
Fig. 49D is a table illustrating a comparison of cut and stamped 4 x 4QFN leadless packages and 4 x 4QFF foot packages.
Fig. 49E is a top view illustrating the cut TDFN5 x 6-8L leadframe and its corresponding foot USMP equivalent.
Fig. 50A is a top view illustrating a conventional TO-252 (DPAK) leadframe and its corresponding foot USMP equivalent.
Fig. 50B is a perspective view and a bottom view illustrating an alternative embodiment of the foot DPAK.
Fig. 50C is a perspective view and a bottom view illustrating a conventional and foot DPAK package.
Fig. 50D is a perspective view and a bottom view illustrating a conventional and foot DPAK package.
Fig. 50E is a table illustrating a comparison of a conventional pin DPAK with two foot DPAK packages.
Fig. 51A is a top view illustrating a conventional SOT23 leadframe and its corresponding foot USMP equivalent.
Fig. 51B is a table illustrating a comparison of a conventional and footed SOT23 package.
Fig. 52A is a top view of a conventional TSSOP-8L leadframe and its corresponding foot USMP equivalent.
Fig. 52B is a top view illustrating an alternative embodiment of a foot TSSOP-8L leadframe and package.
FIG. 52C is a comparison table illustrating a conventional and footed TSSOP-8L package.
Fig. 53A is a top view illustrating a conventional SOP-8L leadframe and its corresponding foot USMP equivalent.
Fig. 53B is a top view illustrating another embodiment of a leadframe and package with a bottom finger SOP-8L.
FIG. 53C is a table illustrating a comparison of a conventional and footed SOP-8L package.
Fig. 54A is a top view illustrating the equivalent of a conventional LQFP7 x 7-32L leadframe and its corresponding foot USMP.
Fig. 54B is a top view illustrating an alternative embodiment of a conventional and leaded LQFP7 x 7-32L lead frame and package.
Fig. 54C is a table illustrating a comparison of a conventional and foot LQFP7 x 7-32L leadframe and package.
[ Main element symbols description ]
Figure GDA0003826875880000241
Figure GDA0003826875880000251
Figure GDA0003826875880000261
Figure GDA0003826875880000271
Figure GDA0003826875880000281
Figure GDA0003826875880000291
Detailed Description
Application Ser. No. 14/056,287 and provisional application Ser. Nos. 61/775,540 and 61/775,544, cited above, relate to methods of the present invention for integrated circuits to make thin wave soldering compatible with semiconductor packages. The methods disclosed in these patent applications are used to fabricate low profile foot packages currently used to fabricate gull-wing pin packages, such as SOP8 or SOT23, in the same semiconductor I C packaging facility. The patent application also discloses methods for manufacturing thin foot packages used in current facilities to manufacture leadless packages such as QFN and DFN.
The above-referenced application No. 14/703,359 relates to the present invention that makes discrete power element such as DPAK and D2PAK and other custom pin packages suitable for use in power integrated circuits with the same factory and thickness of today's fabrication, i.e., thick, packages with thick mechanically bent pins.
From these patent applications, thin wave soldering compatible "foot" packages can be manufactured with minimal or investment in today's factories, according to the following limitations:
pin IC packaging factories produce gull-wing packages, such as SOP8 and SOT23, which can be adapted to produce thin foot versions of the same package, but cannot be used to produce leadless or power packages without incurring significant new equipment and die costs;
leadless IC packaging factories produce leadless packages, such as DFN and QFN, versions of thin footing packages that can be adapted to produce the same packages compatible with wave soldering to replace leaded IC packages of the same footprint (no leadless packages), but cannot be used to produce power packages without incurring significant new equipment and die costs;
power packaging plants producing split power packages, such as DPAK and D2PAK and power IC packages, such as power SOP8 power packaging plants may be adapted to produce versions of the same package thin "footing" but cannot be used to produce pin or leadless IC packages without incurring significant new equipment and die costs;
The above-mentioned points are highlighted in that the pin packaging factory cannot manufacture a different range of packages at all, because each package has to use a dedicated mechanical tool for a particular package. The special packaging equipment and tools include:
punching, punching and trimming machines for the manufacture of lead frames;
the moulding cavity tool (possibly transferred to the moulding press itself);
trimming and shaping tools for pin bending, cutting into single pieces, cutting off and deslagging, i.e. removing connecting bars, frames, etc. after manufacturing is completed;
processing tools specific to each leadframe;
pick up machine to pick up and pack packages cut into individual packages;
all of the above listed machines are specific to a particular package and generally cannot be used to make other package types. This inflexibility forces each package provider to choose a particular package to meet a market-specific segment, and if opportunities or needs for different packages arise, it is not possible, if possible, because they change their own factories in time to accommodate new packages.
Even where it is not possible that a particular production line may be adapted to support another somewhat similar package, for example, a shift from one SOT23 production line to the SOT223 production line, the process is complex. The conversion package must be replaced with another, all mold cavity tools must be changed, the process must be changed, the trimming and shaping machine must be converted, and even the temperature of the molding press must be recalibrated. All of these modifications have the effect of a loss of productivity during the plant changeover, reducing the overall throughput, i.e. the UPH or units per hour of the plant due to downtime. Economically, low UPH means higher cost per unit and the profitability and competitiveness of the packaging company are adversely affected.
Thus, while the methods disclosed in the above-identified patent applications are used to upgrade pin packages to thin-form pin packages that provide absolute coplanarity for improved PCB manufacture, and also to provide a method of producing wave soldering pin packages at a factory where nothing previously could be produced other than pin-less packages, the present disclosure is detrimental to producing excessive packages at the same factory with minimal or no cost of converting factory machinery and dies
The method disclosed herein overcomes this inflexible package-specific fabrication by combining the following features:
double-sided etched leadframe;
shared "block" molding for multiple packages and lead frames;
definition of laser plastic and pins;
combining these elements enables a single factory to make nearly infinite combinations of pins, no pins, and power packages. As it is used to create any number of capabilities of different package types, including:
foot IC surface mount packaging;
leadless IC surface mount packages;
foot power surface mount package;
pin IC package;
pin power package;
thus, the package disclosed herein is referred to as a "universal surface mount package" or USMP.
Double-sided etched lead frame the packages of the present invention may be fabricated from lead frames having double-sided etching. The copper sheet 90 is shown in cross-section 80 of fig. 7A with a thickness of 200 microns or 500 microns for use in forming a USMP leadframe. The copper sheet is modified into four geometric pieces or segments by etching or optionally by stamping.
The copper sheet 90 is further divided into four sections a, B, C and D. In cross-section 81 of fig. 7A, a mask 83 protects sections a and B, but exposes the back side etches of sections D and C, typically a liquid acid solution for etching copper. After etching, the thickness of copper sheet 90 is reduced to create cantilever portion 92, while portion 91 retains its entire thickness. Alternatively, if the top surface of the copper sheet 90 is also exposed to copper etching, the thickness is reduced but the cantilever segments 92 are proportionally reduced throughout the copper sheet 90, including the portions 91.
In cross-section 82 in fig. 7A, a mask 84 protects sections a and C, but exposes sections B and D as a front side etch. During the etching process, section B is thinned at 91 to form foot 100B, and all copper of section D is completely removed. If the etching occurs only on the front surface, the portion 100A at section A and the cantilever 100C at section C remain unaffected. However, if the etching occurs in an acid bath, the back side of the copper leadframe 90 is unprotected, all parts being thinned proportionally.
The result of the manufacturing sequence is four different sections. Section a includes the full thickness of the copper sheet, i.e., 100%. Section C includes etching copper cantilever 100C to have a thickness, e.g., 30%, of a small portion of the total thickness of copper sheet 90, with a top surface that is coplanar with section a. Segment B includes etching copper to a thickness that is a fraction of the total thickness of copper sheet 90, e.g., 30%, with a bottom surface that is coplanar with segment a. Section D includes an opening 101D that is completely cleared of metal.
For the leadframe manufacturing process flow diagram shown in fig. 7B, the copper sheet 90 is started (step 95) and then etched (step 96A), mask and front etched (step 96B), and finally solder plated (step 97) for the leadframe, which is plated with tin, silver, nickel, palladium or other solderable metal.
Fig. 8A illustrates design parameters for etching copper sheet 90, shown in cross-section 85. To keep copper in the cantilever portion C and the foot portion B and to remove all the metal portion D, the sum of the front side etching and the back side etching must exceed 100%, preferably 10% more overetch. For example, in cross-section 86A the front side etch removes 70% of the copper to form the foot 100B and the back side etch removes 70% of the copper to form the cantilever 100C. This embodiment of the invention results in cantilever and foot portions of the same thickness.
Optionally, the front side etch removes more than the back side. As shown in cross-section 86B, the front side etch removes 70% of the copper to form the foot 100B and the back side etch removes 40% of the copper to form the cantilever 100C. This version produces a thick cantilever 100C and a thin foot 100B. In another embodiment, the back side etch removes more than the front side. As shown in cross-section 86C, the front side etch removes 40% of the copper to form the foot 100B, and the back side etch removes 70% of the copper to form the cantilever 100C. This version would produce a thin cantilever 100C and a thick foot 100B.
To ensure that the total of the front and back etch removal thicknesses of the copper removed portions must exceed 100% of the copper thickness. If the two etches are similar in time but do not exceed 100% of the original copper thickness, the unexpected result of metal bridge 89 is shown in cross-section 87A of FIG. 8B. If the duration of the top etch is short and the back etch is one long duration, but the total etch does not exceed the initial thickness of copper, the unexpected result of metal bridge 89 is shown in cross-sectional view 87B. If the top etch is of a long duration and the back etch is of a short duration, but the total etch does not exceed the initial thickness of copper, the result of the unexpected metal bridge 89 is shown in cross-sectional view 87C.
Various useful geometries may be implemented in the fabrication of lead frames according to the present invention, as shown in fig. 9A, including pillars 100A of section a; foot 100B comprising section B; cantilever 100C comprising section C; half-tee 100E comprising a combination of sections a and C; an L-shape 100F comprising a combination of sections a and B; and a Z-shape 100G including a combination of segments C, A and B. Other useful geometries are shown in fig. 9B as an inverted T100H comprising a combination of segments B, A and B; a T-shape 100J comprising a combination of segments C, A and C, a U-shape 100L comprising a combination of segments a, B and a; and also an inverted U-shape 100K comprising a combination of segments A, C and a.
The gap incorporating copper and the intervention including geometry 101M, including column a and the intervention gap is shown in fig. 9C by other useful geometries fabrication during the present disclosure; geometry 101N includes cantilever C and intervening gap; geometry 101P includes foot B and intervening gap; and also geometry 101Q includes column a, foot B, and intervening gap. Also, in fig. 9D, geometry 101R includes column a, cantilever C, and intervening gap; while geometry 101S includes foot B, cantilever C and intervening gap. These various geometric elements are used to construct the leadframe and package functions as disclosed herein.
Another important element of the molding block USMP for pin & no-pin packages is that it eliminates the need for special mold cavity tools for packaging. Instead of localizing the plastic molding around each particular product, plastic is used to encapsulate all of the products on a common lead frame or its separated portions, i.e., molding "blocks", during the USMP process. By simultaneously encapsulating the large-sized lead frame, the need for a special molding tool for encapsulation is eliminated. As a result, a plurality of products may be simultaneously manufactured from a common mold tool in a single leadframe, a mold tool that may be shared with other package types and leadframes.
For example, fig. 10A shows an IC leadframe 105 designed for USMP fabrication including an IC chip and individual leadframe patterns 106, leadframe frames 108, and leadframe cross frames 107. Fig. 10B illustrates USMP leadframe 105 being encapsulated with a single molded plastic block 109. Fig. 10C illustrates USMP leadframe 105 and mold block 109 in a cut away view showing the IC chip and the plurality of arrays contained within individual leadframe patterns 106. Fig. 10D shows USMP leadframe 105 covered by three different plastic blocks 110A, 110B, and 110C, collectively comprising USMP molded block sections. The same lead frame may be used to fabricate either a leaded or leadless IC package, depending on the laser plastic removal and singulation process.
The same lead frame for the IC may also be adapted to manufacture power packages using USMP processes and methods. For example, fig. 10E illustrates that USMP power split leadframe 111 includes a power semiconductor die, an individual leadframe pattern 112, leadframe frame 108, and leadframe cross frame 107. Fig. 10F shows USMP leadframe 111 being encapsulated from a single molded plastic block 109. Fig. 10G illustrates USMP leadframe 111 encapsulated from a single molded plastic block 109. Fig. 10H shows a USMP leadframe 111 covered by three different plastic blocks 110A, 110B, and 110C, which collectively include USMP molding block segments for the fabrication of power packages.
Although the mold block is used in a leadless QFN manufacturing process, the mold block is not compatible with pin IC packages and power packages at all, except for the USMP process disclosed herein.
Laser plastic and pin definition, singulation in existing packaging techniques, one of the undesirable consequences of the molding block is that there is no way to produce pin packages, i.e., a process in which a molding block is singulated inevitably results in a leadless package, which is an edge without pins protruding laterally beyond the plastic. In other words, in today's packages, traditional methods are used to quickly remove plastic from the street naturally and also inevitably cut through the metal pins, and vice versa. For example, during die cutting into individual pieces, the sharp corner edge of one mechanical die completely cuts both plastic and copper pins, cutting each package from its neighbors and leaving the sharp corner edge of one mechanical die completely cut both plastic and copper pins. Also during sawing into singulated, the saw blade completely cuts through both the plastic and copper leads, severing each package from its neighbors and leaving residues of metal and plastic on the vertical sidewalls between each other. In practice, there is no way to mechanically remove the plastic without cutting the metal.
It is envisaged that wet chemical means to remove the plastic without etching the metal pins are possible, the process of wet etching the plastic is slow, imprecise and expensive. The corrosive chemicals required to perform the plastic etching may also damage, oxidize or corrode the metal pins, affecting package reliability and pin solderability. The electrical stability of the packaged device or integrated circuit is affected by the penetration of the package with ion chemical energy generated by the etching process. As an alternative, plasma etching, i.e., dry etching, finished packaged products can cause ionic charges to accumulate within the package and on the semiconductor chip, affecting the operation and electrical characteristics of the device. Furthermore, chemical etching, whether wet or dry, involves the use of a photomask to define where the plastic is etched and removed, which adds cost. In addition to its disadvantageous costs, today, a completely new tool and manufacturing process is developed before such a method is applied without performing the molding of the lead frame. In this way, it is not skilled to etch the package streets by chemical and mechanical methods, and dicing by dicing or punching represents a standard method.
However, in the disclosed USMP process, unwanted plastic is removed from streets between chips by a laser process, wherein the laser energy is precisely controlled so that the plastic can be removed without damaging or cutting the copper lead frame. After the laser removes the plastic, the attached copper pins are then severed by stamping, cutting, or in a preferred embodiment, also laser removing. On the same production line, if a laser is used for both plastic removal and copper pin cutting, the positioning of the laser can be adjusted to create any one of no pins, pins or power packages.
In fig. 11A is shown an example of plastic removal and pin severing, i.e., "street fabrication", during USMP manufacturing. The three cross-sectional views illustrate the encapsulation of two adjacent chips, namely, encapsulation a and encapsulation B, and the intermediate streets therebetween delineated by dashed lines in three consecutive manufacturing steps. The cross-sectional view 120 shows the step of molding plastic 127A and copper conductors 128A extending through the street between package-a and package-B. The plastic also fills the bottom visible portion of package a 131A and package B131B.
In the second figure, the cross-section 121 shows that the laser beam 130A is used to remove portions of the plastic 127A from the street, i.e. between the dashed lines, and additionally to remove portions of the plastic 127A on both sides of the street, i.e. over the copper conductors 128A within the packages a and B, while the encapsulating plastic of the chip area will remain and unaffected, i.e. the plastic capsule 127B survives the process and the encapsulation of package-a and the plastic capsule 127C survives the encapsulation of package-B. By means of the optical scanning by the laser 130A, which plastics are removed and which are unaffected.
The optical scanning includes parameter control of the position of the laser, adjustment of the laser power and pulse frequency, and different scanning rates and the number of repeated laser scans over a given area. The peak laser power required to remove the plastic varies from 5 watts to 20 watts.For any given peak power setting, the transmission of the average laser power is controlled by a laser pulse, which is a prescribed time t on At a fixed frequency f, the working coefficient D is obtained, where d=t on .f pulse From P ave ＝P.D＝P.(t on .f pulse ) Given average power transfer P ave . For example, a 20W laser operates at a pulse rate of 20kHz and a 50% duty cycle, with a 25 microsecond time every 50 microsecond pulse period, delivering an average power of 10W.
The wavelength of the laser is tuned to maximize absorption through the removed material. Plastics that melt and evaporate relatively low melting point molding compounds can be used in black plastic housings, almost any infrared, visible, or sufficiently powerful ultraviolet laser, for example in the range of 10 watts to 20 watts. However, when removing the plastic sitting on top of the copper, the laser wavelength that is advantageously absorbed by the plastic but not by the underlying copper lead frame metal is applied, meaning that at lower power levels, the plastic can be selectively removed from the street without melting, burning or scarring the underlying metal. Because of the low absorption of light relative to copper and other "yellow" metals, compared to black plastics, laser wavelengths that are attractive for selective plastic removal fabrication according to the present invention include infrared gas lasers such as CO 2 The wavelength is at 10.6 microns, or the wavelength of an infrared solid state or fiber laser such as YAG is at 1064 nanometers.
To further avoid underlying copper scarring during laser plastic removal, the laser power required can be reduced by rapidly and repeatedly scanning the same area with the laser, thereby delivering the total energy E to a particular "slice" of plastic being removed scan Equal to the average laser power P ave As previously described, the number of times is used to scan across slice T SCAN Number of times a given slice is scanned n scan Time required for the number of times, i.e. E scan ＝n scan .P ave .t scan . By using the appropriate wavelength to remove the material, the number n of scans scan Can be minimized, typically from2 to 5 scans. However, if a laser having a wavelength that does not match the material being removed is used, a number of scans from 10 to 30 may be required per slice of the laser. Each slice is scanned repeatedly in a large number, n scan >5, are undesirable as they increase the processing time, reduce the UPH process, increase the risk of scarring of the metal or burning of adjacent materials within the package. For example, ultraviolet or blue laser for cutting copper may require only 3 or 4 scans to remove 200 μm of copper lead frame, while infrared laser such as YAG or CO 2 may require 10 or more scans, resulting in burn marks on the lead frame.
The scanning rate F scan ＝1/t scan Should not be in accordance with the laser pulse frequency f pulse And laser pulse duration t on Confusing, this occurrence is at least one or two orders of magnitude faster than the laser scan. In micromachining, the laser pulses are electronically controlled in the microsecond range, while the laser performs optical scanning using a motor and movable mirrors. One-dimensional scanning, i.e. producing a cutting line along a straight line, may use a single mirror system while two-dimensional scanning requires a single mirror that rotates using two axes, or by using dual mirrors-one for determining the x-axis position control and the other for determining the y-axis control. Mirror positioning can be achieved with a stepper motor with fine adjustment or with a continuously driven rotary motor with only laser pulse generation when the mirror is directed towards the area to be laser. Importantly, because the laser and its operating settings are tuned for plastic removal, after plastic removal, copper conductors 128A continue to secure some of the die to the leadframe without interference from laser 130A.
To estimate the throughput of the process, the laser scan rate must be considered. The linear scan rate may reach 5000 mm/s but is reduced to about 400 to 500 mm/s for accuracy. For a 40 mm wide plastic block, this means that a single scan across the width of the block molding takes about 0.1 seconds. By repeating 4 scans over a slice and dividing a street into 7 slices, a total of about 30 scans can clear a street in the width direction, i.e., about 3 seconds is required to clear the plastic from each street. If a block width is 40 mm and about 40 mm long, the result of a 3 x 3mm product is 15 horizontal and 15 vertical streets, or a total of 30 streets, in the molded block. At 3 seconds per street, the block of plastic may be cleared within 90 seconds, i.e., within 1.5 minutes. Assuming four blocks per leadframe, the total time required for plastic removal is 6 minutes. The time required for smaller packages is longer because there are more streets to clear for any given block of area. Conversely, larger packages may be processed in proportion to lower street densities in a shorter time.
In a third step, shown in cross-section 122 of FIG. 11A, a different laser process, laser 130B, optically scans to remove copper conductors 128A from the street, i.e., between the dashed lines. After the laser, copper pin 128B extends under plastic capsule 127B, while copper pin 128C extends under plastic capsule 127C. Pins 128B and 128C are separated by streets. These and other copper conductors (but not shown in this particular cross-section) protruding from the plastic package body are comprised of conductive feet of the disclosed foot package. The conductive pins have the same Z-shape as the previously mentioned geometry 100G. As shown, plastic capsules 127B and 127C cover the tops of these pins, but do not cover the exposed sidewalls or feet. By removing the metal 128A from the street, not only are conductive feet formed, but the package is mechanically separated from the leadframe and from the package. Thus, the laser 130B manufactures the package foot and performs dicing of the product into singulated.
Laser 130B desirably includes a shorter wavelength than laser 130A by improving light absorption by a yellow metal such as copper to minimize power and duration during metal cutting. Short wavelength lasers, including solid state or fiber lasers, include orange light lasers at 593.5nm, green light lasers at 532nm, blue light lasers at 473nm, blue-violet lasers at 405nm, or ultraviolet lasers at 375nm, 355nm, 320nm, or 266 nm. Excimer lasers, however, are commonly used in semiconductor manufacturing and fine surgery where ultraviolet wavelengths are achieved with inert gases such as xenon, krypton, fluorine and argon activated dimers, and such precision and higher associated costs are often not a reason for package fabrication. The throughput of metal removal and package dicing can be even faster than plastic removal using a laser of the appropriate wavelength.
In an alternative embodiment, laser 130B is replaced by mechanical cutting. In this alternative manufacturing sequence, laser 130A is still used to remove the plastic from the street and reveal the footing, but mechanical cutting defines the length of the footing and performs the cut-out as a single piece. In this version of the process, the existing mechanical cutting equipment can be reused at the same time, is less accurate than laser processing, and the product is subjected to greater mechanical stress during processing. The resulting package is inferior with greater variability in conductive pin length and greater risk of plastic cracking. In addition, the cutting rate must be carefully controlled and frequent replacement of the cutting blade otherwise cutting may damage the metal and bent foot.
While the two laser processes disclosed for street fabrication may be used to produce a footing package as shown in the previous figures, FIG. 11B shows that the technique may also be applied to produce a leadless package. Immediately after molding, starting with the same cross-section 120, in cross-section 123, laser 130A is used only to remove plastic from the street. After laser 130A processing, plastic capsule 127B encapsulates chip-a and plastic capsule 127C encapsulates chip-B, but conductive copper 128A is only exposed in the street. As in the previous example, only the street plastic 127A is removed during the scanning process by controlling the laser position.
In cross-section 124, a second laser process, laser 130B, typically has a higher power and energy level than laser 130A, is used to cut and remove copper conductors 128A from the street. Since the removal of plastic by laser 130A and metal by laser 130B both have the same edge defined as the edge of the street, the plastic and metal form a flush standing wall at the edge of the package. As shown, conductive copper leads 128B are flush with the vertical edge of die-a defined by plastic encapsulant 127B, which is equivalent to a conventional cut leadless QFN or DFN package in cross-section. Likewise, the conductive copper pin 128C is flush with the vertical edge of the chip-B defined by the plastic capsule 127C. Street fabrication and die singulation in the USMP process is a single use of lasers over dicing in conventional QFN fabrication because of the improvement in accuracy, reduced stress on the packaging plastic, reduced risk of plastic cracking, smooth packaging edges, and reduced risk of metal-to-plastic delamination.
In addition to improving its quality and throughput, this USMP process enables both foot and leadless packages to be manufactured in the same factory and production line without the need for retrofit equipment. The USMP process is versatile in that it is compatible with the use of wave soldering and pins, i.e. "feet", packaging and leadless QFN and DFN packaging using flexible molding blocks. In contrast, conventional dicing or die-cut QFN processes can only produce leadless packages-packages that are incompatible with low cost wave soldering based on PCB factories.
By simply changing the position and laser scanning, a common production line can manufacture a wide variety of street and capsule edges designed for footing and leadless packages. For example, in fig. 11C, an alternative capsule edge design is possible in which plastic covers the side walls of the Z-shaped pins 100G. The laser 130A, which starts with the same cross-section 120 after molding, is used to remove plastic from the street and expose the footing portions of the conductive copper 128A, but not the vertical sidewalls of the Z-shaped geometry 100G (see 125). Laser 130B then cuts portions of conductor 128A in the street, but leaves the footing of conductive pin 128B of chip-a and the footing of conductive pin 128C of chip-B (see 126).
By controlling the lateral energy distribution of laser 130B, the resulting foot shape of conductive pins 128B and 128C can be adjusted, as shown in fig. 12A. For example, if a square energy distribution 136 using energy E is shown in FIG. 135 with respect to position y, the resulting foot would remain as a square. However, if the smooth-edged energy distribution 138 shown in fig. 137 is used, the foot edges of the pins 128B and 128C will be rounded 129, facilitating easier solder climbing during PCB assembly. The energy E is a combination of the average pulse power and the number of repetitively scanned gratings across the same region. The more sweeps at the same location, the higher the power during the laser, the longer the pulse duration or higher the duty cycle increases the energy transferred while fewer sweeps, lower power, shorter pulses or lower duty cycle decreases the energy transferred. The removal of metal ion energy by controlling the power and by the laser is a controllable parameter, a benefit that is not possible using prior art stamping and cutting techniques.
As previously described, the black plastic used in semiconductor packages can be easily absorbed from the entire spectrum of the ultraviolet to infrared wavelength range. However, copper and other yellow metals reflect for various wavelengths, the impact of the laser beam is a weaker absorption. In the manufacturing industry, weak laser absorption results in a large number of scans resulting in low UPH productivity. Reflected light is also dangerous, risks damaging the laser head from the reflected beam, and equipment design failure, and even constitutes a safety concern for the operator.
Fig. 12B shows a graph of absorption spectra for various common metals, i.e., absorption in the x-axis versus light for wavelengths in the y-axis. Infrared lasers, e.g. CO 2 The laser wavelength 141A of the gas was at 10.6 μm and the YAG fiber laser wavelength 141B was at 1064nm versus the visible solid state laser wavelength 141C at 532nm and the UV solid state laser wavelength 141D at 355nm. As shown, steel and iron (Fe) are easily absorbed in the infrared spectrum exceeding 1. Mu.m. In contrast, yellow metals including copper 140, gold and silver have poor absorption in this infrared, and have high absorption of light shorter than 600nm, i.e., in the ultraviolet and short visible spectrum. Using this graph, the USMP process can thus be optimized.
Plastics can be removed with an infrared laser exceeding 1 μm, for example a YAG fiber laser at 1064nm, resulting in evaporation of the plastic with minimal absorption from the underlying copper leadframe;
to define package footings, dicing into individual chips and bond bars, the metal is removed using a solid state UV or visible laser with a wavelength less than 600nm, such as a yellow orange laser at 593.5nm, green light at 532nm, blue light at 473nm, violet blue light at 405nm, or an ultraviolet laser at any 375nm, 355nm, 320nm, or 266 nm.
The precision servo-controlled mirror is used at a sufficient distance from the stationary leadframe pad to process the commodity, and the available laser can cover a large area without moving the laser head or the platen. It is not necessary, though, to process the leadframe on a block and then mechanically advance the platform. According to the USMP method, the entire lead frame can be processed 80mm by 250mm without moving a laser head or stage after loading by scanning the beam. Laser processing of lead frames is shown in fig. 12C, where laser head 142 scans a laser beam across lead frame 105, including copper lead frame 108 and three molded blocks, including plastic blocks 110A, 110B, and 110C. The middle region 107 is represented by a frame 107 supporting the leadframe.
In the example shown, each block is successively lasered, starting with the processing of block 110A via laser scan 143A, then with the processing of block 110B by laser scan 143B, and finally with the processing of block 110C by laser scan 143C. If different types of lasers are used for plastic and copper removal, it is necessary to unload the leadframe after processing from the laser first used for plastic removal and transfer it to another definition for pins, copper removal, dicing into singles, and tie-bar removal. The laser pattern of each molded block will occur twice in succession throughout the process, once for plastic removal and a second time for metal removal.
The size of a block is arbitrary based on providing sufficient mechanical support to the leadframe with frames and cross frames to prevent sagging or warping of the leadframe during manufacturing and processing. While the number of blocks may vary from 1 to any number, typically 3 to 12 blocks are sufficient to provide adequate support, most manufactured package types have a large number of individual components per leadframe. If the block is too small, the block may not be an even increment of the package size, i.e., pitch, and valuable leadframe area would be wasted. Each block may be processed from 1 to 15 minutes, depending on the size of the block and the pitch at which the package is manufactured. Fine pitch packages contain more streets and require more time to process. Nominally, the leadframe may be processed in 10 to 20 minutes.
In addition to selecting the appropriate laser wavelength to remove plastic and copper, the USMP manufacturing process can be optimized by scanning algorithms employed in street manufacturing. The line grating of the laser beam in a manner used in DLP mobile projection and LCD televisions is an inefficient method because most lead frames retain plastic and do not require laser machining. Instead, it is best to machine the area where only laser light is needed, for example by first lasing the lateral streets as shown in fig. 12D, and then lasing the longitudinal streets as shown in fig. 12E. Lead frame 105 shows a footed package with 12 feet, 3 feet on one side. The beam scan 130A removes plastic in the lateral streets during plastic removal; the beam scan 130C then removes the plastic of the longitudinal streets. After plastic removal, laser removal occurs in a similar fashion, where beam scan 130B removes copper in the lateral streets; the beam scan 130D then removes copper on the longitudinal streets.
As previously described, the width of the removed plastic beam sweep 130A and the width of the removed copper beam 130B are different during USMP to determine the length of the package foot. Each laser scan actually includes a plurality of laterally displaced "slices" of scanned material. For example, as shown in FIG. 12F, plastic cleaning beam 130A includes 145A through 145J 10 independent scans, while laser copper removal beam 130B includes 144A through 144G 7 independent scans, each having a spot of 44 μm size 146. While smaller spots are possible, 20 μm to 50 μm spots are preferred to reduce the number of slices required for laser scanning. However, an excessive dot size is not preferred because it limits the resolution of the package features. The slices may overlap slightly without any adverse effect, in fact it is preferable that they overlap slightly. Without overlap, seven slices per 44 μm wide would result in a plastic cut of 308 μm but the total width of the copper removal beam 130B is only 300 μm. Non-overlapping laser beams create defective products because residual metal and plastic are problematic and metal can be present in the street manufacturing process.
The resulting foot package from leadframe 105 is shown in fig. 12G, including laser defined plastic body 110Z and conductive foot 147. For reference, both the locations where the transverse laser beam 130B removes copper and the longitudinal laser beam 130D removes copper are included.
In manufacturing a quad-pod package, special consideration must be given to how the tie bars are removed during pin formation and singulation. Connecting bars (illustrated in fig. 12G and 12H by connecting bar 148) are additional pieces of metal that stabilize the leadframe and naturally protrude from the plastic body of the package during fabrication to secure the die pad in place. In conventional pin packages, the connecting bars are mechanically sheared off and the extra metal sheet is removed, i.e. "deslagged", during the singulation process. This process is not suitable for USMP because it adds mechanical stress during manufacture, requires additional equipment, and often results in the possibility of small metals protruding outside the plastic as shown in figure 3I DPAK perspective view 45J.
In the USMP process for manufacturing four-sided foot packages, the linear laser algorithm includes lateral and longitudinal dicing resulting in unwanted artifacts, the remaining segments of the connecting bars 148, which form protruding copper cantilevers from the corners of the chip pad. The artifact can be eliminated by adding a laser scan pattern with the same laser machining. The addition of a combination of transverse laser slices 144A through 144G as shown in fig. 12H serves to include additional slices 149A through 149D to remove the tie bar 148 artifacts. To protect the encapsulating plastic from laser light, which is discontinuous but which only occurs for a short duration in order to direct the laser beam on top of the connecting bar 148. Alternatively, the tie-bar removal may occur as a step separate from the formation of the metal footing.
Parallel fabrication of foot, power and leadless packages according to the USMP process and packages disclosed herein, both the pin and leadless packages may be fabricated on the same manufacturing line, even simultaneously. Fig. 13 is a block flow diagram illustrating the manufacturing process including the steps of starting with one of the methods of manufacturing a patterned lead frame (step 150) disclosed previously herein, followed by die attach by solder or epoxy (step 151), optional clip pin attach (step 152) and wire bonding (step 154). As shown by path 153, the solder clip pin process (step 152) may be skipped if the semiconductor is not a high current split device. After wire bonding, the plastic molding is performed using a separate mold cavity or preferably using a molding block (step 155), i.e., the stencil encapsulates many components. After molding, the laser plastic and pin definition, cut into singles (step 159), including selective removal of plastic using a laser (step 156), followed by laser pin definition (step 157) and tie bar cutting (step 158). The singulated die are then ready for testing and packaging to tape and reel or laminate packaging as required by the placement machine.
Fig. 14A-14J illustrate parallel fabrication of a pin power package, particularly a foot power package, and an IC package including a pin or no-pin package using the same USMP process. Providing a leadframe of the same thickness that is used for both leaded and leadless devices, the same USMP process enables these different package types to be fabricated simultaneously on a common wire by simply changing the leadframe design . There is no need for additional changes in the machining or machine tools. If the thickness of the lead frame and the thickness of the plastic mold cavity are changed, the etching time must be adjusted accordingly.
Fig. 14A shows a cross-sectional view of two copper sheets, copper sheet 170A shown in the upper view being used to fabricate a footed power element package, and copper sheet 170B shown in the lower view being used to fabricate a pin or footed IC package using the USMP method in accordance with the present invention. For illustration purposes, the dashed line identifies vertical column 100A, then L-shaped geometry 100F for forming the package's die pad, L-shaped geometry 100F for forming the foot to the power package's heat sink pad, Z-shaped geometry 100G for forming the package's conductive leads and feet, and etched geometry 101R for electrically separating the package's conductive leads from their die pads. The thickness of the copper sheet 170A may vary from 200 μm to 700 μm, with 500 μm being a common good heat dissipation thickness. The thickness of the copper sheet 170B can vary from 50 μm for smart card applications to 300 μm for power ICs, with 200 μm being a common thickness for most integrated circuits.
The top view of fig. 14B illustrates the back side etching of copper sheet 170A during the fabrication of the lead frame of the bottom power package, wherein mask 171A includes a photoresist or a chemical etch resistant coating to define copper etched areas with openings 172A. Also illustrated in the lower diagram of fig. 14B is the back side etching of copper sheet 170B during the fabrication of a leadframe for a leadless or footing IC package, wherein mask 171B includes photoresist or a chemical etching resist coating includes openings for windows 172B and 172C to define copper etched areas. The copper is then etched through windows 172a,172b and 172C using wet chemistry or dry etching as previously described.
The top view of fig. 14C illustrates the front side etching of copper sheet 170A during the fabrication of the lead frame of the foot power package, as immediately before. Copper sheet 170A as shown includes backside etch cavities 173A resulting from a previous backside etch step, consistent with mask window 172A (fig. 14B). To define the front side copper etched areas, mask 174A includes photoresist or a chemical etch resistant coating including windows 175A, 175B and 175C. Similarly, the lower diagram of fig. 14C illustrates the front side etching of copper sheet 170B immediately prior to the lead frame fabrication process for the bottom power package, including back side etch pockets 173B and 173C resulting from the back side etching process corresponding to the previous back side mask features 172B and 172C (fig. 14B). To define the front side copper etched areas, mask 174B includes photoresist or a chemical etch resist coating including windows 175D, 175E, 175F and 175G.
After masking, the copper is then etched through the windows 175A through 175G using wet chemical or dry etching as previously described. Although the etching sequence shows that the back side etching occurs before the front side etching, the sequence may be reversed without changing the resulting leadframe. Regardless of the order, the resulting leadframe is shown in fig. 14D, with the upper diagram showing a leaded power package and the lower diagram showing a leadless leaded IC package. After front side copper etching, the mask windows 175A, 175C, 175D, and 175G cause the corresponding feet 183A, 183B, 183C, and 183D to be connected to other elements in the leadframe as well, for mechanical support.
Also during front side etching, openings 175b,175e, and 175F merge with back side etch pockets 173a,173b, and 173C (fig. 14C) to form notches 185a,185b, and 185C, cantilever pins 181a,181b, and 181C, vertical posts 182a,182b,182C, and back side pockets 184a,184b, and 184C. The combination of cantilever 181A, vertical post 182A and foot 183B forms the Z-shaped geometry 100G described above, with an independent conductive pin being electrically disconnected from the die pad 180A by the gap 185A of the foot power package made according to USMP process and design.
In an IC package, the combination of the cantilever 181B, vertical post 182B and foot 183C, and the same combination of the cantilever 181C, vertical post 182C and foot 183D, form the same feature as the Z-geometry 100G described above in that an independent conductive pin is electrically disconnected from the die pad 180B by respective gaps 185B and 185C. While the elements of the individual lead frames in the figures appear independent of each other, they are attached to each other by feet 183a,183b,183c, and 183D as part of a single interconnect lead frame while other copper elements are not visible in this particular cross-section. The feet are in turn connected to the leadframe frame in order to protect the whole mechanical structure during processing. In the case where the chip pad 180B is not connected to any conductive pins or feet, the chip pad must be held as a cantilever similar to the geometry 100E by using a temporary tie bar configuration and the plastic of the package is cut away during dicing.
In fig. 14E, a semiconductor chip 190A, which includes a power element or power IC, is attached to a chip pad 180A by a conductive epoxy or solder 191A and a semiconductor chip 190B, which includes an IC, is attached to a chip pad 180B by a conductive or non-conductive epoxy layer 191B. Unless the component conducts current vertically through the back side of the semiconductor die pad, it is undesirable to use solder as the die attach material because the semiconductor die requires back side metallization to be applied to the back side of the wafer during fabrication after thinning, adding unnecessary additional cost and complexity to the semiconductor fabrication process.
In fig. 14F, bonding wires 195A connect the semiconductor chips 190A to 181A cantilevers; bond wire 195B connects semiconductor chip 190B to cantilever 181B, and bond wire 195C connects semiconductor chip 190B to cantilever 181C. Other bond wires are connected to other conductive pins and feet, but are not visible in this particular cross-section. As shown, more than one bond wire may be attached to the same surface of the semiconductor, whereby the bond wire contacts the potential, and the signal or electrode may be the same or may be unique and different. In the case of very high current conduction by the power element, the bonding wire may be replaced by a braze clip pin as described above.
In fig. 14G, the lead frame is molded from plastic 196A and 196B. Depending on the mold cavity tool, the plastic may be molded around each individual chip or preferably from one to five large pieces of plastic each comprising more than one product. The number of products manufactured from a common molding block can range from a few to thousands of units, depending on the chip and package size of the product. The plastic covers the entire block in the molded block, including the streets, chip edges on top of the feet 183A, 183B, 183C, and 183D, and fills the backside pockets 184A, 184B, and 184C and gaps 185A, 185B, and 185C. The thickness of the plastic must also be thick enough to completely cover and glue any bonding wires 195a,195b and 195C or any braze clip pins.
A laser plastic removal step as shown in fig. 14H. Laser beam 198A is scanned to selectively remove a portion of plastics 196A and 196B. The upper diagram shows that in the case of a foot power package, the plastic above the feet 183A and 183B is removed beyond the metal portion, where the portion beyond the chip pad 180A refers to the heat sink pad 180C and a small portion of the exposed vertical post 182A. In the case of a leadless or footed IC package as shown in the lower figures, the plastic above the metal portions of the foots 183C and 183D is removed, with the removed areas extending to and exposed to a small portion of the vertical posts 182B and 182C.
In the case of laser removal of plastic on a molding block, the laser defines the lateral dimensions of the encapsulating plastic rather than the mold cavity. For example, using different lead frames, a single mold block may be used to manufacture a range of products including IC packages at 2 x 2mm, 3 x 3mm, 6 x 6mm, 2 x 3mm, 3 x 5mm or any package shape with pins on two or more sides, or to produce discrete transistor and power packages such as SOT23, DPAK and D2PAK. Alternatively, if molding of a particular product is used, the laser plastic removal step may be skipped or used to augment the design after molding for package customization purposes. It is assumed that the same thickness laser settings of plastic thicknesses 196C and 196D can be used to fabricate both the IC and the power package. However, if the power element has thicker plastic than the IC package, the power setting for laser plastic removal of the power package must be increased relatively.
Finally, as shown in FIG. 14I, in the step of laser pin definition and singulation, a laser beam 199A is used to remove metal pins 183A, 183B, 183C and 183D from the street and form pins that are compatible with wave soldering in controllable lateral lengths and shapes. For example, the length of foot 183F and others (not shown) of the foot power package shown in the upper figures is defined by laser beam 199A. And foot 183E extending from heat pad 180C is defined by the same laser beam 199A. Similarly, the IC package shown in the lower drawing is like a footing package, and laser beam 199A is used to remove all metal from the street and define the length of footings 183G and 183H. Alternatively, if mechanical cutting or stamping is employed, the definition and singulation of the laser pins can be eliminated by their mechanical equivalent. At the same time, compatible with the USMP process flow, mechanical solutions are inferior, because the chip stresses they cause lead to plastic cracking and residues, i.e. plastic residues have to be etched away. Mechanical solutions are also subject to mechanical wear resulting in variability in foot length.
Assuming that the thickness of feet 183E and 183F is the same as the thickness of feet 183G and 183H, the same laser setup can be used to fabricate both the IC and the power package. However, if the power element has a thicker metal pin than the IC package, the power setting for laser cutting of the metal pin in the power package must be relatively increased.
The use of a laser provides a significant advantage over today's traditional mechanical methods in that it enables the foot and leadless packages to be manufactured in the same manufacturing line. The flow of attaching the package to the general-purpose surface as described is that the leaded or leadless package is determined by the plastic removal and the laser relative position defined by the metal. For example, if the width of the cut caused by laser beam 199A is smaller than the width of the cut caused by laser beam 198A, the foot package will be caused to extend laterally from the metal foot beyond the edge of the plastic. However, if the edges of each cutout created by laser beams 198A and 199A are aligned, the plastic and metal will exhibit vertical alignment immediately adjacent the sidewalls without metal protrusion.
In this manner, the foot package shown in the lower diagram of fig. 14I can be converted to a leadless package simply by changing the scan position of laser beams 198A and 199A, as shown in fig. 14J.
USMP packaging the universal surface mount packaging technology and processes disclosed herein utilize flexible and diverse package types, including both leadless and footed packages, wherein the footed packages further include footed IC packages, footed power IC packages, and footed split power packages. The footed USMP IC package and the footed USMP power IC package share a common feature with multiple electrical connections or "foots", but in fact include differences in the IC package chip typically including analog, digital, memory, or microcontroller functions in the semiconductor, which typically do not carry large currents or consume large amounts of power, which can be done by the power IC package containing the semiconductor chip.
The power IC semiconductor chips include an array combination of analog and/or digital control circuits with one or more high voltage or high current switches, voltage regulators, switching power supplies, current limiters, ma drivers, solenoid drivers, lamp and LED drivers, and other interface products. In some cases, the foot USMP IC package may be used for power and non-power applications, in other cases, power IC specific USMP packages may also be implemented by any of a variety of techniques, including:
increasing the thermal reduction and thermal spreading capabilities of the USMP package by using thicker lead frames, exposed die pads, and soldering the heat spreader pads to the PCB;
eliminating bonding wires to reduce on-resistance by using clip pins or flip chip assembly methods;
thermal resistance reduction by chip thinning and conductive epoxy chip attachment;
the split power element requires the same low heat transfer and resistance as the power IC and employs the same techniques as described above, except that the power split element typically conducts a correspondingly higher current and lower resistance than its power IC, is achieved with clip pins, a larger diameter bond wire, or more bond wires. The split transistor and power package generally require 2-7 electrical connections, most widely used are made with three connections, i.e., with a low current gate or input signal, by bonding wire or clip pins to high current source or cathode connections, and by conductive die pads also serving as drain or anode connections for heat sinks.
In addition to fabricating footing and leadless packages, the USMP processes and techniques disclosed herein are also capable of fabricating pin packages for through-hole or surface-mount assembly. The main distinction between foot packages and pin packages manufactured using the USMP process is best illustrated by the cross-sectional views of various types of USMP packages. The cross-sectional views shown in fig. 15A-15F illustrate a cut line with pins, feet or connections from either package edge through the package to the opposite edge.
Fig. 15A compares packages manufactured by footing and leadless USMP, each having a lateral length on the PCB extending from Y0 to Y10. Foot package 220A and leadless package 220B include conductive pins 183G and 183H including segment B, vertical posts 182B and 182C including segment a, cantilevers 181B and 181C including segment C, exposed die pad 180B including segment a, and gap AC between segment a and segment C. Semiconductor die 190B is attached over exposed die pad 180B by intermediate die attach 191B. The bonding wire 195B is electrically connected to an electrode of a surface portion of the semiconductor chip 190B and is connected to the foot 183G via the cantilever 181B. The bonding wire 195C is electrically connected to the other electrode of the surface portion of the other semiconductor chip 190B, and is connected to the foot 183H via the cantilever 181C.
The bottom surfaces of segments a and B are constructed from a common piece of copper to be coplanar in nature. The top surfaces of segments a and C are constructed from a common piece of copper to be coplanar in nature. Outside the street, i.e. laterally below Y0 or beyond Y10, segment D is clear of all plastic and metal. In leadless packages 220B, laser defined plastic 196E extends laterally from street to street, i.e., from Y0 to Y10. In the case of the foot package 220A, the plastic 196D does not cover the package from street to street, but rather extends laterally from Y2 to Y8 over the vertical posts 182B and 182C, only a portion of which is visible beyond the edges of the plastic 196D. Both plastics 196D and 196E extend vertically from the bottom of the plastic rim to cover the upper surfaces of bonding wires 195B and 195C. In the manufacturing industry, both foot package 220A and leadless package 220B are manufactured identically except that a laser is used to remove the lateral extension of plastic 196D defined in foot package 220A between Y2 and Y8, while the lateral extension of plastic 196E in leadless package 220B remains between Y0 and Y10.
Fig. 15B shows two variants of a leadless and footing USMP package made in accordance with the present invention. In foot package 220C, plastic 196F extends over feet 183G and 183H from Y1 to Y9 and completely encapsulates vertical posts 182B and 182C. In leadless package 220D, segment B previously included in the foot is replaced by vertical columns 182D and 182E containing segment a.
Fig. 15C shows that foot USMP package 220E and leadless package 220F include individual die pads fabricated in accordance with the present invention, specifically, wherein die pad 181D includes segment C glued on each side by plastic 196D or 196E.
Fig. 15D shows two variants of a power USMP package manufactured in accordance with the invention. In the foot power package 220G, the semiconductor die 190A includes a power element glued by plastic 196C over the exposed die pad with a conductive die attach 191A. Bond wire 195A electrically connects the metallized surface of semiconductor die 190A to cantilever 181A and through vertical post 182A to foot 183H. The exposed die pad 180A and heat sink pad 180C, along with feet 183J, provide both electrical and thermal conduction. Plastic 196C extends laterally from Y3 to Y9, with the plastic between Y0 and Y3 being removed from heat sink pad 180C to enhance convective cooling.
Also shown in fig. 15D is a power package 220H including a semiconductor chip 190A adhered over isolated die pad 181E at section C and glued by plastic 196C. Thermal energy flows laterally through isolated die pad 181E to exposed die pad 181F and through vertical column 182F to foot 183H. Heat is removed in this way by convection from the surface of the heat pad 181F and by heat conduction through the foot 183K to the PCB.
While the USMP process disclosed herein is capable of manufacturing surface mount packages with chip pads and feet that are substantially coplanar, the process is also capable of producing the ability of pin packages for through-hole or surface mount PCB assembly. The cantilever segment C in such a package facilitates the protrusion of the pins from the center of the plastic and is not coplanar with the back surface of the exposed die pad. Fig. 15E illustrates an implementation of one pin package in which cantilever 181H protrudes from plastic 196C to a length extending from Y9 to Y20. During the fabrication of package 220J, the back side mask layer has an opening extending through segment C and the front side mask layer extends through segment C, with the result that the metal sheet is etched only from the back side of segment C. As a result, the bottom surface of cantilever 181H is not coplanar with the bottom surface of die pad 180A, heat pad 180C, or heat pad foot 183J. This approach TO the USMP process can be used TO produce pin packages such as TO-220, but all mechanical stresses can be relieved without mechanical stamping.
The USMP process may also be used to replace gull-wing packages to completely eliminate the need for imprecise mechanical pin bending. An example of a USMP replacement gull-wing power package 220K is shown in fig. 15F, where cantilever 181L extends from Y9 beyond plastics 196C to Y11. Beyond Y11 is vertical column 182L includes segment A connected to foot 183L and extending to Y12. Unlike conventional gull-wing packages, the cantilever length from Y9 to Y11 is not limited by the need to ensure a mechanical pin bending fixture. Furthermore, since they are all formed from the same piece of copper without any mechanical bending or stamping, the bottom surface of the foot 183L is essentially coplanar with the bottom surfaces of the die pad 180A and the foot 183L. No conventional pin bending process can ensure co-planarity. While the heat sink pad 180C in this embodiment is located on one edge of the package and on the other side of the leads 181L, the leads may be present on two, three or four sides of the package, with or without heat sink pads as desired.
The previously shown cross-sectional views show representative of cross-sectional views taken through the dicing lines and in parallel to the conductive pins. Fig. 16 shows a cross-sectional view taken from a plurality of cut lines parallel to the sides of the package and perpendicular to the conductive leads. The perspective view shows the location of each of the illustrated sections, with the die pad 209 being separated from the cantilevers 205A and 205B by a gap 208, including a gap. The cantilevers 205A and 205B include segments C that connect to the vertical posts 203A and 203B include segments a that in turn connect to the footers 201A and 201B that are laterally separated by the void 202. The vertical surface 210 defines a lateral extension of the plastic of the package, wherein all of the front side of the vertical surface 210 is exposed and the back side thereof is glued.
Section Y1-Y1' shows the cut line passing through feet 201A and 201B separated by void 202. In the plane of the vertical surface 210, the section Y2-Y2 'shows the cut line separated by the plastics 204, 202 through the vertical posts 203A and 203B, and the section Y3-Y3' shows the cut line separated by the plastics 204 through the cantilevers 205A and 205B, at the back plane of the vertical surface 210. Between the end gap 208 of the cantilever 205A or 205B and the chip pad 209, the section Y4-Y4' only shows the presence of the plastic 204.
USMP package features multiple package types and different package features can be manufactured using the USMP manufacturing sequence disclosed herein. The internal structure of the USMP package may vary, and the external package features manufactured by the USMP process may be identified and categorized into several large categories related to PCB assembly, namely:
a foot surface mount package having exposed sidewalls;
foot surface mount packages with non-exposed sidewalls;
leadless surface mount packages;
pin through hole package with straight pins;
pin surface mount (i.e., gull wing) packaging (no pin bending);
the heat sink pad power surface may be adhesively packaged;
combinations of the above;
while the pin packages described above may also utilize pin bending and shaping steps to fabricate conventional gull-wing pins, this does not have any benefit, as the various USMP options described above are superior to mechanically bent pins in both performance and manufacturability.
Fig. 17A shows a perspective, longitudinal, side and bottom view of an adhesive package with exposed sidewall foot surfaces. In perspective view 250, plastic package 251 includes at least one conductive pin 252 protruding from the package body coplanar with the bottom of the package. The footing includes copper plated with a solderable metal such as tin, silver, palladium, nickel, etc. that is used to solder the package to the PCB and is compatible with wave soldering and solder reflow assembly.
In wave soldering assembly of a foot package, solder is applied from above after the package is glued or adhered to the PCB. The solder is applied in molten form to the package and PCB but adheres only to the metal surfaces, i.e., the exposed feet 252 and possibly also the exposed sidewalls 253. In wave soldering assemblies, no solder has been applied under the feet 252 prior to placement of the components. The resulting solder is easily inspected using automated optical inspection methods to determine that a properly completed solder is an easily inspected solder adhesion.
The foot package shown in fig. 17A is also compatible with assembly processes using solder reflow. In solder reflow assembly, solder is applied to the PCB and melted into place prior to component placement. The package is then placed over the hardened solder and secured to the PCB with an adhesive or mechanical support, and the PCB is typically fed into a furnace or oven on a slow moving conveyor. The temperature of the oven is selected to be sufficient to re-melt the solder on the PCB as it passes. The melted solder then adheres to the conductive feet 252 of the package in liquid form and wets the sides of the feet, possibly by surface tension. Because the solder is melted onto the PCB prior to component placement, and melted a second time, this process is known as the "reflow" assembly process of the solder. Reflow PCB assembly is slower and involves more expensive production equipment than wave soldering assembly. Typical wave soldering assemblies require X-ray inspection to confirm the quality of the solder joint.
The peculiarity of the foot USMP package is that it is wave soldering compatible with reflow soldering. Specifically, the package is suitable for wave soldering because the solder readily flows over the feet 252 and portions of the vertical side walls 253, however, as shown in the bottom view, it is apparent that the feet 252 include a conductor that protrudes beyond the plastic 251. This large metal pad is exposed to the bottom surface of the package, has an equal or greater total metal area than current leadless packages such as QFN or DFN, providing a sufficient area for reliable solder reflow adhesion. With proper PCB design, solder can also be redistributed during reflow by the top and sides of the surface Zhang Liyu feet 252, even in a reflow assembly line to facilitate optical inspection.
Fig. 17B shows a perspective, longitudinal, side and bottom view of the foot surface mount package. In perspective view 260, the plastic package 261 includes at least one conductive foot 262 protruding from the package body coplanar with the bottom of the package, but does not include a metal vertical sidewall to which solder wets. As with the previously described packages, this variation of the foot package may be assembled onto a PCB using wave soldering or reflow soldering.
Whether the vertical conductive sidewalls are beneficial or a matter of preference at a particular PCB assembly plant. Eliminating the vertical conductive sidewalls reduces the risk of accidental shorting between the package foot and any exposed connecting bars, but with proper design rules, the risk can be completely alleviated. The advantage of exposing the vertical sidewalls is that it provides additional area for soldering and is easily confirmed by optical inspection, but only proper machining of the foot package can reliably produce the same effect. Thus, in essence, there is no distinction between the two versions of the foot package. The remainder of the description applied throughout this foot package will depict the package having exposed vertical sidewalls, but it should be understood that non-exposed sidewall versions may be substituted if desired.
Fig. 17C shows perspective, longitudinal, side and bottom views of a leadless surface mount package. In perspective view 270, plastic package 271 has no conductive feet or pins protruding from the package body and no metal for the solder to reliably adhere thereto. The vertical conductive side walls 273 are not soldered sufficiently to ensure solderability using wave soldering assembly. Unlike the previously described foot package, this variant of the USMP package can only be assembled to PCBs using solder reflow. The key point of this pattern is that the USMP process can be exactly repeated to make existing leadless packages such as QFN and DFN using the same USMP manufacturing process to make wave soldering foot packages and even to make through hole pin packages, thus the nickname of the package is "generic".
A perspective, longitudinal, side and bottom view of a variation of the USMP manufacturing leadless package is shown in fig. 17D. In this version, shown in perspective view 276, the leadless landing pad includes only one foot 277 instead of the entire conductive post, such that the exposed vertical sidewall is replaced by the vertical sidewall of foot 277, including the entire plastic 271 except for its sidewall and bottom edge. The bottom view of this variation is the same as the previously described feet 275. In another alternative embodiment shown in fig. 17E, feet 279 are inserted from the edge of plastic body 271 and no metal is present on the package side walls as depicted in perspective 278.
An example of a pin package fabricated using this USMP method is shown in fig. 18A, which includes perspective, longitudinal, side and bottom views. While the USMP process is designed to produce a surface mount package, the package shown in perspective view 280 is a pin package designed for through-hole PCB assembly rather than surface mount. As with the pins 286 protruding from the package body 281 in this way, are near the center of the body of the plastic package and are not coplanar with the bottom surface of the package. A shadow or optical "projection" 287 of the pin 286 is shown on a plane defined by the bottom of the plastic 281 to clarify the three-dimensional position of the pin.
For completeness, this USMP process may be used to make a "pin surface mount package" shape similar to a gull-wing package but without any pin bending. This type of package is shown in perspective view 290 of fig. 18B. Includes metal pins 296 protruding from the plastic body 291 and connected to the bottom pins 292 intersecting the vertical posts 293. The feet 292 are precisely coplanar with the bottom of the package and plastic 291 because no bending is involved in manufacturing the pins. A shadow or optical "projection" 297 of the pin 296 is shown on the same plane as the plastic 291 and the bottom surface of the foot 292 to clarify the three-dimensional position of the pin element.
The USMP process also enables the fabrication of heat sinks for power packages. In the perspective view 300 of fig. 18C, thick metal heat sink pads 303 protrude from the plastic 301 to facilitate improved heat transfer to the PCB and enhanced convection into the air. As shown, a thick metal heat sink pad 303 is attached to the foot 302 to provide wave soldering compatibility, a feature not provided by conventional manufacturing heat sinks. Foot 302 may be located along one edge of heat sink pad 303, as shown, or may circumscribe heat sink pad 303 along all or a portion of its perimeter.
In summary, the various packaged visible elements that can be manufactured with this USMP process include the geometric elements previously described in fig. 9A-9D. In particular, in a foot package only the foot protrudes beyond the package plastic, in a pin package the cantilever arm protrudes from the plastic, in a power package the entire vertical post protrudes beyond the package body, whereas in a leadless package no metal extends significantly beyond the outer edge of the plastic.
Internal structure of foot package manufactured by USMP to demonstrate the versatility of USMP processing to manufacture a wide variety of packages, cross-sectional views are useful for illustrating exemplary package internal structures. In an asymmetric package, such as a foot DPAK or a foot DFN, the cross-section in the longitudinal direction, i.e. transverse to the pin, will be different from the cross-section in the transverse direction. In a quad-pod, the profile is typically symmetrical between the longitudinal and transverse directions with no distinction being made, except possibly for the length of the pod in that direction.
Fig. 19A includes a cross-sectional view of the exposed and isolated die pad USMP leadframe in the longitudinal packaging direction, particularly a single foot and separate feet connected by die pads along a tangent line. The cross-sectional view of the leadframe is "asymmetric" with respect to an imaginary center line because the features of the leadframe are not mirror images on opposite sides of the center of the package, i.e., the left side and the right side are different. The cross-sectional view 340A, representing the tangent line A-A', shows an exposed chip-pad package in which the chip pad 351A is connected to the foot 352A on the side and the cantilever 353A, vertical column 354A and foot 352B form a Z-shaped conductor and the foot is not electrically connected to the chip pad 351A. The plastic encapsulated leadframe and semiconductor die (not shown) include an upper half 350A and a lower half 350B to form a void-free uniform encapsulation. The lower edge of the plastic 350B is coplanar with the bottom surfaces of the feet 352A and 352B, the vertical posts 354A, and the exposed chip pad 351A. The section 340C at the tangent C-C' shows that the exposed die pad 351A is replaced by a cantilever portion of the isolated die pad 353A comprising a leadframe.
Fig. 19B includes a cross-sectional view of a leadframe for exposing and isolating a die pad USMP, particularly along a tangent line of symmetry through the die pad and connecting bars. In section 340B, which is taken along line B-B', it is shown that exposed die pad 351A includes cantilevered portions of connecting bars 353C and 353D, including lead frames, surrounded by plastic 350A and 350B. The side edges of the connecting bars 353C and 353D do not protrude outside the plastic package body. The lower edge of the plastic 350B is coplanar with the bottom surface of the exposed die pad 351A. In section 340D, which is shown as a cut line D-D', the isolation die pad 353E includes a cantilevered portion of the leadframe that extends through the entire plastic body. Since the separated chip pads merge with the connecting bars, they are indistinguishable in this section.
Fig. 19C includes a cross-sectional view of the exposed and isolated die pad USMP leadframe, particularly through the die pad connection feet along a symmetry cut. Section 340E at line E-E' shows exposed die pad 351A connected to feet 352A and 352B on opposite sides of the package and glued to its upper surface by plastic 350A. Section 340F at line F-F' shows that the isolated die pad 353F is connected to the bottom pins 352A and 352B on opposite sides of the package, and the upper 350A and lower 350B sides are glued with plastic.
Fig. 19D includes a cross-sectional view of a USMP leadframe for a power package exposed die pad, particularly showing a cut through the heat spreader pad and the foot. Exposed die pad 351A is shown in section 340G at tangent line G-G' extending beyond encapsulant 350A to form heat dissipation pad 355. Feet 352A are connected to heat sink pads 355 to facilitate wave soldering capability. At the other edge, cantilever 353A, vertical column 354A and foot 352B form a Z-shaped conductor and the foot is not connected electrically to chip pad 351A. The lead frame and semiconductor chip (not shown) are plastic encapsulated, including an upper half 350A and a lower half 350B to form a void-free uniform encapsulation. Section 340H at the H-H' tangent represents the connection of exposed die pad 351A to cantilever 353G, vertical column 354B and foot 352B. Cantilever 353G sits above plastic 350B. The bottom edge of the plastic 350B is coplanar with the bottom edges of the feet 352A and 352B, the exposed chip pad 351A, and the heat sink pad 355.
Fig. 19E includes a cross-sectional view of an exposed die pad USMP leadframe along a tangent line through the heat spreader pad and the connecting bars. Section 340J at tangent J-J' shows the exposed die pad 351A connected to the heat sink pad 355 and foot 352A, while cantilever 353D sits above plastic 350B laterally to the edges of plastic 350A and 350B at the opposite edge.
Fig. 19F includes a cross-sectional view of the exposed and isolated die pad USMP leadframe along a tangent line of symmetry through the feet without connection to the die pad. Specifically, the cross section 340K at tangent line K-K' shows that the Z-shaped conductors and feet include cantilever 353A, vertical post 354A, and foot 352A are located adjacent to but electrically spaced apart from exposed chip pad 351A. Symmetrically, the opposite edge of the package includes another Z-shaped conductor and foot electrically separated from each other, including cantilever 353B, vertical post 354B, and foot 352B. The plastic encapsulant includes an upper half 350A and a lower half 350B to form a void-free uniform encapsulant. The bottom edge of plastic 350B is coplanar with feet 352A and 352B and with isolated die pad 353H, which is surrounded by plastic 350A and 350B on four sides, includes a cantilevered bottom edge. Electrical properties such as the die pad 353H are isolated from the back side of the package and from any adjacent feet.
Fig. 19G includes a cross-sectional view of a leadframe for exposing and isolating a die pad USMP, particularly along a scribe line through the die pad without crossing the feet or connecting bars. For example, section 340M, representing tangent M-M ', illustrates die pad 351A surrounded by plastics 350A and 350B, while section 340N, representing tangent N-N', illustrates isolated die pad 353H surrounded by plastics 350A and 350B.
Fig. 19H includes a cross-sectional view of an exposed die pad USMP leadframe along a tangent line of symmetry through a dual die pad with and without a connecting bar. Section 340Q, representing a tangent line Q-Q', illustrates two die pads, particularly exposed die pads 351A and 351B surrounded by plastic 350A and 350B. In section 340P, which is shown as tangent P-P', the two die pads are connected to the cantilevered connecting bars extending to the edge of the plastic body, particularly where exposed die pad 351A is connected to connecting bar 353C and die pad 351B is connected to connecting bar 353D.
Fig. 19I includes a cross-sectional view of an isolated die pad USMP leadframe along a tangent line of symmetry through a dual die pad with and without a connecting bar. Section 340S, representing a tangent S-S', illustrates two die pads, particularly isolated die pads 353J and 353K surrounded by plastic 350A and 350B. The section 340R at the tangent line R-R' represents the two die pads connected to the cantilever connection bars extending to the edge of the plastic body, but they are not different in the figure because the cantilever connection and isolation die pads are formed by the same cantilever.
Fig. 19J includes a cross-sectional view of a hybrid isolated and exposed die pad USMP leadframe along a tangent line of symmetry through a dual die pad with and without a connecting bar. The section 340U, representing the tangent line U-U', illustrates two die pads, particularly an exposed die pad 351A and an isolated die pad 353K surrounded by plastic 350A and 350B. The section 340T at the tangent T-T' represents the edge of the two die pads that are connected to the connecting bars that extend to the plastic body. As shown, the exposed die pad 351A is connected to the connecting bar 353C including a cantilever. The isolated die pad 353K is similarly connected to the cantilever connection bar, but since the die pad is formed of the same cantilever, the isolated die pad and connection bar are not distinguishable from each other in the figure.
Fig. 19K includes a cross-sectional view 340V of a dual-isolation die pad USMP leadframe, particularly depicting a symmetry cut V-V' through isolated dual die pads 353L and 353M, corresponding vertical posts 354A and 354B, and corresponding die pad connections to feet 352A and 352B.
Finally fig. 19L shows a cross-sectional and bottom view of Z-shaped conductors and feet not connected to the chip pad including cantilever portion 353A for wire bonding, vertical post 354A and feet 352B. The exposed metal on the back of the package, both from the bottom and cross-sectional view, includes a portion of the overlapping plastic 350A and another portion protruding beyond the edges of the plastic. In subsequent figures of the present disclosure, the Z-shaped conductors and feet will be represented as a shaded foot depicting a portion visible from the bottom connection of the package and a thin line extension representing the cantilever portion inside the plastic 350A and indistinguishable from the outside of the package, from the bottom of the package, except by using X-ray inspection. The portion of the long dashed line is to avoid the situation where the subsequent illustrations may not be to scale, but it is also straightforward to alert the reader that the square foot is part of the Z-conductor.
Examples of dual USMP foot packages the following illustrations depict various types of dual sided package structures that may be fabricated using the USMP processes and methods disclosed herein. A dual package is one in which pins or feet are present on opposite sides of the package. The dual package may be square or rectangular. In rectangular packages, the longer dimension is referred to as the longitudinal direction of the package, whether it has connections, i.e., pins or feet, on those edges or edges perpendicular to those edges. The drawing generally includes a perspective view and two bottom view illustrations of the package-one using an exposed die pad and the other the same package including an isolated version. The perspective view of the exposed die pad and isolated version is the same in most cases.
Relevant section tangents from the previous section are identified in the bottom view to explicitly identify the structure of each package. In addition, any footing dual-sided package using the USMP process can be converted into a dual-sided leadless package, i.e., no footing extends beyond the edge-outside DFN equivalent bottom area of the plastic body, metal is simply removed by linear laser cutting, for which the same area and edge are used to define the plastic removal. For brevity, the next dual-encapsulated USMP no-pin version will be excluded from the figure.
Fig. 20A-31 illustrate the very wide variety of single-chip and multi-chip packages that can be fabricated from top and bottom surfaces and, in some cases, from perspective views that are depicted for use with the USMP methods and apparatus disclosed herein. The cross-sectional views labeled for a single chip pad package correspond to those shown in fig. 19A-19G (i.e., tangents A-A ', B-B ' … N-N ') and the cross-sectional configuration thereof is described in detail, and the labeled cross-sectional views for a multi chip pad package correspond to those shown in fig. 19H-19K (i.e., tangents P-P ', Q-Q ' … V-V '), and the cross-sectional configuration thereof is described in detail in fig. 24C-24J (i.e., tangents W1-W1', W2-W2' … Z4-Z4 '). A detailed comparison of the top surfaces and cross-sectional views of the Z-shaped conductors and feet is also included in fig. 19L.
The drawings included are schematic representations of the packages and their elements made by the various USMPs, rather than CAD drawings that are dimensionally accurate. Although the dimensions of the typical drawing are primarily accurate, in many cases the exact dimensions are not exactly the same, for example the Z-shaped conductor and cantilever section of the foot may be longer than what is depicted by the drawing in bottom view. Such as those depicted primarily for purposes of illustration of USMP elemental components, such as packaged die pads, feet or pins, Z-conductors, cantilever extensions, and non-limiting tie bars. It will be appreciated by those skilled in the art that the dimensions can be increased or decreased without affecting the general features that may be created by the USMP manufacturing process.
As shown, various views of fig. 20A, including a single chip pad 2-foot USMP370 package, show compatibility with either a single chip pad or an exposed chip pad. Such packages are useful for packaging components having two electrical connections, such as semiconductor diodes including PN, zener and Schottky diodes, transient voltage suppressors, voltage clamps, current limiters, and other two terminal components. The foot package includes plastic 371, feet 372, and wide feet 373 as shown. The connecting bars 374 and the package feet are connected to the matrix array of lead frames, keeping the package in a fixed position during manufacture.
In the lower left illustration, to maximize the available chip size and reduce the thermal resistance of the package, the exposed chip pad 376 is connected to the wide foot 373 as depicted along cut line A-A' and shown in previous fig. 19A. The cross-sectional view along the tangent line B-B 'shown in the previous fig. 19B is a cross-sectional view depicting the corresponding connection of the connecting bars perpendicular to the tangent line A-A'. Similarly, in the lower right hand corner illustration, to maximize this chip size, wide foot 373 is connected to isolated chip pad 377, as depicted along tangent line C-C 'and along connecting bar tangent line D-D', respectively, as shown in the cross-sectional views corresponding to FIGS. 19A and 19B, previously. The thermal resistance of the isolation package in the isolation chip pad package is not lower than that of the exposed chip version, and a large amount of heat is conducted through the cantilever chip pad, down to the foot of the chip pad connection, and into the PCB.
A variation of the prior art single chip pad 2-foot USMP380 is shown in fig. 20B, wherein the second isolation foot 382 is fabricated to be as wide as the chip pad connection foot 383. The profile is the same as previously shown. FIG. 20C further illustrates the use of the three-sided foot design to eliminate the tie-bars by extending the chip pad tie-feet on three sides of the package to extend the maximum chip size of the package. For example, in the exposed chip pad version shown in the lower left view, exposed chip pad 396 is connected to feet 393 on three sides.
While the longitudinal cross-sectional view depicted by the tangent line A-A 'remains unchanged from the previous version, the transverse cross-sectional view is different as depicted along the tangent line E-E' by the previously depicted transverse cross-sectional view representation of fig. 19C. Likewise, the isolated chip pad version of the same package is shown in the lower right plot with three-sided foot 393 connected to isolated chip pad 397. While the cross-sectional view of fig. 19A previously shows that the longitudinal cross-sectional view depicted along the tangent line C-C 'remains unchanged from the prior version, the transverse cross-sectional view is different and representative of what was depicted along the tangent line F-F' by the corresponding cross-sectional view previously shown in fig. 19C. In another embodiment of the same 2-foot package, the three-sided foot is combined with a wide foot 402 as shown in the plot of fig. 20D.
The size of the USMP foot package with two electrical connections can be adjusted according to the current rating and the chip size of the packaged product. For large area chips conducting higher currents, multiple bond wires, flip chip packages or copper clip pins may be used to connect the top surface of the chip to other connections. For components intended to dissipate large amounts of heat, this exposed chip pad version is preferred because of its lower thermal resistance and better heat dissipation capability.
Fig. 21A includes various views of single chip pad 3-foot USMP 410 compatible with isolated or exposed chip pads. Such a package is very useful for packaging elements with three electrical connections, such as bipolar transistors, small signal MOSFETs, JFETs, power MOSFETs, high voltage MOSFETs, three terminal regulator ICs, low dropout linear regulators or LDOs, and shunt regulators, or any three termination elements, as long as they do not exhibit excessive heat generation. High power components such as thyristors and IGBTs typically require a power package with a heat sink and are therefore unsuitable for use with this particular type of foot USMP.
The foot package is shown to include plastic 411, feet 412A and 412B wide feet 413. The connecting bars 414 and the package feet are connected to the matrix array of lead frames, maintaining the package in a fixed position during manufacture. In the lower left illustration, to maximize the available chip size and reduce the thermal resistance of the package, the exposed chip pad 416 is connected to the wide foot 413 as depicted along the tangent line A-A' and shown in previous fig. 19A. The cross-sectional view along the tangent line B-B 'shown in the previous fig. 19B is a cross-section depicting the corresponding connection of the connecting bars perpendicular to the tangent line A-A'. Similarly, in the lower right hand corner illustration, to maximize this chip size, wide foot 413 is connected to isolated chip pad 417 as depicted along tangent line C-C 'and shown in FIG. 19A previously, and along connecting bar tangent line D-D' as previously shown in FIG. 19B. While the thermal resistance of the isolated chip-pad package is not lower than the exposed chip-pad version, a significant amount of heat is conducted through the cantilevered chip pad down to the feet connected to the chip pad and into the PCB.
An improved thermal performance is achieved with a three-sided foot such as USMP 420 shown in fig. 21B. As shown, the maximum chip size of the package is enlarged by extending the chip pad to the package edge, eliminating tie bars and feet connecting the chip pad to three sides of the package. Such as the exposed chip pad version shown in the lower left drawing, the exposed chip pad 426 is connected to the feet 423 on three sides.
While the length of the chip pad 426 remains unchanged from the previous version shown in fig. 19A along the tangent line A-A ', the width of the chip pad 426 is larger, i.e., wider, as depicted in fig. 19C along the tangent line E-E'. Likewise, an isolated chip pad version of the same package is shown in the bottom right view, with three-sided foot 423 connected to isolated chip pad 427. Although the length of the die pad 427 along the tangent line C-C 'and the corresponding cross-section are shown as unchanged in FIG. 19A from the previous version, the width of the die pad 427 is depicted as being greater, i.e., wider, along the tangent line F-F' in FIG. 19C.
At higher power levels, heat sinks are required to further improve heat conduction and convective cooling. For example, fig. 21C shows a 3-foot single chip pad power USMP 430 with a heat sink pad 438. The package includes four feet, 432A, 432B, 432C, and 433; an exposed die pad 436 with a heat sink pad 438 and a connecting bar 434. To be consistent with conventional DPAK and D2PAK designs, the electrical properties of the center leg 432B are shorted together with the exposed die pad as previously described along the tangent line H-H' in the corresponding cross-sectional view of fig. 19D. The feet 432A and 432C are electrically isolated from the die pad 436 as depicted in the corresponding lateral cross-section along the line G-G' by the previous figure 19D, with an electrode typically used as a gate signal and other connections for high currents, such as the source connections of power MOSFETs. To accommodate more additional bond wires for high current conduction, the cantilever 439C is connected to the foot 432C wider than its corresponding foot. Likewise, the cantilever 439A is wider than its corresponding foot 432A. One unique function of the foot USMP power package is to add a heat sink pad to the foot 433 as disclosed, enabling assembly of DPAK with wave soldering. The power package variant 440 is shown in fig. 21D, which may be replaced by a connecting bar 444B depicted along the tangent line J-J' in the corresponding section shown in fig. 19E previously.
The application is different for higher pin count dual sided packages. Packages with 4 to 8 electrical connections typically include linear ICs, power ICs, interface ICs, and even dual MOSFETs, such as one N-channel and one P-channel power MOSFET. For example, fig. 22A illustrates that single chip pad 4-foot USMP 500 includes a plastic body 501, feet 502A-502D, and a connecting bar 504. The foot package may be implemented using the exposed die pad 506 as previously described with respect to fig. 19F, 19B and 19C along transverse tangent line K-K ' and longitudinal tangent lines B-B ' and M-M ', respectively, by corresponding cross-sectional views. The foot package may also be implemented using a single isolated die pad 507 as previously described in fig. 19F, 19B and 19G along lateral tangent line L-L ' and along longitudinal tangent lines D-D ' and N-N ', respectively.
The terms "transverse" and "longitudinal" are any descriptions of the vertical direction and are not intended to limit or define the invention. Generally, the term "length" refers to any longer direction but should not be construed as limiting the flexibility of the package structure in the lead frame-related direction as well as the number of plastic-type or longer or shorter edge feet packaged so as to be maintained as foot-to-foot spacing and foot-to-corner spacing design rules. To allow for foot-to-foot spacing, i.e., pitch from the center of a foot to the center of its adjacent foot, depends on the ability to adhere the USMP at the PCB factory rather than on its manufacture.
The pitch between the feet may vary as desired, and industry standard pin pitch values used in today's gull-wing pin packages are typically used. Common center-to-center pitch dimensions may include 0.2mm, 0.35mm, 0.4mm, 0.45mm,0.5mm, 0.8mm, 1.0mm, 1.27mm, and 1.5mm. In some cases, such as in high voltage applications, a larger size may be achieved, not by introducing a new pitch, but by omitting the foot from the package standard pitch size, while maintaining the rest of the package foot. For example, one USMP manufacturing foot package with standard feet of 0.45mm pitch can achieve a 0.9mm pitch by omitting feet from the package.
Fig. 22B shows that single chip pad 6-foot USMP 510 includes a plastic body 511, feet 512A through 512F, and connecting bar 514. The foot package may be implemented using the exposed die pad 516 as depicted along the lateral tangent line K-K 'and the longitudinal tangent lines B-B' and M-M 'as depicted by the corresponding cross-sectional views of FIGS. 19F, 19B and 19G, respectively, or with the isolated die pad 517 as depicted along the lateral tangent line L-L' and the longitudinal tangent lines D-D 'and N-N', respectively, as depicted in the same reference figures previously.
Fig. 22C illustrates a bottom view of various single chip pads USMP with exposed chip pads. An 8-foot package may be implemented as shown including exposed die pad 526 as described by corresponding cross-sectional views along lateral tangent lines K-K ' and longitudinal tangent lines B-B ' and M-M ' with feet 522A through 522H, respectively, as previously described with respect to FIGS. 19F, 19B and 19G, or similar 12-foot packages including exposed die pad 536 with feet 532A through 532L. Or in an 18-foot package includes exposing the chip pad 546 with feet 542A through 542R. In the latter case, the chip pad is scaled up in accordance with the length of the package, and more than one connecting bar, such as connecting bars 544A and 544B, may be used.
Fig. 22D illustrates a bottom view of various single chip pads USMP with isolated chip pads. The 8-foot package may be implemented as depicted by the corresponding cross-sectional views of fig. 19F, 19B and 19G, including isolation die pad 557 along lateral tangent line L-L ' and longitudinal tangent lines D-D ' and N-N ', respectively, with feet 552A through 552H, or similar 12-foot package including isolation die pad 567 with feet 562A through 562L, or 18-foot package including isolation die pad 577 with feet 572A through 572R. As previously described, more than one connecting bar may be used to stabilize a wide chip pad, such as connecting bars 574A and 574B.
In the USMP technology according to the present disclosure, the width range of the package can be simply manufactured by changing the lead frame design using a generally used manufacturing process. For example, a 16-foot double sided USMP may be used to implement innumerable permutations such as single or double exposure, isolation, or hybrid chip pads and pinouts of different sizes. Fig. 23A illustrates a bottom view of a 16-foot USMP with single and dual exposed chip pads. The single chip pad is shown in the left view, including exposing the chip pad 606 with feet 602A through 602P. Along the transverse tangent K-K' as described by the corresponding cross-sectional view previously shown in fig. 19F. The foot is not connected to the chip pad. The longitudinal structure is shown as intersecting only the exposed diepad 606 and plastic 601 along the tangent line B-B 'through the connecting bars 604A and 604B and along the tangent line M-M', consistent with the corresponding cross-sectional views previously shown in fig. 19B and 19G, respectively.
The right side of fig. 23A shows that the dual-chip-pad version includes two chip-pads, namely, with the chip-pad 616A held in a fixed position by the connecting bar 614A and the chip-pad 616B held in a fixed position by the connecting bar 614B. The longitudinal structure is consistent with the corresponding cross-sectional view previously shown in fig. 19H along the tangent line P-P 'through the connecting bars 614A and 614B and along the tangent line Q-Q' only transecting the exposed die pad 616 and the plastic 611. While the exposed die pad may be mechanically supported from below during wire bonding, neither of the center extremities of die pads 616A and 616B are connected by a connecting bar and are easily moved during manufacture, particularly during molding. To prevent this problem, the chip pad may be connected to either foot by a vertical post or by a cantilever. Various combinations of chip pad connections to the footings are shown in subsequent figures. For example, the left side view in fig. 23B shows a dual chip pad package with exposed chip pad 626A held in a fixed position by connecting bar 624 and chip pad connection to pin 622F. The exposed die pad 626B is held in a fixed position by the connecting bar 624B and the die pad connection to the feet 622B,622c and 622D, also serving as an electrical and thermal conduction path.
When the pins are connected to the chip pads, the maximum number of electrical connections for one package is reduced. For example, while the dual chip pad design shown in fig. 23A has 16 different feet, it provides 18 electrical connections because the chip pads 616A and 616B may be electrically connected to under the chip pads by a PCB. In contrast, while the left-hand view of fig. 23B also has 16 different feet, it provides only 14 different electrical connections, as feet 622B, 622C, 622D and 622F are short circuits to the electrical properties of the chip pad.
In the right-hand view of fig. 23B, the four feet have been combined into one long foot 632Z, while the chip pad connections to the feet 632A-632D remain separate. The resulting package incorporates two low thermal resistance chip pads 636A and 636B into 13 different feet including only 10 individual electrical connections. Due to the ultra-wide foot 632Z, after wave soldering the exposed die pad 636A is able to carry higher current and slightly more thermal energy than the exposed die pad 636B.
The connection of the die pad to the foot may also be accomplished using USMP to make a multi-pin package with isolated die pads, except that special care must be taken in the leadframe design to ensure stability during wire bonding and molding. An example of a USMP with dual isolated chip pads 16-feet is shown in bottom view in fig. 23C. The illustrated isolated die pad 647A on the left side is stabilized by connecting bars 644A and 644B and die pad connections to feet 642e,642f and 642G. As depicted along the transverse tangent C-C' or by the cross-sectional view of fig. 19A. The foot is connected to a chip pad 647A with corresponding cantilever segments 642e,642f and 642G. Likewise, cantilever segment 649M connects foot 642M to isolation chip pad 647B, along with connecting bars 644C and 644D, stabilizing isolation chip pad 647B. The resulting USMP has 16 different feet supporting up to 14 different electrical connections.
As illustrated on the right side of fig. 23C, the isolated die pad 657B may be supported with opposing feet as depicted along a transverse tangent F-F' for increased stability and illustrated by its corresponding cross-sectional view of fig. 19C, wherein the foot 652D and the connecting cantilever 659D, the foot 652M and the connecting cantilever 659M, and the connecting bar 654B together form a triangle. The same concept is used to isolate the die pad 657A including the die pad connected to the wide foot 652Z, to which the opposing foot 652L is connected by the cantilever segment 659L, together with the connecting bar 654A to stabilize the isolated die pad 657A. Wide feet 652Z and 652Y are designed to accommodate a vertically integrated power device, such as a power MOSFET, wherein feet 652Z and 652L together conduct drain current and heat from the back side of the die, while foot 652Y supports a plurality of bond wires required to bond to the top high current source of the die.
The concepts described above for isolating and exposing the chip pads may be combined with a dual chip pad package, such as those shown in the bottom view of the 16-foot USMP in fig. 23D. In the left side view, the exposed chip pad 666 is connected to the foot 662L with the vertical post 669L and via the connecting bar 664A. The foot 662D with the connecting cantilever 669D, the opposing foot 662M with the connecting cantilever 669M, and the connecting bar 664B together form a triangle to support the isolated chip pad 667. The USMP includes 16 different feet supporting 15 different electrical connections.
In the right-hand view of fig. 23D, exposed die pad 676 extends beyond plastic 671 to form wide foot 672Z. Increasing the maximum die size allows lower resistance devices to be packaged by combining the wide foot 672Z with the die pad 676 and eliminating the void space required for the plastic 671 within the die pad. The wide foot 672Y is positioned on the opposite side of the package to facilitate connection of multiple bond wires using high current.
Another consideration is the minimum allowable gap between exposed die pads on the PCB. Some printed circuit board manufacturers limit the minimum allowable space between PCB landing pads, particularly for chip pad attach elements that are not suitable for optical inspection. This problem can be particularly problematic for dual chip pad packages. One solution is to give a sufficient distance to the dual chip pad where the chip attach is located that is highly unlikely to cause an electrical short and does not limit the maximum usable chip size of the chip. As shown in the left-hand view of fig. 24A, the space between the exposed die pads 686A and 686B may be increased by the separate exposed die pads and the space where the cantilever extensions 689A and 689B are not used.
The distance as identified along the longitudinal tangents W1-W1 'and W2-W2' is increased in this manner without sacrificing the maximum chip size. The structure of the longitudinal tangents W1-W1 'and W2-W2' is shown in the cross-sectional view of FIG. 24C. Wherein the exposed die pad 686A is tightly coupled to the cantilever extension 689A across a portion of the intermediate space between it and the other exposed die pad. The cantilever-like extension 689B spans a portion of the intermediate space between the exposed die pad 686B and the exposed die pad 686A. The result of these changes increases the width of the plastic 681 and reduces the risk of PCB shorting.
As shown in the right side view of fig. 24A, the space between the feet 692E to 692P and the die pad 696 may also be increased in the same manner by surrounding the three sides of the exposed die pad 696A, by the cantilever extension 699A in the longitudinal direction, and by the cantilever extension 699C in the transverse direction. The space between the exposed die pad 696B and its adjacent feet, i.e., feet 692A to 692D and 692M to 692P, may be increased in the same manner by surrounding the exposed die pad 696B, by the cantilever extension 699B in the longitudinal direction, and by the cantilever extension 699D in the transverse direction, as depicted along the transverse tangent line X1-X1'. The cross-sectional view in fig. 24E shows the structure of the transverse tangent X1-X1' where the cantilever extension 719C increases the width of the plastic 711 and reduces the risk of PCB shorting.
The left side view of fig. 24B shows that the cantilever extension may be asymmetric, wherein the cantilever extension 709A connected to the exposed die pad 706A is a cantilever extension 709B having a shorter length than the cantilever extension connected to the exposed die pad 706B. To support its greater length, cantilever extension 709B is connected to cantilever bridge 709C with foot 702M. The configuration of tangents W1-W1' and W2-W2' in FIG. 24B is depicted in the cross-sectional view of FIG. 24C, except for the lengths of the cantilever extensions 709A and 709B, which refer to corresponding cantilever extensions 689A and 689B by way of the cross-section of tangents W2-W2' in FIG. 24C. Are not adjusted to different lengths.
In an alternative embodiment, shown in the right hand view of fig. 24B, reinforcing cantilever extensions 719A and 719C surround three sides of exposed die pad 716A. The exposed die pad 716B is surrounded by cantilever extension 719B as shown in the cross-section of fig. 24E along transverse tangent X2-X2' and in longitudinal tangents W3-W3' and W4-W4' of fig. 24D. The distance from the exposed chip pad 716B to the nearest conductor, or to the bottom pins 712J and 712G or to the other exposed chip pad 716A, is greatly increased and the width of the plastic 711 is significantly widened in both figures.
In alternative embodiments, only one chip pad is reduced in size and the other remains unchanged. An example of this approach is shown at 24F, where the exposed die pad 686A remains unchanged in section W2-W2' while the exposed die pad 686B is reduced in size and is connected at the edges to the cantilever extension 698B to increase the width of the plastic 681. The exposed die pad 716A remains unchanged in section W4-W4' while the exposed die pad 716B is reduced in size and surrounded by the cantilever extension 719B to increase the width of the plastic 711.
The dual package manufactured by USMP may also include the use of cantilever extensions while referring to cantilever interconnects, cantilevers or cantilever beam interconnects herein to enhance wire bonding and package-to-chip interconnects. The cantilever beams are interconnected to improve access to difficult-to-reach portions of the IC, bypass the limitation of bond angle, reduce bond wire length, and reduce stray inductance and parasitic resistance. Examples of cantilever beam interconnections are shown in fig. 25A in various combinations of 16-foot USMP integrated exposed and isolated chip pads with isolated cantilever extensions.
In the left hand view, cantilevered extensions 759A, 759H, 759I, and 759P surround the die pad 756, enlarging the locations where wire bonds are available in order to improve the angle of the bond. In this way, wire bonding from all four sides of the semiconductor chip can be achieved in a dual sided package, which is advantageous for a dual sided packaged product, which may have been previously only four sided. To support stable wire bonding and prevent misalignment of the isolated cantilever beam during manufacture, the beam is secured at least two points in the package. For example, cantilever beam 759A is supported by and connected to foot 752A at its other end by connecting bar 754A on one side. The bond from the foot 752A directly to the semiconductor die bond pad has not previously been possible, and thus the bond from the cantilever beam 754A can be wire bonded to a bottom edge located adjacent the die pad 756.
Likewise, cantilever beam 759H is supported by connecting bar 754B on one side and by foot 752H on the other side, cantilever beam 759I is supported between connecting bar 754C and foot 752I, and cantilever beam 759P is supported between connecting bar 754D and foot 752P. The tangents V-V ' identify the structure in the width direction of the package, while tangents Z1-Z1' and Y1-Y1 ' identify the cross-section of the longitudinal structure and cross-section the connecting bars, including the cantilever beam extension 759H, the exposed die pad 756, and the cantilever beam extension 759A as depicted in FIG. 24G. At the tangent lines Z1-Z1', the cross section of the cantilever beam extension 759I from the connecting bar 754C is indistinguishable, as is the cross section of a similar cantilever beam extension 759P from the connecting bar 754D. The cross section of tangent line V-V' shown in FIG. 19K illustrates the transverse cross section of the dual cantilever beam structure, wherein cantilever extension 353L is connected to foot 352A by vertical column 354A and cantilever extension 353M is connected to foot 352B by vertical column 354B.
In the right side view of fig. 25A, isolation cantilever extension 769B is supported between feet 762H and 762I and further supported by connecting bar 764B to facilitate bonding wires into any semiconductor die (not shown) by being adhered to exposed die pad 766. The cross-sectional structure of the tangent line F-F' is depicted in FIG. 19C, although the identification element numbers are different. To facilitate improved heat transfer and to maximize chip size, chip pad 766 is incorporated into feet 762Y and 762Z. The isolated chip pad 767 is supported in two parts-connected to the foot 762N by a cantilever bridge 769A and to the foot 762N by a connecting bar 764A. The longitudinal cross-section identification of the package and leadframe is depicted in the cross-section of fig. 24H by the cuts Y2-Y2 'and Z2-Z2', including cantilever extension 769B, exposed die pad 766, and isolated die pad 767. At the tangent line Z2-Z2', the cross section of the cantilever extension 769B from the connecting bar 764B is indistinguishable, while the cross section of the isolated chip pad 767 from the connecting bar 764A is indistinguishable.
A possible wide range of lead frames may be achieved with isolated cantilever extensions. For example, the bottom view of fig. 25B includes two alternative embodiments of a 16-foot USMP integrated dual-exposure chip pad with isolated interconnects. The left illustration includes two die pads, namely an exposed die pad 776 and an isolated die pad 777, and an intervening isolated cantilever 779D supported between feet 772D and 772M, identified along tangent line F-F' as depicted in fig. 19C. The longitudinal cross-section of the package and leadframe identified by the cuts Y3-Y3 'and Z3-Z3' is depicted in the cross-section of FIG. 24I.
Two die pads are included in the right illustration of fig. 25B, namely an exposed die pad 786 and an isolated die pad 787, with an isolated cantilever 789H suspended between a foot 782H at the top of the package and a connecting bar 784B. The cross-sectional view of the isolation cantilever 789H is depicted by cut line C-C' shown in FIG. 19A. The longitudinal section of the package and leadframe identified by the cuts Y4-Y4 'and Z4-Z4' is depicted in the cross-sectional view of FIG. 24J.
Although the application of the embodiment and isolated cantilever extension shown in the 16-foot USMP design is shown, the concepts and methods can be extended to USMPs with almost any more than three feet, and thus the number of electrical connections is not limited to that shown in this embodiment.
Examples of quad USMP foot packages the subsequent illustrations depict quad variants, i.e., quad package structures that can be manufactured with USMP processing and methods. A quad-pod is a package in which pins or feet are present on three or four sides of the package. The quad-pod may be square or rectangular. The figure generally includes a perspective view and two bottom views of the package-a version using exposed die pads, and another version of isolated die pads that include the same package. In most cases, the perspective view is the same for the version of the exposed and isolated chip pad.
The tangent to the relevant section from the previous section is identified on the bottom view to explicitly identify the structure of each package. Furthermore, any quad-pod package using the USMP process can be converted to quad-no-lead package, i.e., QFN equivalent base area without feet extending beyond the edges of the plastic body, simply by adjusting the laser cut for metal removal to the same area and edge for determining plastic removal. For simplicity, the USMP leadless version of the quad-pod below will be excluded from the figures.
Fig. 26A shows a perspective view of a 16-foot quad USMP package 900 including plastic 911, connecting bars 914A through 914C, and feet 912A through 912H. Since package 900 is symmetrical, it is understood that like tie-bars and like feet are located on opposite sides, both sides of package 900 are not visible. In summary, the package feet shown in the square version are distributed four on one side. The connecting bar is positioned at a corner. Package 900 may be fabricated with isolated or exposed die pads. FIG. 26B shows a bottom view of 16-foot USMP package 900 with exposed die pad 917, where the cross-sectional structure is shown by tangent line K-K, either longitudinally or laterally, as shown in FIG. 19F. In contrast, FIG. 26C shows a bottom view of a 16-foot USMP with isolated die pad 917, wherein the cross-sectional structure is shown either in the longitudinal or transverse tangents L-L', as shown in FIG. 19F.
Fig. 27A includes various bottom views of 4 and 6 foot quad USMP and exposed die pad. The plastic 921 is shown in the upper left corner to include an exposed die pad 926, a connecting bar 924, and four feet 922, one on each side. In its smallest dimension, a quad-pod with 4 feet is not an active area and is preferably implemented as a dual sided package as previously shown. The utility of the four foot USMP design improves with 6 feet. In the upper right corner, for example, the exposed die pad 936 is substantially larger than the die pad 926 previously described. The resulting package comprises a rectangular shaped plastic 931 with 6 feet 932, two at each end of the package and two at each longitudinal edge. The size of the chip pad can be increased by connecting 2 feet 948 to the chip pad 946, as shown in the lower left-hand view of fig. 27A along line A-A'. Or alternatively by connecting the 4 feet 958A and 958A to the chip pad 956 as shown in the lower right drawing along the line E-E'.
Extending the foot four-sided USMP design to increase foot count is a simple method by which 8-and 10-foot four-sided USMPs with exposed and isolated chip pads are shown in fig. 27B by a bottom view. The upper left corner is shown as 8 feet USMP, a square four-sided foot USMP comprising plastic 961, exposed chip pads 966, corner connecting bars 964, and two feet 962 on each side, with a cross section depicted along tangent line K-K'. The bottom left hand drawing of the same figure shows a version of an isolated chip pad, a square four-sided foot USMP comprising plastic 961, isolated chip pad 967, corner connecting bars 964 and two feet 962 on each side, with a cross section depicted along tangent line L-L'.
Extending the USMP design to a rectangular 10 foot package as also shown in fig. 27B, the upper right corner USMP includes plastic 971, exposed die pad 976, corner connecting bars 974 and 3 feet 972 located at the left and right ends and at the top and bottom sides. The package has a cross-section depicted along a tangent line K-K'. The bottom right hand drawing of the same figure shows an isolated chip pad version, a rectangular four sided foot USMP comprising plastic 971, isolated chip pad 977, corner connector bars 974, and foot 972 having a cross section depicted along cut line L-L'.
The thermal performance and maximum chip area of the above-described USMP can be improved using a chip pad attachment foot, as shown in fig. 27C. The method is applicable to both exposing and isolating the chip pad. In the upper left view, one 8-foot quad USMP includes an exposed die pad 986 surrounded by plastic 981 connected to two feet 982B by vertical posts 988 as depicted in cross-section along line A-A'. The remaining feet 982A are not connected to the chip pad. The bottom left diagram in fig. 27C shows that one 8-foot quad USMP includes an isolated chip pad 987 connected to two feet 982B by a cantilever 989 as depicted in cross-section along line C-C'. The remaining feet 982A are not connected to the chip pad.
In the upper right view of fig. 27C, the 8-foot four-sided USMP includes 7 feet 982 that are not connected to the exposed die pad 996 and one wide foot 993 that is connected to the exposed die pad 996. The corners of the exposed die pad 996 on the opposite side not connected to the foot 993 include connecting bars 994. Similarly, the bottom right hand view of fig. 27C shows an 8-foot quad USMP including 7 feet 992 that are not connected to the isolated die pad 997 and one wide foot 993 that is connected to the isolated die pad 997. The corner of the isolated die pad 997 on the opposite side not connected to the foot 993 includes a connecting bar 994.
Fig. 27D includes a bottom view of various 8-foot and 10-foot rectangular quad USMPs plus an exposed and isolated chip pad. The top left view includes plastic 1001, an exposed chip pad 1006 that incorporates four feet 1002B, while the remaining feet 1002A are separated from the exposed chip pad 1006. The longitudinal section is depicted along the symmetry line E-E 'and the transverse section is depicted along the symmetry line K-K'. The resulting USMP has a total of 10 feet, but only seven individual electrical connections. The lower right structure of the package is identical except that the exposed die pad 1006 is replaced with an isolated die pad 1007. Yet another minor variation of the package herein is shown in the upper right hand view of fig. 27D, where the joined 4 feet 1002B are replaced by two wide feet 1003 on the opposite edges of the package, thus creating an 8-foot USMP package with 7 independent electrical connections.
While the three versions of the package defined by plastic 1001 described above are shown in fig. 27D with the locations of the die pad connections to the feet on the narrower edges of the package, the locations of the USMP isolation die pad 1007 shown in the lower left view connected to the three feet 1002B are replaced by longer edges. The resulting USMP includes 10 feet with 8 independent electrical connections.
Fig. 28A includes a bottom view of a 12-foot square quad USMP formed in plastic 1011 plus exposed and isolated chip pads. In both figures, the chip pad is attached at all four corners by connecting bars 1014 and surrounded by individual feet 1012, three on each edge of the package. The left view utilizes the exposed die pad 1016 while the right package uses the isolated die pad 1017.
Fig. 28B includes a bottom view of the 16-foot rectangular quad USMP formed in plastic 1021 plus the exposed and isolated chip pads. In both figures, the chip pad is attached at all four corners by connecting bars 1024 and surrounded by individual feet 1022, five on each long side and three on each short side of the package. An upper view utilizes an exposed chip pad 1026, while the lower package utilizes an isolated chip pad 1027.
Fig. 29A includes a bottom view of a 20-foot rectangular quad USMP formed in plastic 1031 with an exposed die pad 1036 plus twenty individual pins 1032 located at four each of the left and right ends and six each of the top and bottom sides. The bottom view of fig. 29B includes a 20-foot rectangular quad USMP that is identical except that it utilizes isolated die pad 1037.
Fig. 30A includes a bottom view of a 48-foot quad USMP with exposed die pad 1046, including a bottom view of plastic 1041, four connecting bars 1044 at the corners of the package, and 48 feet 1042 at 12 feet per side. The bottom view of fig. 30B includes 48 foot quad USMP which is identical to the previous package except that it utilizes an isolated chip pad 1047. In another embodiment, the same package with isolated die pad 1047 includes four vertical pillars or posts 1049A-1049D to provide additional stability to the leadframe. The standoff distance is sufficient to avoid any accidental risk of shorting the PCB to the isolation chip pad 1047.
Finally, fig. 31 illustrates that any four sided multi-foot USMP package may be integrated with an extended heat pad. As shown in perspective and bottom view, USMP 1050 includes plastic 1051, foot 1052F connected to the chip pad, eleven individual feet 1052A through 1052E and 1052G through 1052L, extended heat pad 1058, and foot 1053 connected to the heat pad. The design combines the ability of a low inductance and high pin count USMP IC package with the heat dissipation ability of a USMP power package to facilitate advanced power IC designs.
Advanced USMP leadframe designs using USMP procedures, designs, and methods disclosed herein, the unique benefits provided by the features of the leadframe are not possible with conventional packages.
One of the unique benefits of this is the selective removal of the connecting rods. For example, the laser metal removal process shown in fig. 12H is one example of selectively removing the connecting rod. In the example shown, cutting the pins along a straight line inevitably leaves unwanted connecting bars, whereas connecting bars 148 cannot be selectively removed by mechanical means, such as cutting, shearing or dicing, without risking damage to the molded plastic and adjacent pins. Using USMP laser street fabrication, the unwanted protruding metal can be safely removed by laser, even between closely spaced adjacent feet or pins. Because the tie-bars are removed by optical machining, no space is required to clamp or hold the package pins in place.
Another example of selective bar removal is shown in power packages such as DPAK or D2 PAK. For example, in fig. 3E, the center pin of the DPAK 31Q is mechanically clamped and then fabricated, i.e., the center pin functions as a connecting bar only and is not required by the customer for electrical connection. Because it is mechanically clamped, the connecting bar pin inevitably protrudes from the plastic body of the package. The length of the protrusion is determined by the clearance required to mechanically grip the connector pin without damaging the packaging plastic. The bar pin protrusions are electrically connected to the packaged die pad, undesirably increasing the risk of electrical shorting between the bar pin and an adjacent pin.
Furthermore, in power devices, the chip pad and package pins often need to maintain a high voltage between them, typically supporting 600V and in some cases up to 1000 volts. Even a partial solder bridge between the electrodes can lead to electrical leakage currents, circuit failures, and even dangerous failures. In contrast to conventional manufacturing of DPAK, using the USMP process, fig. 21D shows that the connecting bar 444B can be cut off exactly flush with the package body, i.e. plastic 441, without any risk of mechanical damage to the plastic or foot bends 442A and 442B.
The benefits of selective bar removal may be extended to multi-pin packages to enable unprecedented possibilities for lead frame design and features. For example, fig. 32A shows a foot IC package manufactured according to the USMP process, wherein connecting bar 1104A is positioned between two feet 1102A and 1102B. Likewise, connecting bar 1104A is positioned between two adjacent feet. The chip pad and foot 1102E are connected together and connecting bars 1104A and 1104B maintain the exposed chip pad 1106 in a fixed position during the manufacturing process. The mechanical support during the fabrication of the package is shown in fig. 32B by the lead frame. The exposed bond bar 1114A is attached to the leadframe main frame 1119, while the bond bar 1114B and the foot 1112E extend to connect with the metal cross frame 1118, which together hold the exposed die pad 1106 in a fixed position, particularly during wire bonding and molding processes.
The lateral extent of the plastic 1101 is defined after the plastic is removed, and the package is then cut from the leadframe, i.e., singulated. The package may be temporarily held in a fixed position by an adhesive tape, commonly referred to as a "blue tape", until the cut is completed. The risk of distortion of the package by mechanical cutting or die cutting during singulation is completely eliminated by using USMP laser metal removal. As a result, the sequence of cutting off the foot or "desmear", i.e., removal of the tie bar during USMP, is not important. In a dual channel USMP process, cutting the foot first and then removing the protruding tie-bars or vice versa, cutting the tie-bars and then cutting the foot, that order will provide the same result. Alternatively, both the foot and the connecting bar may use a single channel laser process, where the laser cuts off the foot, then removes the connecting bar, and then sequentially removes more feet based on anywhere that laser scan arrives first.
An example of a USMP dual channel laser metal footing and bar severing method is shown in fig. 32C, where a horizontal laser scan 1121X cuts and removes the metal leadframe connection across the street to the package edge 1120X (i.e., the end of the footing) and a lateral laser scan 1121Y cuts and removes the metal leadframe connection in a vertical direction across the street to the package edge defined by dashed line 1120Y. The resulting package at this stage in the USMP process is shown in fig. 32D, where connecting bars 1114A and 1114B protrude from plastic rim 1101 by the same length, such as feet 1102A and 1102B. The second metal removal laser pass is shown in fig. 32E, with the laser scanned again in the horizontal direction by horizontal scan 1123X to selectively remove protruding link 1124B, and again scanned vertically by vertical scan 1123Y to selectively remove protruding link 1124A. Laser spot 1120 may be adjusted by focal length and power to cut off a smaller spot than was used when previously shown to clear the street by laser scans 1121X and 1121Y during the double scan.
The resulting package 1100 is shown in fig. 32A as being accommodated by the use of inter-foot connecting bars, i.e., inner-foot connecting bars, which are capable of stabilizing the packaged chip pad without compromising the foot by connecting it to the chip pad only for the purpose of providing mechanical support during manufacture. For example, in the left side view of fig. 33A, the isolated die pad 1147A is stabilized not only by the die pad connecting wide foot 1142C and the conventional connecting bar 1144A, but also by the inner pin connecting bar 1144D. If the inner lead connecting bar 1144D is not used, the corners of the isolated die pad 1147A will be unstable, exhibiting diving board effect during wire bonding and possible misalignment, i.e. unnecessary movement and repositioning. In a similar manner, the isolated die pad 1147B is held in a fixed position by three supports, namely, by the die pad connection to the foot 1142D, the conventional connecting bar 1144B, and by the inner pin connecting bar 1144C.
In the right-hand view of fig. 33A, isolated die pad 1157A is stabilized by wide foot 1152C of the die pad connection, conventional connecting bar 1154A at the end of the dual, no-foot package, and by inner pin connecting bar 1154D at the foot side of the package. The isolated die pad 1157B is supported by a conventional connecting bar 1154B and by two inner pin connecting bars 1154C and 1154E on opposite sides to form a stable triangular base.
The inner pin connection bars also allow advanced interconnections to be contained within a USMP-implemented package. For example, in the lower left view of fig. 33B, a 10-foot USMP includes two die pads-one exposed and the other isolated, with one isolated inter-package interconnect. Such interconnections are valuable when customer PCB designs require that a particular pinout package cannot be bonded by wire bonds. As shown, the exposed die pad 1166 is stabilized by the conventional connecting bar 1164B and the inner-pin connecting bar 1164C while the isolated die pad 1167 is stabilized by the triangular support including the conventional connecting bar 1164A and the inner- pin connecting bars 1164D and 1164E. Isolated intra-package interconnects 1164G connect the feet 1162H on one side of the package to the feet 1162E on the opposite side of the package diagonal opposite the corners of the near-exposed chip pads 1166.
The inner pin connecting bar is also suitable for four-side USMP. For example, the upper right hand four-sided foot USMP of fig. 33B includes an isolated die pad 1176 stabilized by a conventional corner connection bar 1174C and by an inner pin connection bar 1174D, while the isolated die pad 1177 is stabilized in four positions, namely with corner connection bars 1174A and 1174F and 1174B and 1174E with inner pin connection bars. As previously mentioned, even though the corner connector bars use mechanical methods to remove the plastic body as used in LQFP packages are difficult, waste space and risk damaging the plastic body of the package.
Using this USMP process, the lead frame geometry and packaging characteristics can be flexibly determined in two different ways, namely
The geometric feature may be created as part of the leadframe manufacturing process;
the geometric feature may be created by a post-laser, i.e., patterning by a laser before or during singulation after molding;
an example of such a geometric leadframe feature is a thermal comb as shown in fig. 34A, wherein DPAK and D2PAK packages include plastic 1201, feet 1202A, 1202B and 1202C, connecting bars 1204A, cantilever extensions 1209A and 1209C, and exposed die pad 1206. The exposed die pad 1206 incorporates a heat sink pad 1208A with a thermal comb including metal fingers 1208B, 1208C, 1208D, and 1208E. The finger is constructed as shown using the full leadframe thickness, i.e., vertical column 100A, shown initially in fig. 9A. The inner periphery of the finger includes a wide serpentine foot 1203 for solder wetting thereon. With its large circumference, the comb structure maximizes the electrical and thermal conduction between the package and the PCB, enhancing thermal conduction. The exposed solid metal portion of the heat sink pad, heat sink pad 1208A, maximizes the convection of heat into the air. By adjusting the relative areas dedicated to the solid heat sink pad 1208A and the heat comb, the amount of cooling by heat conduction to the PCB and heat convection to the air can be adjusted by design.
Fig. 34B shows an example of a thermally combed pre-fabricated lead frame. As shown, the heat comb finger 1218 and its associated serpentine leg 1213 are extended beyond the package edge to cross frame 1229Y, as is the extension of leg 1212. The connecting bars 1214 are connected to the frames 1229X and 1229W at the vertical package edges. The package edge is longitudinally defined by laser cut lines 1220Y defining the length of the package foot 1212 and the heat comb fingers, and transversely cut the slag of the connecting bars 1214 with plastic 1201 by cut lines 1220X. As shown in fig. 34C, a plurality of vertical laser scans 1221Y are used between scribe lines 1220Y to remove lead frame connections to the package feet and heat comb fingers. Likewise, a plurality of horizontal laser scans 1221X are performed between cut lines 1220X to remove tie bars.
In another embodiment of a DPAK or D2PAK package with a thermal comb, shown in fig. 35A, the leadframe is modified, wherein the thermal comb 1228B is connected to the heat spreader 1228A comprising a thin metal, i.e., comprising the same thickness of metal as the feet 1212. This version is advantageous for easier wave soldering but includes less thermal mass than previous versions. More importantly, by using thin "footing" metal thermal combs, the comb-like features can be fabricated using laser light after encapsulation molding. The leadframe prior to singulation is shown in fig. 35B, which shows the thin metal feet 1228B extended. Prior to singulation, the holes may be cut with a laser to form a thermal comb as shown in fig. 35C, wherein horizontal scan 1226 removes multiple areas 1225 within thin metal extended footing 1228B. The size of the opening may be determined by the number of scans and the size 1227 of the laser spot using the focal length control.
In an alternative embodiment shown in fig. 36A, the thin metal footing 1228B uses a laser to open a pattern of bolt holes 1225, similar to the method of forming a thermal comb, and the manufacturing process involves multiple overlapping horizontal scans 1226 to remove circular areas 1225 within the thin metal extension footing 1228B as shown in fig. 36B.
Advanced USMP leadframe processes as previously described, the USMP leadframe must be electroplated to improve solderability and inhibit copper oxidation. In the USMP process, electroplating can be performed at several different times and by several different methods, i.e
In the manufacturing process of the lead frame before package manufacturing, by "pre-plating" the entire surface of the lead frame;
during the manufacture of the leadframe prior to package manufacture, a portion of the leadframe is selectively plated on its surface by "preplating", sometimes referred to as "patterned leadframe plating";
after molding but before the metal pattern and cut into individual pieces;
the sequence of the various manufacturing processes is shown in the flow chart of fig. 37. In the first case, the entire leadframe is preplated and the USMP process sequence includes leadframe formation (step 1250A), leadframe preplating (step 1250B), molding (step 1250C), laser plastic removal (step 1250D), and metal patterning and singulation (step 1250E). In the second case, the patterned lead frame plating (step 1252B) replaces step 1250B. In a third process option, lead frame preplating (step 1250B) is skipped, indicated by dashed line 1251A, and lead frame formation (step 1250A) is followed by molding (step 1250) and then plastic removal (step 1250D). After the plastic is removed from the street, the leadframe is then plated, referred to as "post-de-deslagging leadframe plating" (step 1251B), followed by metal patterning and dicing into individual 1250E. The term "deslagging" refers to the removal of plastic chips resulting from cutting or die cutting but removal with laser plastic is not an issue.
Fig. 38 shows an example of a pre-plated lead frame in which all sides of copper die pad 1261 are covered by plated metal 1269 and the feet 1262 and cantilevers 1263 and the vertical columns connecting them are covered by the same plated metal 1269. However, pre-plated lead frames are generally good for small packages, but for large and high pin count packages and power packages, the packages may suffer from poor adhesion and delamination between the plastic and the plated metal. For example, plastic 1260A may delaminate in areas 1265A and 1265B. Surface 1265C may also delaminate from bottom surface plastic 1260B. Delamination in any area may lead to reliability failures.
By using selective plating, delamination may be avoided by preventing plating on sensitive areas of the leadframe where the risk of delamination is high. As shown in the cross-sectional view of fig. 39, regions 1269A, 1269B, and 1269C are areas where selective plating of metal 1270 is precluded because plating is intentionally inhibited in these areas. Three methods may be used for selective electroplating. In one case, a base layer, such as titanium, platinum, palladium, nickel, or various refractory metals, is deposited on the area to be electroplated. A variety of methods may be employed to create the selective seed layer.
The base layer may be locally deposited through an intervening template mask so that it only occurs where electroplating is intended to occur. The method is used to form a patterned base layer, a process referred to herein as "patterned deposition";
the leadframe is covered or uniformly deposited with the base layer metal and then selectively covered with photoresist through a patterned stencil mask exposing only those areas where the base layer should be removed. After baking the photoresist until it hardens, the underlying layer is then etched to attack the particular metal with an acid, but not to etch or only slowly etch the copper, thereby removing the exposed underlying metal. The photoresist is removed and the leadframe after cleaning is ready for electroplating. The method for forming the patterned base layer is referred to herein as a "mask back-etch" process;
the leadframe is covered with photoresist by a patterned stencil mask and deposited only on those areas of the base layer from which the photoresist is removed. The result is a patterned leadframe with areas open to copper and other layers covered by photoresist. After baking, the metal of the base layer is deposited on the patterned lead frame, some of the metal is deposited directly onto the copper, and the metal in other areas is deposited on the photoresist. The photoresist "strip" and base metal removed therefrom remains on the copper lead frame where the base metal only occurs where plating should occur. The method used to form the patterned base layer is referred to herein as a "lift-off" process;
The base layer may be printed onto a lead frame with a printer, the base metal dispensed in a solvent suspension that is dry, and the solvent completely evaporated during printing by a lamp, laser or heat block and then baked. After baking, the leadframe is heated to a higher temperature to bond the base metal to the copper leadframe. The base layer is only left in this printed area. The process used to form the patterned base layer is referred to herein as a "metal printing" process;
after forming the patterned base layer, the leadframe is ready to be selectively plated. The plating chemistry must be adjusted so that plating does not occur on bare copper without a base layer.
In the second method, plating is performed anywhere and selectively removed by masking and etching. In a third method shown in fig. 40, plating resist layers 1271A and 1271B, i.e., a material that prevents plating, such as glass or organic compounds, are screen printed or printed onto lead frame 1261 prior to plating. The inhibitor layers 1271A and 1271B will be chemically removed after plating of the plated metal 1273A.
In addition to lead frame plating, another valuable function of the USMP design involves soldering the power package or exposing the die pad to the PCB. Since wave soldering spreads solder on a surface only from above the component, there is no way to obtain solder under a large metal area using wave soldering processes. Conversely, as previously described, reflow soldered PCBs are expensive relative to wave soldering. The foot package itself does not solve this problem and on the same technology it is necessary to rely on the use of today's DPAK assemblies, i.e. to perform a two-channel PCB assembly with one channel for attaching power components or exposing the chip pad package and another channel for wave soldering pins to the circuit board.
The first pass of the dual pass PCB assembly is shown in fig. 41A, where the PCB 1300 and copper paths 1301A, 1301B and 1301C in the top view are covered with conductive epoxy or solder paste, such as a solder paste layer 1302A over copper path 1301A and a solder paste layer 1302B over copper path 1301B. Copper path 1301C is not used for power components and is therefore skipped without coverage as is most PCB paths. The exposed chip pad package is then positioned over the epoxy or solder paste as shown in the middle view. Thus, the exposed die pad 1305A is located above the solder paste layer 1302A and the foot 1305B is located above the solder paste layer 1302B. After being heated by the oven, the solder paste melts and exposes the die pad 1305A to sink into the solder paste layer 1302A. Likewise, feet 1305B sink into solder paste layer 1302B which melts into molten solder. After the solder solidifies, electrical and thermal connection to the copper conductors of the PCB is made as shown in the bottom view. In addition, if a conductive epoxy is used instead of solder paste, the package is mechanically pushed down into the epoxy and the epoxy is left to cure. The fast setting epoxy resin may cure in 30 minutes to one hour.
After the solder or epoxy attachment process, additional solder flows over the feet during wave soldering. Since wave soldering achieves high quality electrical connection between the copper paths and the feet of the PCB, the primary purpose and benefit of the solder paste or epoxy is to promote improved heat conduction to the PCB, rather than being the primary path for electrical conduction. To minimize thermal resistance, the final thickness of the epoxy or solder layers 1302A and 1302B should be as thin as possible. If it is deposited too thick, excess solder paste or epoxy may overflow the bottom "squeegeeing" side of the package and may cause a short circuit to the PCB. Such problems are particularly problematic for dual exposure chip pad packages. A minimum distance of 1 mm to 1.5 mm or more may be desirable.
If the epoxy or solder paste layer is sufficiently thin, the solder paste layer 1302B under the package foot 1305B may be eliminated because the electrical connection between the foot 1305 and the copper path 1301B is achieved using a subsequent wave soldering process. However, if the solder paste layer applied under the exposed die pad 1305A is too thick, then, as shown in the upper diagram of fig. 41B, during heating, the feet 1305B may be separated from the copper paths 1301B by gaps 1307, and the package may be tilted such that the package and the exposed die pad 1305A are no longer parallel to the PCB 1300. As a result, solder paste layer 1302A melts into non-uniform wedge-type solder 1302Z, making wave soldering of the feet 1305B to the copper paths 1301B difficult. Furthermore, foot 1305B may contact copper path 1301B only at one point 1308, making uniform solder joints difficult to reproduce consistently.
One solution, as shown in the modified USMP manufacturing flow diagram of fig. 42A, is to insert an additional "solder print" step (step 1250G) into the workflow between the plastic removal (step 1250D) and the metal patterning and singulation (step 1250E). The presence of this additional step complicates the procedure and it completely eliminates the need for a dual channel PCB assembly. With this modified process, any USMP package with exposed chip pads may have an optional thin solder coating on its feet and the bottom edges of the exposed chip pads. As shown in the upper cross-sectional view of fig. 42B, the power package with the chip pad 1315A is covered with a thin solder layer 1319A, including a thin solder layer 1319C under the chip pad connection foot 1315C and a thin solder layer 1319B under the foot 1315B. Also, as shown in the lower cross-section, in any USMP IC package with a die pad, whether double sided or quad sided, the exposed die pad 1325A is covered by a thin solder layer 1329A. Likewise, foot 1325C is covered by thin solder layer 1329C, foot 1325B is covered by thin solder layer 1329B, and other feet (not shown) are also covered by thin solder layer. The solder layer may be deposited or printed.
In the process flow shown in fig. 43A, attaching the power package with die pad 1315A and the USMP foot IC package with die pad 1325A to the PCB may be performed in a single step, such that they are fixed in position to the melted solder paste when in contact with the PCB, resulting in the cross-sectional structure diagram shown in fig. 43B, wherein copper foot 1315B is melted by solder layer 1319B over copper path 1331B of PCB 1330. After heating, non-power packages, such as USMP IC packages and plastic 1334 are attached by adhesive or mechanical fastening. Unlike the footing in the power and exposed chip-pad package, copper footing 1335B sits directly on copper path 1331F of PCB1330, with no intervening solder layer. After wave soldering, the cross-sectional view of PCB1330 is shown in FIG. 43C, with solder layer having covered all of the copper feet, namely solder layer 1340A covering foot 1315C, solder layer 1340B covering foot 1315B, solder layer 1340C covering foot 1325C, solder layer 1340E covering foot 1325B, and solder layer 1340F covering foot 1335B. In this way, all power and non-power packages are manufactured in flow wave soldering without the need to cover and even assemble the power element with solder paste.
The left side diagram in fig. 44A shows a bottom view of the solder plating DPAK. Solder paste is printed, covering exposed die pad 1403 and die pad attachment foot 1402C with solder paste layer 1404C, covering foot 1402A with solder paste layer 1404A, and covering foot 1402B with solder paste layer 1404B. The solder paste becomes solder at the same location after heating.
In the right-hand side of fig. 44A, an embodiment of a modified solder plated USMP package is shown, with holes 1406 included in solder paste layer 1405C and solder paste layers 1405A and 1405B being made in a doughnut-like shape, such that some areas are free of solder, even after the solder paste melts into solder. The purpose of the absence of solder for the holes is to facilitate testing the probe contact package locations during the manufacturing process without causing solder to adhere to the probe tips.
The method is equally applicable to USMP IC packages. As shown in fig. 44B, the package on the left utilizes a uniform solder paste layer 1414A on the exposed die pad 1413 and a uniform solder paste layer 1414C on the package foot 1412, whereas the package on the right utilizes a doughnut-like shaped solder paste layer 1415A on the package foot 1412 and holes 1416 in the solder paste layer 1415C are located on the exposed die pad 1413.
As shown in the cross-sectional view of fig. 44C, during electrical testing, probes 1420 are swung into position in solder layer 1405 in contact with exposed die pad 1403 and footing 1402 through opening 1406 in such a way that the probes do not cause solder scratches and sticking to the probe tips, compromising the ability of the probes to make good electrical contact under device testing.
Another consideration in the design of USMP lead frames is particularly relevant to isolating the die pad. As shown in the cross-sectional view of fig. 45, during the process of adhering semiconductor chip 1459 to the top surface of isolation die pad 1457 to wire bonding to connect via cantilevered segments 1454A and 1454B to feet 1452A and 1452B, custom heater assembly 1460 must be designed to prevent spring plate effects and oscillations during the bonding process. Customization is possible, and another option is to fill the void under the isolated die pad with an electrically insulating and thermally conductive compound, such as polyamide or epoxy filled with diamond powder, carbon nanotubes or ceramic powder. Such processing, like pre-formed lead frames, does not use the same molding compound to form the plastic, but instead uses an optimized material that has good thermal conductivity properties for it.
Fig. 46 shows the resulting leadframe structure, including thermal compound 1465 or 1466, that will permanently adhere to the bottom surface of the leadframe during fabrication and subsequent processing of the end product. In the upper illustration, thermal compound 1465 is coplanar with the upper surfaces of isolated die pad 1457 and cantilever segments 1454A and 1454B. In the lower illustration, thermal compound 1466 is coplanar with the bottom surface of isolated die pad 1457 and fills the gap between the die pad and cantilever segments 1454A and 145B during molding.
The order of manufacture of these two versions is slightly different. In fig. 47, a first case is illustrated in which the top surfaces of the leadframe elements 1454A, 1454B, and 1457 are covered with a temporary adhesive layer 1464, such as blue tape, before the thermal compound 1465 is printed onto the backside of the leadframe. The thermal compound naturally fills the void between the die pad 1457 and the cantilever segments 1454A and 1454B so that it is coplanar with the top surface of the isolated die pad 1457. After printing, the temporary adhesive layer 1464 will be removed.
In the manufacturing sequence of fig. 48, the back surface of the lead frame 1468 is completely etched, forming thinned portions 1467, as shown in the above figures. However, before preforming the front side etch, thermal compound 1466 is printed or overlaid to the cavity created by the back side etch. Next, a front side etch is performed, as described above, resulting in the leadframe shown in the bottom illustration, filling the area under the isolated die pad 1457 with thermal compound 1466. The resulting package provides one benefit of enhanced thermal conduction and lower thermal resistance than conventional isolated chip pad packages. In addition, the thermally conductive compound provides mechanical support during wire bonding while also allowing the planar heater assembly to heat up to the die and leadframe during wire bonding to improve the adhesion of the bond. Thus, a dedicated heater assembly, such as the heater assembly 1460 shown in FIG. 45, is not required.
Practical examples of USMP designs as described above, the USMP procedure can be widely substituted for the use of any leadless package or any pin or gull-wing package with leadless or footing packages, with only a simple change in lead frame design avoiding the need for new or custom molding tools. The flexibility and versatility of the USMP process and design support strategies for arbitrary manufacturing quantities, designs, products and market trends, including:
reduced manufacturing costs and improved factory flexibility and throughput by converting traditional cut and die QFN to USMP process production, enabling the production of multiple packages on a common line, i.e., improved package manufacturing through integration of product lines;
converting reflow PCB assembly to low cost wave soldering by replacing the existing leadless package with USMP foot package, using the existing chip without changing the area or path of the PCB, i.e. reducing the cost of stitch-to-stitch replacement;
maintaining the same PCB platform pad location, designing a new larger chip with better performance, e.g., high current, low resistance, more functions, etc., from the benefits of manufacturing packages with improved USMP area efficiency, i.e., the benefits of upgrading pin-to-pin replacement;
Reducing the PCB area, using existing chip packages in a package made with a larger area efficiency USMP, i.e. a reduced package;
shrinking the PCB area, using custom chip designs to accommodate packaging made at a smaller USMP, i.e., chip and shrink packaging, is compatible with a standard PCB path of a smaller package, e.g., changing from 3 x 3DFN to 2 x 3DFN.
Also, using USMP manufacturing methods, the footprint package may have a smaller PCB footprint than the equivalent area of the gull wing to enclose the chip originally designed for the pin package, i.e., the package size may be reduced, which is typically easier in industry to employ a fixed package footprint for industry standard conventional packages, and then maximize chip size. In contrast, the foot USMP occupies slightly less area efficiency than an etched QFN or DFN leadless package for the same PCB space and PCB land layout, and slightly more area efficiency than a die cut QFN or PCB land layoutDFN leadless packages, but have more significant area efficiency than any equivalent pin, gull-wing, or bent-pin packages. In the case of an LQFP package, the foot USMP version is substantially more efficient. The definition of area efficiency as used herein is the maximum chip area, whichever is larger, that is, the area efficiency η, of a given package divided by the PCB area required for the adhesive element, while being defined by the lateral extension of the plastic or the conductors used for the adhesive element area ＝A max die /A PCB 。
Fig. 49A shows an example in which a cut QFN3 x 3 package leadframe 1500 is converted to its wave solder compatible foot equivalent leadframe 1510, whereby the die pad 1516 replaces the die pad 1506, the leadless platform pad 1502 is replaced with wave solder foot 1512, the corner bar 1514 replaces the corner bar 1504, and the plastic 1501 is replaced with plastic 1511.
The conventional package shown is a cut QFN leadless package because it is cut, rather than mechanically die cut, to cut plastic and metal landing pads to the correct dimensions. As with the leadless package, no metal protrudes beyond the edge of the plastic after dicing, with the conductive landing pad 1502 of the package under the entire plastic body 1501. Each conductive landing pad is 0.4mm long and 0.3mm wide to enable reliable soldering. The landing pad or "stitch" pitch is 0.65mm, the period of the repeating pitch of the spacing or conductive landing pad. The four-sided package with the pin pitch of 3mm by 3mm comprises 13 electrical connections, three on each side. The exposed die pad 1506, held in a fixed position by the connecting bar 1504, can accommodate a maximum die size of 1.65mm by 1.65 mm.
By converting the QFN package to a foot version of the QFN, i.e., QFF, the USMP procedure can be used to eliminate the need for solder reflow according to the PCB assembly. The USMP procedure is used to convert cut QFN with leadframe 1520 to bumped QFN with leadframe 1530, shown in fig. 49B, without changing the position of bumped 1532 needed for PCB routing and soldering and in the same location as conventional QFN landing pads 1522. The feet 1532 must extend beyond the plastic body 1531 by a sufficient distance to ensure a good soldering range, i.e., the "outer pin length" of the package. As described in the corresponding table, a length of 0.125mm is selected as the "outer pin length". To maintain compatibility with conventional QFN assemblies, the foot 1532 includes a 0.4mm long by 0.3mm wide solder area, as with QFN, except that the foot protrudes 0.125mm beyond the edge of the plastic 1531, the other 0.275mm conductive "heel" foot portion, the remainder being under the package.
The foot packages shown in this manner can be assembled onto the PCB using wave soldering or reflow assembly without any change in the copper path of the PCB. The compatibility of both the foot packaging and the wave soldering and reflow assembly is another benefit in that the foot packaging is "universal" in that the only available is to use the USMP designs and methods disclosed herein. No other package like this can replace both the leaded and leadless packages with the same design.
As previously mentioned, the area efficiency of a quad-leaded QFN on a per-area basis is slightly less than a comparable size diced QFN package. Because the bottom area of the standard QFN is sized externally, the space allocated for package feet reduces the available area of the chip pad. Therefore, the area of exposed die pad 1536 must be smaller than QFN die pad 1526. The resulting foot package has a maximum chip size of only 1.4mm by 1.4mm, which is about a 20% reduction in chip area compared to a cut QFN package.
In order to regain the lost area of the solderable feet, a slightly larger package is required. For example, increasing the 3×3 foot USMP size to 3×4 specification increases the maximum chip size to 1.45mm×2.1mm. Although the package is somewhat larger, the resulting foot package is wave soldering compatible and no pin package does not. In addition, the foot package is significantly smaller than any wave soldering pin package that can be packaged on an equally sized chip.
The same production line used to manufacture USMP foot packages can also be used to manufacture leadless packages. Converting a cut QFN with leadframe 1520 to a USMP that is the same as the PCB footprint using the USMP procedure creates a QFN that does not require modification of the chip, chip leadframe, or PCB path. By converting fabrication of leadless packages such as QFN or DFN from conventional singulation to USMP processes, the fabrication of leadless and footing packages can be performed on the same production line without investment in equipment for a particular package, in particular, eliminating the need for die cutting into individual machine tools and expensive dedicated lead frame "machine tools". (the machine tool die is a cutting tool and should not be confused with a semiconductor chip). Resulting in lower cost and more flexible manufacture. However, leadless QFN packages lacking conductive feet still require expensive reflow-based PCB assembly, even with USMP manufacturing processes.
Fig. 49B illustrates the conversion of a 16-pin cut QFN4 x 4 package leadframe 1520 to a leadframe 1530 equivalent to its wave solder compatible footprint. The effect of this variation is that the plastic body 1521 is slightly reduced in size to form a new plastic body 1531 to accommodate the foot, and the corner connecting bars 1524 are used in a final package of shortened size to form new connecting bars 1534 by laser cutting the debris from the outer surface of the plastic body 1531. Using a foot length of 125 microns and a total foot size of 400 microns, the table describes that one cut QFN can package a maximum chip size of 2.65mm x 2.65mm, as well as a minimum chip size of 2.4mm x 2.4mm in this embodiment, representing a reduction of about 18% in chip area.
However, if we compare this 4 x 4 foot package with the "die cut" QFN leadframe 1540 shown in fig. 49C. The equivalent area foot package 1550 provides a 25% larger chip area, i.e., the foot package can accommodate 125% of the die cut QFN maximum semiconductor chip size of 2.145mm by 2.145 mm. The die cut QFN 1540 is relatively small in its maximum chip size because it must extend deeper into the package than the feet 1552 to avoid tearing off the plastic 1541 when die cut into individual pieces, and the mechanical process of the plastic and leads of the package transfer significant pressure.
The conversion of die cut QFN 1549 into foot packages 1559 with the same PCB dimensions has the effect that the size of the die pad 1546 is increased to form a larger die pad 1556, the size of the plastic body 1541 is increased to form a new plastic body main 1551, and the size of the corner connector bars 1544 is adjusted to form new connector bars 1554, which are cut by the laser to be flush with the outer surface of the plastic body 1541.
The footing QFN is designed for use in assembling a 4 x 4 path PCB with a maximum chip size 18% smaller than the cut QFN and 25% larger than the die cut QFN, as summarized in the table shown in fig. 49D. Considering that the PCB area required to adhere one 4 x 4 QFN on the PCB is actually 4.3mm x 4.3mm, the area efficiency ηarea of the three packages can be directly compared to 38% for cut QFN or USMP cut single QFN, 31% for QFF (quad-leaded QFN) and 28% for die cut QFN.
Note that the maximum chip size and maximum area efficiency for a 4 x 4 package, the diced QFN may also be fabricated by the USMP process without any changes in the leadframe design or fabrication process (other than re-programming the laser scanning process). In practice, this USMP process involves laser metal removal and singulation that can be used to interchangeably fabricate both the USMP leadless QFN44 and the footing QFN 44. The quad flat no-lead package is referred to by the term QFF for the acronym QFN, and a simple modification to the QFF means a "quad flat quad-lead" package.
Another consideration in lead frame design is the effect of pin spacing, i.e., foot-to-foot spacing, on the number of electrical connections for a given package and its effect on PCB assembly. For a pin pitch of 0.5mm, 24 feet are integrated into a 4 x 4QFN or foot QFN package, six feet per side. At small stitch pitch sizes, the wave soldering process has the risk of electrical shorting. The resulting yield loss depends on the PCB assembly plant and its old equipment. As previously indicated, the same 4 x 4 package may be adjusted to a 0.8mm pitch such as in lead frame 1530 where the number of feet is reduced to four total 16 feet per side.
Alternatively, the package may utilize 20 feet, 5 on each side, created by a 0.6mm pitch. In the case of older factory extremes, the stitch spacing may be increased to 1.0 millimm with a total of 12 feet per side of 3, or to 1.27mm stitch spacing, in which case the number of feet is reduced to or 2 total of 8 feet per side. A summary of pin spacing versus pin count for a 4 x 4 foot package is shown in the table below.
Figure GDA0003826875880000721
As previously mentioned, the leadless package name is intended to be suitable for use in conventional QFN package manufacturing or using the USMP process disclosed herein. The foot package name is represented by the term QFN, meaning that a simple modification of a "quad flat no-lead" package is QFF, meaning a "quad flat foot" package.
While the USMP process may be used to fabricate leadless and footing quad-pod packages, the disclosed method is equally applicable to fabricated dual-sided packages. Fig. 49E illustrates the conversion of cut DFN5 x 6 package leadframe 1560 into its wave soldering compatible foot equivalent leadframe 1570. The non-leaded landing pads 1562 are replaced with wave soldering compatible feet 1572 whose plastic body 1561 is reduced slightly in one dimension to form a new plastic body 1571, while the other plastic body is unchanged in dimension to facilitate cutting off the connection of the connecting bar 1564 and laser cutting off the bar 1564 to maintain the same size. Considering the variation in only one dimension, and using a foot length of 0.125mm and a total foot size of 0.4mm, the table illustrates that the maximum chip size of the cut DFN package is 4.35mm x 4.55mm. In this foot version, the foot DFN of the "DFF" is nearly identical to 4.35mm by 4.30mm, with a reduction of about 6% in chip area. However, the foot package is wave soldering compatible and no pin package is not. Furthermore, the USMP process can manufacture both leadless QFN and footing QFF packages even in the same production line and equipment.
Fig. 50A illustrates the conversion of a 2-pin DPAK or TO-252 package leadframe 1580 into its bottom equivalent leadframe 1590A. Because of the area savings, a substantially larger package may be realized using a 1.6mm solderable foot length foot package, with a conventional DPAK 1589 having a maximum chip size of 3.05mm by 4.98mm and a foot DPAK 1599A that can accommodate a 4.05mm by 4.98mm chip or 133% of the conventional maximum chip size. To achieve this significant improvement, the mechanical flex-guides 1582 are replaced by USMP manufactured feet 1592A, the plastic body 1581 is enlarged in size to form an elongated plastic body 1591A, the area of the die pad and heat sink pad 1586 is increased to form a larger die pad and heat sink pad 1596A, and the mechanical-trimmed tie bars 1584 protrude from the plastic body 1581, instead the laser-cut tie bars 1594A are cut out to align with the vertical edges of the plastic body 1591A.
In an alternative embodiment of the design, foot DPAK 1590B, shown in fig. 50B, includes a modification to foot 1592B wherein the weldable portion of the foot is maintained at 1.6mm long, but the foot extends laterally only 0.25mm beyond the edge of plastic 1591B. This USMP design principle is further illustrated in the perspective view of fig. 50D, where the conventional DPAK includes a mechanically bent pin 1582 contacting the PCB by a distance L, where l=1.6 mm in the previous example. In design a of DPAK 1599A manufactured by USMP, foot 1592A extends beyond the vertical edge of plastic 1591 by a full distance of l=1.6 mm, whereas in design B of DPAK 1599B manufactured by USMP, foot 1592B only extends beyond the vertical edge of plastic 1591 by a fraction of the total foot length L, e.g., the remaining foot length L is 0.25mm to 0.5mm and the rest is underneath the package and not visible from the front.
The benefit of the foot DPAK 1599B design B is that the plastic body 1599B is extended to allow the die pad and heat sink pad 1596B to be further enlarged, increasing the maximum allowable die size to 5.29mm x 4.98mm, representing a significant increase in die size, i.e., providing the ability to package more than 173% of a die and using the same PCB board space as a conventional DPAK. The connecting bar 1594B may also be laser cut flush with the vertical plane of the plastic 1591B, eliminating the protruding portion required to mechanically cut the connecting bar 1584 in conventional DPAK assemblies.
A direct comparison of two USMP feet DPAK 1599A and 1599B to a conventional DPAK1589 is shown in fig. 50C, in which the external length deltay is reduced to save space in the USMP design, where deltay 3 <ΔY 2 <ΔY 1 For increasing the area of the die pad and heat sink 1586 to achieve a larger area of die pad and heat sink 1596A and 1596B. As shown, the copper pin contacts the length "L" of the PCB, l=1.6 mm, remains unchanged, while ΔyFor the protruding length of the pins or feet, from deltay 3 =2.7 mm for DPAK to Δy 2 =1.6 mm and Δy 2 =0.25 mm for foot design. Thus, while the PCB landing pads 1587 and 1597 remain in a fixed position, the package still increases the chip pad and maximum chip size. Another advantage is that the feet DPAK 1599A and 1599B, the tie bars 1594A and 594B, respectively, can be completely glued inside the plastic body 1591A and 1591B, whereas in the traditional DPAK1589 the tie bars 1584 inevitably protrude from the package and the plastic 1581, increasing the risk of unnecessary and potential electrical shorts. As further illustrated in fig. 50C and 50D, the height of the foot packages 1599A and 1599B may be significantly made thinner, typically thinner than conventional DPAK1589 30% to 70%, by avoiding mechanical pin bending, depending on the thickness of the leadframe and the amount of heat dissipation required.
Fig. 50E shows a comparison of a conventional DPAK1589 with a design-a foot DPAK1599A and a design-B foot DPAK 1599B. As shown, USMP based packages can accommodate maximum chip sizes of 33% and 74% greater than conventional DPAK. In USMP manufacturing, the singulation is performed using a laser rather than a mechanical tool, and does not require mechanical bending or shaping. DPAKs fabricated as such USMP may be fabricated at higher throughput and lower cost matrix lead frames, rather than in a single package strip, reducing cost and improving manufacturability.
Fig. 51A illustrates the conversion of SOT23 package leadframe 1600 to its foot equivalent leadframe 1610, wherein gull- wing pins 1602A, 1602B, and 1602C are replaced by wave-soldering compatible feet 1612A, 1612B, and 1612C, the pin extension 1604 is replaced by a cantilever extension 1614, and the size of the chip pad 1607 is greatly increased to form a new chip pad 1617. In conventional SOT23, isolated die pad 1607 is connected to pin 1602C, while the other two pins 1602A and 1602B are connected to isolated pin extension 1604 for bonding. All pins, including mechanically curved gull-wing pins, require long pin lengths-in fact the pin lengths are longer than the width of the chip pad. The maximum chip size of the conventional SOT23 shown is about 0.765mm by 1.706mm. In sharp contrast to gull-wing SOT23, the foot version shown for matrix lead frame 1610 includes an isolated die pad 1617 connected to bottom foot 1612C, and two feet 1612A and 1612B connected to cantilevered extension beam 1614. The beam may be further supported by a connecting bar (not shown), if desired.
By eliminating the wasted space consumed by gull-wing pins, the foot package allows the plastic and isolation die pad 1617 to expand in the direction of the pins, increasing the maximum die size to 1.365mm by 1.706mm, and increasing the maximum die size of current SOT23 to 178%. A side-by-side comparison of a conventional SOT-23 1609 with a footed SOT-23 1619 and its corresponding lead frames 1600 and 1610 is shown in fig. 51B, which illustrates that only 13% of the PCB area efficiency of a conventional SOT-23 can be increased to 24% by USMP footed packaging and that the footed SOT-23 can accommodate chips greater than 78% of a conventional SOT-23 package.
In addition to providing the ability to improve transistor package area efficiency, i.e., larger chips in the same package, the USMP design approach may also be applied to significantly reduce the size of the gull-wing I C package. For example, in fig. 52A, a TSSOP-8L package 1649 fabricated from lead frame 1640 and including connecting bars 1644, gull-wing pins 1642, and isolated die pad 1647 is converted to its foot equivalent package 1659A while retaining the same PCB configuration for soldering. As shown, the lead frame 1650A includes a foot 1652A, a larger isolated chip pad 1657A, and an additional connecting bar 1654A for added stability. By designing the foot for the same solder length as a conventional gull-wing package, i.e., 0.6mm, but eliminating the space wasted specially for pin bending and formation, the foot enclosure 1659A maximum chip size increases to 3.8mm by 2.2mm by more than 49% as compared to a conventional TSSOP8 maximum chip size of 2.8mm by 2 mm. In an alternative embodiment, as shown in fig. 52B, the same PCB configuration may be used for a foot equivalent package 1659B including a leadframe 1650B, feet 1652B, even a larger isolated chip pad 1657B, and connecting bars 1654B.
Fig. 52C shows that the PCB area efficiency of a conventional TSSOP-8L package, 27%, can be improved to 40% or 45% with corresponding increases in chip size of 49% and 69%, respectively, using a foot package made of USMP, as compared to three packages. In practice, such as lithium battery protection of this package has become industry standard, increasing the die area by 49% in the same PCB space allows the protection power MOSFETs to either reduce their on-resistance or power consumption or increase their current rating at the same dissipated power. The performance enhancement is particularly beneficial for high-end smartphones with fast charging capability. The USMP manufactured foot package also provides an option that provides additional flexibility in thermal management, whether for isolating or exposing the chip pad.
In fig. 53A, a ubiquitous SOP8 package 1669, including a dual-bar 1664, gull-wing pins 1662, and isolated die pad 1666, and is fabricated from lead frame 1660, is converted into its foot equivalent package 1679A while retaining the same PCB configuration for soldering. As shown, the foot package 1679A is made from a lead frame 1670A, including feet 1672A, larger isolated die pads 1676A, and additional connecting bars 1674A for better stability. The isolated die pad 1676A may be replaced by an exposed die pad as desired, as the foot and die pad are made of the same copper block providing perfect co-planarity. Similar coplanarity is not possible with conventional SOP8 1669 because mechanical pin bending is substantially imprecise. By designing the foot of foot package 1679A to be the same solder length as conventional gull-wing package 1669, i.e., 0.6mm, but eliminating the wasted space dedicated to wire bending and molding, the foot package's chip pad 1676A is increased to support a maximum chip size of 3.285mm by 4.102mm, which is increased by more than 96% over the maximum chip size 2.213mm by 3.102mm of conventional package SOPS 1669. The calculation of the maximum chip size is useful for isolating the chip pad for I C or split transistors, not just for split power MOSFET packages.
In an alternative embodiment, shown in fig. 53B, a foot package 1679B made from lead frame 1670B includes a foot 1672B, a larger isolated or alternative exposed die pad 1676B, and an additional connecting bar 1674B that provides better stability. The chip pad 1676B of the alternative foot package is increased to support a maximum chip size of 4.102mm by 3.792mm, increasing by more than 127% over the traditional SOP8 1669 on chip area. This doubled chip area can be used to accommodate larger ICs with additional functionality or to increase the maximum chip size of one or more power MOSFETs to reduce on-resistance, reduce heat, increase efficiency or expand the current handling capability of the product. A comparison of the conventional and USMP foot SOP8 package performance is summarized in the table of fig. 53C.
The obvious advantage of the USMP footing packaging technology is that the packaging technology is packaged in a four-side pin gull-wing mode. As shown in fig. 54A, an industry standard and commercially available LQFP package 1709A, made from leadframe 1700A and having a body of 7mm x 7mm, corner connecting bars 1704A, gull-wing pins 1702A, and isolated die pad 1706A is converted to its foot equivalent package 1719A while retaining the same PCB configuration for soldering. As shown, a foot package 1719A, fabricated from leadframe 1710A, includes a foot 1712A, a larger isolation die pad 1716A, and a corner connection bar 1714A. The isolated die pad may be replaced with an exposed die pad as desired.
By designing the foot for the same solder length as a conventional gull-wing package, i.e., 0.6mm, eliminating the wasted space dedicated to wire bending and shaping, and optimizing the leadframe, the foot-packaged die pad 1716A increases to a maximum die size of 6.35mm by 6.35mm, which is 318% of the maximum die size of the commercially available LQFP7 by 7, 3.56mm by 3.56 mm. This larger chip area means that today's higher functionality circuits can be integrated into wave soldering packages. The three-fold increase in area is an improvement achieved by the foot design, as conventional leadframe 1700A cannot account for the maximum die size possible. The maximum possible die pad size for a conventional 7 x 7LQFP package 1709B is made from leadframe 1700B as shown in fig. 54B, corner connecting bars 1704B, gull-wing pins 1702B, and isolated die pads 1706B that (theoretically) increase in size to accommodate a maximum die size of 4.950mm x 4.950mm, approaching twice the die size area of commercially available LQFP 1709A.
For completeness, the maximum chip size of the USMP manufacturing foot package is also increased in alternative embodiments. Also shown in fig. 54B is a foot package 1719B made from leadframe 1710B and including feet 1712B, corner connecting bars 1714B, and larger isolation chip pads 1716B capable of increasing the maximum chip size to 6.750mm x 6.750mm.
A comparison of the equivalent of two conventional LQFP packages for their USMP foot packages is summarized in the table of fig. 54C, in which it is assumed that the gull-wing LQFP leadframe 1700B is used as a reference, i.e., the chip area ratio is set to 1.00 and has a PCB area efficiency of 23%. In contrast, the commercially available 7×7LQFP lead frame has a maximum chip size 48% smaller than optimum and a small PCB area efficiency of only 18%. In contrast, the replacement of the LQFP, QFF package maximum chip size with the lead frames 1719A and 1719B with the feet can be 65% and 85% larger than the maximum chip size of the hypothetical reference LQFP lead frame 1708 and more than 200% larger than the maximum chip size for the commercially available 7 x 7LQFP package.
In many cases, when a wave soldering pin package is needed to package chips that were originally developed for QFN leadless packages, no area efficient and cost effective package may be substituted. This is illustrated in the table below, where a 2.65mm x 2.65mm semiconductor chip designed in a 20-pin QFN is required to be packaged in a wave soldering-capable package. Considering this maximum chip size and the number of pins required for a particular IC, only a few options exist, many of which are too large or too expensive to achieve the design goals of the system.
The potential options are summarized in the following table:
Figure GDA0003826875880000761
Figure GDA0003826875880000771
when the foot version of the QFN, QFF-20, can be used to replace conventional packages in terms of low cost and substantially the same PCB area, TSSOP requires three times the area and SOP requires six times the area. The LQFP55 has acceptable area efficiency but it cannot package a 2.65mm by 2.65mm chip, so it is not an option. The LQFP66 is only twice the PCB area, but it is not in production and unlike any packaging company would make a limited market outdated package for high cost. The result is a commercially available LQFP that is only 7mm by 7mm package, three times the size required for the chip. Any package that is more than twice as large will have an excessive cost to support its application.
As a result, the foot package uniquely addresses the problem that no practical solution is available today, providing comparable performance to leadless packages in a cost-effective manner for compatibility with PCB assemblies based on low cost wave soldering.

Claims (16)

1. A method for manufacturing a semiconductor package by using a leadframe design, the leadframe comprising a die pad, a connecting bar, and pins arranged in an array, the leadframe die pad being connected to the leadframe by the connecting bar or a portion of the pins, a first semiconductor die being bonded to the first die pad and a second semiconductor die being bonded to the second die pad during a packaging process, bonding electrical wire bonds of the die to the pins, and molding to form a plastic block, the plastic block covering the first and second semiconductor die, and the pins, the method comprising:
Removing a portion of the plastic block from the plastic block by a first laser beam, wherein the portion of the plastic block covers the pin, and the pin is expected to be exposed outside the plastic capsule;
and removing the first laser beam from the plastic material between the leads that is expected to be exposed outside the plastic capsule, thereby forming a first plastic capsule and a second plastic capsule, the first plastic capsule covering the first semiconductor chip, the second plastic capsule covering the second semiconductor chip;
wherein directing a first laser beam at the plastic block comprises moving the first laser beam through a series of parallel adjacent scans, each scan removing a sheet of the plastic block, and the leadframe further comprises a metal conductor extending between the first and second plastic capsules,
wherein the first laser beam has a first wavelength such that the metal conductor absorbs less of the first laser beam than the plastic block, and a second laser beam is directed at the metal conductor to remove a portion of the metal conductor thereby forming a first pin and a second pin separated by a street, the first pin extending under the first plastic capsule, the second pin extending under the second plastic capsule.
2. The method according to claim 1, characterized in that: directing a second laser beam at the metal conductor includes moving the second laser beam through a series of parallel adjacent scans.
3. The method according to claim 1, characterized in that: the second laser beam is of a second wavelength such that the second laser beam is more readily absorbed by the metal conductor than the first laser beam.
4. The method according to claim 1, characterized in that: the first pin includes a foot section, a post section, and a cantilever section.
5. The method according to claim 4, wherein: the first laser beam is directed against the plastic block such that a side edge of the first plastic capsule is positioned over one of the post segments and the cantilever segments of the first leads, thereby leaving the first leads exposed at the sidewalls of the post segments.
6. The method according to claim 4, wherein: the first laser beam is performed with respect to the plastic block such that the side edges of the first plastic capsule are positioned over the first pins and the foot sections, thus leaving the two side walls of the column covered by the first plastic capsule.
7. The method according to claim 4, wherein: a second laser beam is directed at the metal conductor such that the side edges of the street are vertically aligned with the side edges of the first plastic capsule so as to form a leadless semiconductor package.
8. The method according to claim 1, characterized in that: a second laser beam is directed at the metal conductor such that the side edges of the street are vertically aligned with the side edges of the first plastic capsule so as to form a leadless semiconductor package.
9. The method according to claim 1, characterized in that: next, a second laser beam is directed against the metal conductor to extend from the first plastic capsule to the remaining connecting bar, and the method further includes cutting a third laser beam against the connecting bar such that the connecting bar is flush with the side wall of the first plastic capsule.
10. The method according to claim 9, wherein: directing a third laser beam at the connecting rod includes moving the third laser beam through a series of parallel adjacent scans.
11. The method according to claim 1, characterized in that: the method for forming the lead frame comprises the step of partially etching the back surface of the metal sheet at the first position so as to form a cantilever section of the pin.
12. The method according to claim 11, wherein: forming the leadframe further includes: the front surface of the metal sheet is partially etched in a second position spaced horizontally from the first position so as to form a leg section of the lead, and the first and second positions are spaced by a third position, wherein the metal sheet is not etched so as to form a column section of the lead.
13. The method according to claim 12, wherein: forming the leadframe further includes: in the fourth position, a full etch is performed in the metal sheet so that the pins are separated from the die pad.
14. The method according to claim 13, wherein: forming the leadframe further includes etching the die pad from the back side of the metal sheet so as to form an isolated die pad.
15. The method according to claim 11, wherein: forming the leadframe further includes: in the fourth position the metal sheet is etched completely so that the pins are separated from the die pad.
16. The method according to claim 1, characterized in that: and the method further comprises the step of printing a solder layer on the back surface of the first chip pad so as to weld and assemble the first chip pad and pins contained in the first plastic capsule with a conductive platform and a conductive path on the PCB by using a flowing wave soldering mode.
CN201680040633.2A 2015-07-10 2016-07-06 Universal surface mount semiconductor package Active CN109478544B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/797,056 US9576932B2 (en) 2013-03-09 2015-07-10 Universal surface-mount semiconductor package
US14/797056 2015-07-10
PCT/US2016/041169 WO2017011246A1 (en) 2015-07-10 2016-07-06 Universal surface-mount semiconductor package

Publications (2)

Publication Number Publication Date
CN109478544A CN109478544A (en) 2019-03-15
CN109478544B true CN109478544B (en) 2023-05-26

Family

ID=57757928

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680040633.2A Active CN109478544B (en) 2015-07-10 2016-07-06 Universal surface mount semiconductor package

Country Status (4)

Country Link
CN (1) CN109478544B (en)
MY (2) MY186501A (en)
TW (1) TWI640071B (en)
WO (1) WO2017011246A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI810380B (en) * 2019-02-22 2023-08-01 南韓商愛思開海力士有限公司 System-in-packages including a bridge die
TWI690039B (en) * 2019-07-03 2020-04-01 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof
CN111432554B (en) * 2020-03-13 2021-08-10 清华大学 Micro-system architecture
TWI736409B (en) * 2020-03-27 2021-08-11 美商矽成積體電路股份有限公司 Package structure
CN114839401A (en) * 2022-03-12 2022-08-02 江苏宝浦莱半导体有限公司 High-density arrangement aging board of service life test experiment golden finger plug structure with acceleration

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909178B2 (en) * 2000-09-06 2005-06-21 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US7588999B2 (en) * 2005-10-28 2009-09-15 Semiconductor Components Industries, Llc Method of forming a leaded molded array package
DE102006034679A1 (en) * 2006-07-24 2008-01-31 Infineon Technologies Ag Semiconductor module with power semiconductor chip and passive component and method for producing the same
US8071427B2 (en) * 2009-01-29 2011-12-06 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
US20110115069A1 (en) * 2009-11-13 2011-05-19 Serene Seoh Hian Teh Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same
US8575006B2 (en) * 2009-11-30 2013-11-05 Alpha and Omega Semiconducotr Incorporated Process to form semiconductor packages with external leads
CN101719759B (en) * 2009-12-04 2011-12-14 武汉盛华微系统技术股份有限公司 Method for adhering components and parts to packaging surface
US9831393B2 (en) * 2010-07-30 2017-11-28 Cree Hong Kong Limited Water resistant surface mount device package
KR101698932B1 (en) * 2010-08-17 2017-01-23 삼성전자 주식회사 Semiconductor Package And Method For Manufacturing The Same
US8513787B2 (en) * 2011-08-16 2013-08-20 Advanced Analogic Technologies, Incorporated Multi-die semiconductor package with one or more embedded die pads
JP6095997B2 (en) * 2013-02-13 2017-03-15 エスアイアイ・セミコンダクタ株式会社 Manufacturing method of resin-encapsulated semiconductor device

Also Published As

Publication number Publication date
WO2017011246A1 (en) 2017-01-19
CN109478544A (en) 2019-03-15
TWI640071B (en) 2018-11-01
MY186501A (en) 2021-07-22
TW201712826A (en) 2017-04-01
MY183619A (en) 2021-03-03

Similar Documents

Publication Publication Date Title
US10615146B2 (en) Universal surface-mount semiconductor package
CN109478544B (en) Universal surface mount semiconductor package
US10312111B2 (en) Method of fabricating low-profile footed power package
US11469205B2 (en) Universal surface-mount semiconductor package
CN108364918B (en) Thin profile lead semiconductor package
US7238549B2 (en) Surface-mounting semiconductor device and method of making the same
CN105185752B (en) Semiconductor devices and its manufacturing method
CN101681897B (en) Dual side cooling integrated power device package and module and methods of manufacture
CN102714201B (en) Semiconductor packages and method
US20120181676A1 (en) Power semiconductor device packaging
US9029995B2 (en) Semiconductor device and method of manufacturing the same
TWI601253B (en) Low-profile footed power package
US20130017652A1 (en) Method of manufacturing a semiconductor device package with a heatsink
KR20060021744A (en) A lead frame and the method for manufacturing the same
US20120181677A1 (en) Semiconductor device package with two component lead frame
JP4330980B2 (en) Lead frame manufacturing method and semiconductor device manufacturing method using the same, lead frame and semiconductor device using the same
US20200328092A1 (en) Lead frame, chip package structure, and manufacturing method thereof
JP2006140522A (en) Method of manufacturing lead frame, method of manufacturing semiconductor device using it, the lead frame and the semiconductor device using it
JPH05166988A (en) Semiconductor device, manufacture thereof, and lead frame applied thereto
JP2006502568A (en) Semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20190424

Address after: L-2220, 681 Nudov Road, Luxembourg

Applicant after: ADVENTIVE IPBANK

Address before: Far East Development Building 1501-3, 121 Devon Road Central, Hong Kong, China

Applicant before: ADVENTIVE TECH LTD.

Applicant before: Richard K. Williams

TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20220706

Address after: Far East Development Building 1501-3, 121 Devon Road Central, Hong Kong, China

Applicant after: ADVENTIVE TECH LTD.

Address before: L-2220, 681 Nudov Road, Luxembourg

Applicant before: ADVENTIVE IPBANK

TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20230106

Address after: Room C, 21/F, Liwen Commercial Center, 169 Dian Dian Road, North Point, Hong Kong, China

Applicant after: Chuangyantang International Co.,Ltd.

Address before: Far East Development Building 1501-3, 121 Devon Road Central, Hong Kong, China

Applicant before: ADVENTIVE TECH LTD.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant