JP2009038145A - Lead terminal type semiconductor device - Google Patents

Lead terminal type semiconductor device Download PDF

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JP2009038145A
JP2009038145A JP2007199730A JP2007199730A JP2009038145A JP 2009038145 A JP2009038145 A JP 2009038145A JP 2007199730 A JP2007199730 A JP 2007199730A JP 2007199730 A JP2007199730 A JP 2007199730A JP 2009038145 A JP2009038145 A JP 2009038145A
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lead
semiconductor device
envelope
semiconductor chip
type semiconductor
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Sumio Yoshino
純雄 吉野
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Toshiba Components Co Ltd
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Toshiba Components Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

<P>PROBLEM TO BE SOLVED: To more improve a contactness between a lead and an envelope than heretofore. <P>SOLUTION: In the lead terminal type semiconductor device, which comprises the lead 21, a semiconductor chip 22 mounted on the lead 21, a bonding wire 25 connecting the lead 21 and semiconductor chip 22 to each other, and the envelope 26 sealing a portion of the lead 21, the semiconductor chip 22, and the bonding wire 25 with resin, a projection 23 is provided on the lead 21 in contact with the envelope 26. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、リードと樹脂製外囲器との密着性を改善したリード端子型半導体装置に関する。   The present invention relates to a lead terminal type semiconductor device having improved adhesion between a lead and a resin envelope.

従来、ＤＩＰ型のリード端子型半導体装置としては、図２に示す構成のものが知られている（非特許文献１）。図中の符番１は、内部リード２上にダイボンド材３を介して搭載された半導体チップを示す。この半導体チップ１の周辺には、２列に配置された複数の外部リード４が配置されている。これらの外部リード４の一端には夫々部分銀めっき５が施されている。これらの部分銀めっき５と半導体チップ１は、金製のボンディングワイヤ６により電気的に接続されている。前記半導体チップ１，内部リード２，ボンディングワイヤ６及び外部リード４の一部は、樹脂製の外囲器７により樹脂封止されている。こうした構成のリード端子型半導体装置においては、外部リード４が外囲器７の側部から突出するように外囲器７により樹脂封止されている。   2. Description of the Related Art Conventionally, as a DIP type lead terminal type semiconductor device, one having the configuration shown in FIG. 2 is known (Non-Patent Document 1). Reference numeral 1 in the drawing indicates a semiconductor chip mounted on the internal lead 2 via the die bond material 3. A plurality of external leads 4 arranged in two rows are arranged around the semiconductor chip 1. Partial silver plating 5 is applied to one end of each external lead 4. The partial silver plating 5 and the semiconductor chip 1 are electrically connected by a gold bonding wire 6. A part of the semiconductor chip 1, the internal lead 2, the bonding wire 6 and the external lead 4 are sealed with a resin envelope 7. In the lead terminal type semiconductor device having such a configuration, the external lead 4 is resin-sealed by the envelope 7 so as to protrude from the side portion of the envelope 7.

また、従来、上記半導体装置と種類が異なるリード端子型半導体装置としては、例えば図３（Ａ），（Ｂ）に示す構成のものが知られている。ここで、図３（Ａ）は前記半導体装置の全体の断面図、図３（Ｂ）は図３（Ａ）の半導体装置の一構成であるリードの拡大断面図を示す。   Conventionally, as a lead terminal type semiconductor device of a type different from that of the semiconductor device, for example, one having a structure shown in FIGS. Here, FIG. 3A is a cross-sectional view of the entire semiconductor device, and FIG. 3B is an enlarged cross-sectional view of a lead which is one configuration of the semiconductor device of FIG.

図中の符番１１は、片面（下面）が露出したリードを示す。このリード１１上には半導体チップ１２が搭載されている。半導体チップ１２を除くリード１１の表面には、Ｖ字型の溝１３が複数個形成されている。半導体チップ１２にはパッド１４が形成され、このパッド１４とリード１１とは、ボンディングワイヤ１５を介して電気的に接続されている。前記半導体チップ１２、ボンディングワイヤ１５及びリード１１の一部は、樹脂製の外囲器１６により覆われている。こうした構成の半導体装置は、リード１１を直接実装基板上に搭載するタイプであるため、外囲器１６がリード１１から剥れるのを回避するために、上述したように、リード１１の表面に溝１３を設けている。
半導体用語辞典，第１版，１０９５頁，１９９９年３月２０日発行，（株）日刊工業新聞社（発行所） Reference numeral 11 in the drawing indicates a lead with one side (lower surface) exposed. A semiconductor chip 12 is mounted on the lead 11. A plurality of V-shaped grooves 13 are formed on the surface of the lead 11 excluding the semiconductor chip 12. A pad 14 is formed on the semiconductor chip 12, and the pad 14 and the lead 11 are electrically connected via a bonding wire 15. The semiconductor chip 12, the bonding wire 15, and a part of the lead 11 are covered with a resin envelope 16. Since the semiconductor device having such a configuration is a type in which the lead 11 is directly mounted on the mounting substrate, in order to avoid the envelope 16 from being peeled off from the lead 11, a groove is formed on the surface of the lead 11 as described above. 13 is provided.
Semiconductor Glossary, 1st Edition, 1095 pages, published on March 20, 1999, Nikkan Kogyo Shimbun Co., Ltd. (Issuing Office)

しかしながら、従来のリード端子型半導体装置によれば、リード１１と外囲器１６との密着性がリード１１の表面に設けた溝１３では十分ではなく、外囲器１６がリード１１から剥離し易いという問題があった。また、溝１３はプレス加工、あるいはエッチングにより形成するが、プレス加工ではフレームに反りや歪みが生じやすく、組み立てに悪影響がでやすい。また、エッチングでは、マスキング精度が不充分で十分な加工ができないと共に、加工時間が多くなるという問題があった。   However, according to the conventional lead terminal type semiconductor device, the groove 13 provided on the surface of the lead 11 is not sufficient for adhesion between the lead 11 and the envelope 16, and the envelope 16 is easily peeled off from the lead 11. There was a problem. The grooves 13 are formed by pressing or etching. However, the pressing tends to cause warping and distortion of the frame, and adversely affect assembly. In addition, the etching has a problem that masking accuracy is insufficient and sufficient processing cannot be performed, and processing time increases.

本発明は従来の課題を解決するためになされたもので、外囲器と接するリードの上部に突起物を設けることにより、リードと外囲器との密着性を従来と比べて向上し得るリード端子型半導体装置を提供することを目的とする。   The present invention has been made to solve the conventional problems, and by providing a protrusion on the top of the lead that contacts the envelope, the lead can improve the adhesion between the lead and the envelope as compared with the conventional one. An object is to provide a terminal-type semiconductor device.

本発明に係るリード端子型半導体装置は、請求項１記載のように、リードと、このリードに搭載された半導体チップと、前記リードと半導体チップを接続する接続部と、前記リードの一部、半導体チップ及び接続部を樹脂封止する外囲器とを具備するリード端子型半導体装置において、前記外囲器と接するリードの上部に突起物を設けたことを特徴とする。
本発明に係るリード端子型半導体装置は、請求項２記載のように、前記突起物は、荷重をかけた状態で熱圧着若しくは超音波の少なくともいずれか一方の手段を用いて形成されることを特徴とする。 The lead terminal type semiconductor device according to the present invention, as described in claim 1, includes a lead, a semiconductor chip mounted on the lead, a connecting portion connecting the lead and the semiconductor chip, a part of the lead, In a lead terminal type semiconductor device including a semiconductor chip and an envelope for resin-sealing a connection portion, a protrusion is provided on an upper portion of a lead in contact with the envelope.
In the lead terminal type semiconductor device according to the present invention, as described in claim 2, the protrusion is formed using at least one of thermocompression bonding or ultrasonic waves under a load. Features.

本発明によれば、リードと外囲器との密着性を従来と比べて向上することができる。   According to the present invention, the adhesion between the lead and the envelope can be improved as compared with the conventional case.

本発明において、前記突起物は、荷重をかけた状態で熱圧着を行うか、あるいは荷重をかけた状態で超音波を用いるか、少なくともいずれか一方の手段を用いて形成する。突起物の材料は特に限定されないが、例えば金（Ａｕ），銅（Ｃｕ）あるいはＦｅ−Ｎｉ合金が挙げられる。また、突起物の形状は、平面形状が円形状，四角形状，線形状のいずれでもよい。更に、突起物の数や場所も特に限定されないが、外囲器と接するリードに平面的にみてできるだけ均等に複数個形成することが外囲器の剥れを防止する点で好ましい。   In the present invention, the protrusion is formed using at least one of either thermocompression bonding with a load applied, or ultrasonic waves applied with a load applied. The material of the protrusion is not particularly limited, and examples thereof include gold (Au), copper (Cu), and Fe—Ni alloy. Further, the shape of the protrusion may be any of a circular shape, a quadrangular shape, and a linear shape as a planar shape. Further, although the number and location of the protrusions are not particularly limited, it is preferable that a plurality of protrusions are formed as evenly as possible on the leads in contact with the envelope from the viewpoint of preventing the peeling of the envelope.

次に、本発明の一実施例に係るリード端子型半導体装置について図１（Ａ），（Ｂ）を参照して説明する。ここで、図１（Ａ）は前記半導体装置の断面図、図１（Ｂ）は図１（Ａ）の平面図を示す。
（実施例）
図中の符番２１は、片面（下面）が露出したリードを示す。このリード２１上には半導体チップ２２が搭載されている。半導体チップ２２を除くリード２１の表面には、例えば平面形状が円形の金製の突起物２３が荷重をかけた状態で熱圧着により複数個形成されている。突起物２３は、２個リード２１上に形成されている。半導体チップ２２にはパッド２４が形成され、このパッド２４とリード２１とは、接続部としてのボンディングワイヤ２５を介して電気的に接続されている。前記半導体チップ２２、ボンディングワイヤ２３及びリード２１の一部は、樹脂製の外囲器２６により覆われている。なお、前記突起物２３は、リード２１と外囲器２６との密着度を高めるために設けられている。突起物２３は、外囲器２６で覆われた領域内で数量、レイアウトを自由に設定することができる。 Next, a lead terminal type semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. Here, FIG. 1A is a cross-sectional view of the semiconductor device, and FIG. 1B is a plan view of FIG.
(Example)
Reference numeral 21 in the drawing indicates a lead with one side (lower surface) exposed. A semiconductor chip 22 is mounted on the lead 21. On the surface of the lead 21 excluding the semiconductor chip 22, for example, a plurality of gold projections 23 having a circular planar shape are formed by thermocompression bonding with a load applied. The protrusions 23 are formed on the two leads 21. A pad 24 is formed on the semiconductor chip 22, and the pad 24 and the lead 21 are electrically connected via a bonding wire 25 as a connection portion. The semiconductor chip 22, the bonding wire 23, and a part of the lead 21 are covered with a resin envelope 26. The protrusion 23 is provided to increase the degree of adhesion between the lead 21 and the envelope 26. The number and layout of the protrusions 23 can be freely set within the region covered with the envelope 26.

こうした構成のリード端子型半導体装置において、突起物２３は、リード２１上に半導体チップ２２を形成した後、半導体チップ２１上にパッド２４を形成する時にワイヤを押し付け熱圧着により同時に形成する。   In the lead terminal type semiconductor device having such a configuration, the protrusions 23 are simultaneously formed by pressing the wire and thermocompression bonding when forming the pads 24 on the semiconductor chip 21 after forming the semiconductor chip 22 on the leads 21.

上記実施例によれば、外囲器２６と接するリード２１の表面により突起物２３が複数個略均等に形成された構成になっているため、従来と比べ、外囲器２６とリード２１との密着性が高まり、外囲器２６がリード２１と剥れにくくできる。また、突起物２３は、ワイヤを押し付けて熱圧着により形成するので、従来のようなＶ字型の溝を形成する場合と比較して作り方が簡単であるとともに、リードに反りや歪みが生じることを回避できる。更に、突起物２３は、半導体チップ２２上にパッド２４を形成する時に形成することができるので、従来のエッチングによる溝形成のように特別なマスキング工程が不要となり、作業時間を短縮できる。   According to the above-described embodiment, the plurality of protrusions 23 are formed substantially uniformly by the surface of the lead 21 in contact with the envelope 26, so that the envelope 26 and the lead 21 are compared with the conventional example. Adhesion is enhanced, and the envelope 26 can be hardly peeled off from the lead 21. Further, since the protrusion 23 is formed by thermocompression by pressing a wire, it is simpler to make than the conventional V-shaped groove, and the lead is warped and distorted. Can be avoided. Further, since the protrusion 23 can be formed when the pad 24 is formed on the semiconductor chip 22, a special masking process is not required as in the case of the conventional groove formation by etching, and the working time can be shortened.

なお、本発明は、上記実施例そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具現化できる。また、上記実施例に開示されている複数の構成要素の適宜な組み合せにより種々の発明を形成できる。例えば、実施例に示される全構成要素から幾つかの構成要素を削除しても良い。更に、異なる実施例に亘る構成要素を適宜組み合わせてもよい。具体的には、突起物の作り方は上記実施例で述べた方法に限らないとともに、その数量や形状や材料も特に限定されない。   In addition, this invention is not limited to the said Example as it is, It can implement by modifying a component in the range which does not deviate from the summary in an implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiments. Furthermore, constituent elements in different embodiments may be appropriately combined. Specifically, the method of making the protrusion is not limited to the method described in the above embodiment, and the number, shape, and material are not particularly limited.

本発明の一実施例に係るリード端子型半導体装置の説明図を示す。An explanatory view of a lead terminal type semiconductor device concerning one example of the present invention is shown. 従来のリード端子型半導体装置の部分的に切欠した説明図を示す。An explanatory view in which a conventional lead terminal type semiconductor device is partially cut away is shown. 従来の別なタイプのリード端子型半導体装置の説明図を示す。An explanatory view of another conventional type lead terminal type semiconductor device is shown.

符号の説明Explanation of symbols

２１…リード、２２…半導体チップ、２３…突起物、２４…パッド、２５…ボンディングワイヤ（接続部）、２６…外囲器。   DESCRIPTION OF SYMBOLS 21 ... Lead, 22 ... Semiconductor chip, 23 ... Protrusion, 24 ... Pad, 25 ... Bonding wire (connection part), 26 ... Envelope.

Claims (2)

リードと、このリードに搭載された半導体チップと、前記リードと半導体チップを接続する接続部と、前記リードの一部、半導体チップ及び接続部を樹脂封止する外囲器とを具備するリード端子型半導体装置において、
前記外囲器と接するリードの上部に突起物を設けたことを特徴とするリード端子型半導体装置。 A lead terminal comprising: a lead; a semiconductor chip mounted on the lead; a connecting portion for connecting the lead to the semiconductor chip; and an envelope for resin-sealing a part of the lead, the semiconductor chip and the connecting portion. Type semiconductor device,
A lead terminal type semiconductor device, wherein a protrusion is provided on an upper portion of a lead in contact with the envelope. 前記突起物は、荷重をかけた状態で熱圧着若しくは超音波の少なくともいずれか一方の手段を用いて形成されることを特徴とする請求項１記載のリード端子型半導体装置。 2. The lead terminal type semiconductor device according to claim 1, wherein the protrusion is formed using at least one of thermocompression bonding and ultrasonic waves in a state where a load is applied.
JP2007199730A 2007-07-31 2007-07-31 Lead terminal type semiconductor device Pending JP2009038145A (en)

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JP2014139968A (en) * 2013-01-21 2014-07-31 Toyota Motor Corp Semiconductor device and manufacturing method of the same
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JP2011222616A (en) * 2010-04-06 2011-11-04 Shindengen Electric Mfg Co Ltd Magnetic substrate and electronic circuit module
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JP2014139968A (en) * 2013-01-21 2014-07-31 Toyota Motor Corp Semiconductor device and manufacturing method of the same
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