TW202129892A - 封裝積體電路裝置和封裝半導體裝置 - Google Patents

封裝積體電路裝置和封裝半導體裝置 Download PDF

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Publication number
TW202129892A
TW202129892A TW109132911A TW109132911A TW202129892A TW 202129892 A TW202129892 A TW 202129892A TW 109132911 A TW109132911 A TW 109132911A TW 109132911 A TW109132911 A TW 109132911A TW 202129892 A TW202129892 A TW 202129892A
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layer
semiconductor wafer
insulating layer
redistribution
frame
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TW109132911A
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English (en)
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金相昱
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南韓商三星電子股份有限公司
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Abstract

一種封裝積體電路裝置和封裝半導體裝置。封裝積體電路裝置包括其中具有空腔的框架及位於空腔內的內部半導體晶片。提供下部重佈線層，所述下部重佈線層鄰近框架及內部半導體晶片的下表面延伸。下部重佈線層中具有開口，所述開口至少部分地暴露出內部半導體晶片的下表面。提供下部半導體晶片，所述下部半導體晶片鄰近內部半導體晶片的下表面延伸，且位於下部重佈線層中的開口內。此下部重佈線層包括：（i）覆蓋框架的下表面的絕緣層、（ii）設置在絕緣層上的重佈線圖案以及（iii）設置在絕緣層上且圍繞下部半導體晶片的至少一部分的障壁層。

Description

封裝積體電路裝置和封裝半導體裝置
本揭露的示例性實施例是有關於被配置成承受對其中的半導體晶片的熱損傷的半導體封裝及其製作方法。 [優先權申請案的參考]
本申請案主張於2020年1月20日提出申請的韓國專利申請案第10-2020-0007407號的優先權，所述韓國專利申請案的揭露內容全文併入本案供參考。
隨著半導體晶片的小型化及輕量化，正在研究能夠達成高速/寬頻輸入/輸出（input/output，I/O）傳輸的多晶片封裝。當使用堆疊技術達成包括半導體晶片或半導體晶片封裝的電子電路時，可達成積體度（integration degree）及訊號傳輸特性的改善。
為了達成此種電子電路，需要適當地利用被動元件（例如電容器）或具有半導體晶片的動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）升壓記憶體（boosting memory）。傳統上，可大量生產其中被動元件安裝在封裝的底表面上的結構。但可能存在的缺點是功率傳輸特性可能隨著半導體晶片與被動元件之間的互連長度的增加而降低。此外，被動元件的安裝可導致所得半導體封裝的總高度增加。為此，可能存在缺點是上述結構難以應用於具有日益小型化趨勢的電子產品。因此，需要開發在將半導體晶片與被動元件（例如，電容器）之間的互連長度小型化的同時支持三維積體電路的半導體封裝。
本揭露的示例性實施例提供一種半導體封裝及其製造方法，在所述半導體封裝中，重佈線層被敞開以使得防止在敞開重佈線層的製程中對半導體晶片的熱損傷的同時被動元件能夠直接安裝在半導體晶片上。
根據本揭露實施例的一種封裝半導體裝置包括其中具有空腔的框架。提供設置在所述框架內的內部半導體晶片。提供下部重佈線層，所述下部重佈線層設置在所述框架及所述內部半導體晶片的下表面上。並且提供下部半導體晶片，所述下部半導體晶片設置在所述內部半導體晶片的所述下表面上。在一些實施例中，所述下部重佈線層包括用於部分地暴露出所述內部半導體晶片的所述下表面的開口，其中所述下部半導體晶片設置在所述開口內，其中所述下部重佈線層包括：覆蓋所述框架的所述下表面的絕緣層、設置在所述絕緣層上的重佈線圖案以及設置在所述絕緣層上的障壁層，且其中當自俯視平面圖角度觀察時，所述障壁層圍繞所述下部半導體晶片。
根據本揭露另一實施例的一種半導體封裝包括其中具有空腔的框架。提供設置在所述框架內的內部半導體晶片。提供下部重佈線層，所述下部重佈線層設置在所述框架及所述內部半導體晶片的下表面上。並且提供下部半導體晶片，所述下部半導體晶片設置在所述內部半導體晶片的所述下表面上。所述下部重佈線層包括覆蓋所述內部半導體晶片的所述下表面的第一絕緣層、設置在所述第一絕緣層上的重佈線圖案、設置在所述第一絕緣層上的障壁層以及設置在所述障壁層上同時部分地暴露出所述障壁層的上表面的第二絕緣層。所述下部重佈線層的所述第一絕緣層、所述重佈線圖案、所述障壁層及所述第二絕緣層具有階梯式結構。
根據本揭露另一實施例的一種半導體封裝包括：框架，包括空腔；內部半導體晶片，設置在所述框架內；下部重佈線層，設置在所述框架及所述內部半導體晶片的下表面上；以及下部半導體晶片，設置在所述內部半導體晶片的所述下表面上。根據一些實施例，所述下部重佈線層包括用於部分地暴露出所述內部半導體晶片的所述下表面的開口。所述下部半導體晶片設置在所述開口內，且所述下部重佈線層包括覆蓋所述框架的所述下表面的第一絕緣層。重佈線圖案設置在所述第一絕緣層上，障壁層設置在所述第一絕緣層上，且第二絕緣層設置在所述障壁層上。所述下部半導體晶片包括設置在所述內部半導體晶片的所述下表面上的本體。焊球電性連接所述本體與所述內部半導體晶片。模製層夾置在所述本體與所述下部重佈線層之間。當在俯視圖中觀察時，所述障壁層圍繞所述下部半導體晶片，且所述障壁層的上表面的一部分接觸所述模製層。
圖1是根據本揭露示例性實施例的半導體封裝10的示意性俯視圖。圖2是根據本揭露示例性實施例的半導體封裝10A沿著圖1中的線I-I’截取的剖視圖。
參考圖1及圖2，半導體封裝10A可包括下部半導體封裝100及上部半導體封裝300。半導體封裝10可為例如具有疊層封裝（package-on-package，PoP）結構的半導體封裝，其中上部半導體封裝300安裝在下部半導體封裝100上。下部半導體封裝100可為例如具有扇出型面板級封裝（fan-out-panel-level package，FOPLP）結構的半導體封裝。下部半導體封裝100可包括框架105、內部半導體晶片120、包封體130、下部重佈線層140/150/160、下部半導體晶片200、上部重佈線層170/180及連接端子190。框架105可包括芯體110、連接接墊111及矽穿孔（through-silicon-via，TSV）112。舉例來說，框架105可為印刷電路板。
芯體110在其中心部分處具有空腔CV。當在俯視圖中觀察時，芯體110可為具有四邊形的輪緣形狀的板。可堆疊多個芯體110。舉例來說，芯體110可由選自酚醛樹脂、環氧樹脂和聚醯亞胺的群組中的至少一種材料製成。舉例來說，芯體110可包含選自阻燃劑4（flame retardant 4，FR4）、四官能環氧樹脂、聚苯醚、雙馬來醯亞胺三嗪（bismaleimide triazine，BT）、環氧樹脂/聚苯醚、塞門特（Thermount）、氰酸酯、聚醯亞胺和液晶聚合物的群組中的至少一種材料。
連接接墊111可設置在芯體110的上表面HS及下表面LS處。每一矽穿孔112可延伸穿過芯體110，以電性連接設置在芯體110的上表面HS處的連接接墊111及設置在芯體110的下表面LS處的連接接墊111中的對應的連接接墊。舉例來說，每一連接接墊111可包含選自電解沈積（electrolytically-deposited，ED）銅箔、輥軋退火（rolled-annealed，RA）銅箔、不銹鋼箔、鋁箔、超薄銅箔、濺鍍銅和銅合金的群組中的至少一種。矽穿孔112可選自包含銅、鎳、不銹鋼和鈹銅的群組中的至少一種。
內部半導體晶片120可設置在芯體110的空腔CV內。空腔CV可具有較內部半導體晶片120大的水平橫截面積。內部半導體晶片120可設置成在芯體110的空腔CV內與芯體110的內側表面間隔開。
晶片接墊122可設置在內部半導體晶片120的下部部分處。晶片接墊122的下表面可與內部半導體晶片120的下表面共面。晶片接墊122的下表面可與設置在芯體110的下表面LS處的連接接墊111的下表面共面。在示例性實施例中，每一晶片接墊122可設置在內部半導體晶片120的下表面上，同時具有自內部半導體晶片120的下表面突出的結構。
舉例來說，內部半導體晶片120可為中央處理器單元（central processor unit，CPU）、微處理器單元（microprocessor unit，MPU）、圖形處理器單元（graphics processor unit，GPU）或應用處理器（application processor，AP）單元。在示例性實施例中，內部半導體晶片120可為被配置成控制稍後將闡述的上部半導體封裝300的控制器半導體晶片。
包封體130可設置在芯體110的空腔CV內。包封體130可完全填充芯體110的內側表面與內部半導體晶片120的側表面之間的空間，且可接觸下部重佈線層140/150/160及上部重佈線層170/180。下部重佈線層140/150/160可設置在框架105的下表面上。上部重佈線層170/180可設置在框架105的上表面上。
重佈線層140/150/160可包括絕緣層140及重佈線圖案150。多個絕緣層140可堆疊在框架105的下表面上。舉例來說，絕緣層140可包括依序堆疊在框架105的下表面上的第一絕緣層141、第二絕緣層143及第三絕緣層145。第一絕緣層141可覆蓋框架105的下表面。第三絕緣層145可形成下部半導體封裝100的底表面。第二絕緣層143可設置在第一絕緣層141與第三絕緣層145之間。
所述多個絕緣層140中的至少一者可由與其餘絕緣層140的材料不同的材料製成。舉例來說，第一絕緣層141及第二絕緣層143可由感光成像介電質（photo imageable dielectric，PID）製成，且第三絕緣層145可為味之素構成膜（ajinomoto build-up film，ABF）。（參見，例如https://www.ajinomoto.com/innovation/action/buildupfilm）。在示例性實施例中，第一絕緣層141及第二絕緣層143可包含環氧樹脂或聚醯亞胺。
多個重佈線圖案150可以多層結構的形式設置在框架105的下表面上。重佈線圖案150可包括通孔151及153以及配線層152及154。重佈線圖案150可包括凸塊下金屬（under-bump-metallurgy，UBM）接墊155。舉例來說，重佈線圖案150可包含銅、鎳、不銹鋼或銅合金，例如鈹銅。
下部半導體晶片200可設置在內部半導體晶片120的下表面上。下部半導體晶片200可使用覆晶接合製程接合至內部半導體晶片120。下部半導體晶片200可包括本體201、焊球203及模製層205。
焊球203可分別設置在內部半導體晶片120的一些晶片接墊122上。本體201可設置在內部半導體晶片120的下表面處的焊球203上。焊球203可電性連接本體201與內部半導體晶片120。模製層205可覆蓋本體201的側表面及下表面，同時覆蓋焊球203及內部半導體晶片120的被暴露的表面。模製層205可夾置在本體201與下部重佈線層140/150/160之間。
上部重佈線層170/180可設置在框架105的上表面上。上部重佈線層170/180可包括絕緣層170及重佈線圖案180。絕緣層170可包含ABF及阻焊層。重佈線圖案180可包括通孔181及配線層183。重佈線圖案180可包括連接接墊185。每一通孔181可延伸穿過覆蓋芯體110的上表面HS的包封體130，且因此可連接連接接墊111中的對應的一者與配線層183的對應部分。配線層183可設置在包封體130上。連接接墊185可分別設置在一些配線層183上。在本發明的一些實施例中，通孔181及配線層183可包含銅。在本發明的一些實施例中，連接接墊185可包含鎳及/或鋁。在本發明的一些實施例中，上部重佈線層170/180可包含與下部重佈線層140/150/160相同的材料，但不限於此。
連接端子190可設置在下部重佈線層140/150/160上。在此種情況下，每一連接端子190可接觸重佈線圖案150的UBM接墊155中的對應的一者。連接端子190亦可設置在上部重佈線層170/180的重佈線圖案180上。在此種情況下，連接端子190可接觸相應的連接接墊185。舉例來說，每一連接端子190可為焊球或焊料凸塊。連接端子190可電性連接下部半導體封裝100與上部半導體封裝300。
上部半導體封裝300可使用覆晶接合製程接合至下部半導體封裝100。上部半導體封裝300可藉由連接端子190及上部重佈線層170/180電性連接至內部半導體晶片120。舉例來說，上部半導體封裝300可包括記憶體半導體晶片，且記憶體半導體封裝300可包括揮發性記憶體半導體晶片（例如DRAM或靜態隨機存取記憶體（Static Random Access Memory，SRAM））或者非揮發性記憶體半導體晶片（例如電阻式隨機存取記憶體（Resistance Random Access Memory，RRAM）、磁性隨機存取記憶體（Magnetic Random Access Memory，MRAM）或鐵電隨機存取記憶體（Ferroelectric Random Access Memory，FeRAM）。
圖3是圖2所示根據本揭露示例性實施例的半導體封裝10A中的一部分A的俯視圖。圖4是圖2所示根據本揭露示例性實施例的半導體封裝10A中的一部分B的放大圖。
參考圖2及圖3，下部重佈線層140/150/160可包括設置在第一絕緣層141上的障壁層160。障壁層160可設置在與接觸第一絕緣層141的上表面的配線層152相同的水平高度處。當在俯視圖中觀察時，障壁層160可圍繞下部半導體晶片200。舉例來說，當在俯視圖中觀察時，障壁層160可具有四邊形環形狀。當在俯視圖中觀察時，障壁層160可與下部半導體晶片200間隔開。
參考圖2至圖4，下部重佈線層140/150/160可具有延伸穿過絕緣層140及障壁層160的開口OP，以部分地暴露出內部半導體晶片120的下表面。下部半導體晶片200可設置在開口OP內。開口OP可由絕緣層140的內側表面、絕緣層140的上表面、障壁層160的內側表面及障壁層160的上表面來界定。界定開口OP的下部重佈線層140/150/160的內側表面及上表面可形成階梯式結構。當在俯視圖中觀察時，階梯式結構可具有圍繞下部半導體晶片200的四個階梯式結構S1、S2、S3及S4。
具有階梯式結構的下部重佈線層140/150/160可包括台階面。在示例性實施例中，下部重佈線層140/150/160可包括多個台階面ST1、ST2及ST3。所述多個台階面ST1、ST2及ST3可包括暴露出障壁層160的上表面的第一台階面ST1以及暴露出絕緣層140的上表面的第二台階面ST2及第三台階面ST3。在示例性實施例中，可省略第二台階面ST2及第三台階面ST3中的任一者。即，第一絕緣層141的上表面可被障壁層160完全覆蓋，或者第二絕緣層143的上表面可被第三絕緣層145完全覆蓋。
下部重佈線層140/150/160的內側表面可相對於內部半導體晶片120的下表面具有傾斜度（inclination）。舉例來說，障壁層160的內側表面可相對於障壁層160的下表面具有傾斜度。此外，絕緣層140的內側表面可相對於絕緣層140的下表面具有傾斜度。舉例來說，在絕緣層140的內側表面與絕緣層140的下表面之間形成的角度α°可為約60°至80°。
下部半導體晶片200的模製層205可完全覆蓋本體201的側表面。模製層205可填充開口OP，使得模製層205延伸穿過下部重佈線層140/150/160。模製層205可覆蓋絕緣層140的側表面及上表面以及障壁層160的側表面及上表面。在示例性實施例中，下部半導體晶片200的本體201可與第一絕緣層141垂直交疊。
在示例性實施例中，模製層205的上表面可連接設置在最上水平高度處的下部重佈線層140/150/160的邊緣（即，第三絕緣層145的邊緣）與下部半導體晶片200的本體201的邊緣。模製層205的上表面可相對於內部半導體晶片120的下表面具有傾斜度。在示例性實施例中，本體201的側表面與障壁層160的內側表面之間的最大水平距離D1可小於本體201的側表面與第二絕緣層143的內側表面之間的最小水平距離D2。
圖5A是根據本揭露示例性實施例的半導體封裝10B沿著圖1中的線I-I’截取的剖視圖。參考圖5A，下部半導體封裝100與上部半導體封裝300可藉由導線電性連接。上部半導體封裝300可接觸上部重佈線層170/180的絕緣層170。
圖5B是根據本揭露示例性實施例的半導體封裝20的剖視圖。根據本揭露的示例性實施例的半導體封裝20可為晶圓級封裝。舉例來說，半導體封裝20可為如圖5B所示的扇出型晶圓級封裝（fan-out wafer-level package，FOWLP）。作為另一選擇，半導體封裝20可為扇入型晶圓級封裝（fan-in wafer-level package，FIWLP）。在示例性實施例中，扇出型晶圓級封裝可包括在安裝的疊層封裝（PoP）型封裝中。參考圖5B，半導體封裝20可包括內部半導體晶片220、模製層230、重佈線層140/150/160、連接端子190及下部半導體晶片200。舉例來說，模製層230可包含環氧模製化合物（epoxy molding compound，EMC）。
圖6至圖20是解釋根據本揭露示例性實施例的半導體封裝製造方法的剖視圖。圖6示出框架105中可用於單元封裝的區的橫截面。框架105可具有各種尺寸，以易於大規模生產。結合此種情況，在所述方法中，可製備具有大尺寸的框架105，且可使用框架105製造多個半導體封裝。此後，可藉由鋸切製程將半導體封裝單體化成單個封裝。
參考圖6及圖7，所述方法可包括：製備包括芯體110、連接接墊111及矽穿孔（TSV）112的框架105；以及形成延伸穿過框架105的空腔CV。舉例來說，空腔CV的形成可藉由機械鑽孔及/或雷射鑽孔、使用磨粒的噴砂製程或使用電漿的乾式蝕刻製程等來施行。
參考圖8，所述方法可包括：將黏合膜115貼附至框架105的下表面；以及將內部半導體晶片120設置在芯體110的空腔CV內。舉例來說，黏合膜115可為味之素構成膜（ABF）。黏合膜115可用作支撐內部半導體晶片120的支撐膜。黏合膜115可覆蓋連接接墊111的下表面及/或芯體110的下表面。
內部半導體晶片120可在設置在芯體110的空腔CV內的同時貼合至黏合膜115。內部半導體晶片120可被設置成與空腔CV的內側表面間隔開。結果，可在芯體110的內側表面與內部半導體晶片120的側表面之間形成空間。
在內部半導體晶片120的下表面處設置晶片接墊122。內部半導體晶片120可以面朝下的方式設置，使得晶片接墊122指向下。內部半導體晶片120的下表面及晶片接墊122的下表面可被黏合膜115完全覆蓋。
參考圖9，所述方法可包括在芯體110與內部半導體晶片120之間的空間中形成包封體130。包封體130可完全填充在芯體110的內側表面與內部半導體晶片120的側表面之間的空腔CV中界定的空間。包封體130可接觸黏合膜115的上表面。包封體130可用於固定內部半導體晶片120，且因此可最小化在後續製程中因內部半導體晶片120的移動所引起的問題。
參考圖10，所述方法可包括：將第一載體基板CA1貼合至框架105及內部半導體晶片120；以及移除黏合膜115。參考圖11至圖13，所述方法亦可包括在框架105的下表面上形成下部重佈線層140/150/160。下部重佈線層140/150/160的形成可包括形成絕緣層140、形成重佈線圖案150及形成障壁層160。
參考圖11，將在貼合第一載體基板CA1之後獲得的所得結構顛倒，使得第一載體基板CA1指向下，且晶片接墊122指向上。此後，所述方法可包括在框架105的下表面上形成第一絕緣層141。第一絕緣層141可覆蓋框架105的被暴露的下表面、包封體130的下表面以及連接接墊111的下表面及側表面。第一絕緣層141亦可覆蓋內部半導體晶片120的被暴露的表面。此外，第一絕緣層141可覆蓋內部半導體晶片120的晶片接墊122的被暴露的表面。可藉由部分地移除第一絕緣層141來形成通孔孔洞VH。通孔孔洞VH可被形成為分別與連接接墊111的部分及內部半導體晶片120的晶片接墊122的選擇的晶片接墊垂直交疊。在示例性實施例中，通孔孔洞VH可包括與內部半導體晶片120垂直交疊而不與晶片接墊122交疊的通孔孔洞VHa。舉例來說，可藉由曝光來形成通孔孔洞VH。作為另一選擇，可藉由使用紫外（ultraviolet，UV）雷射或準分子雷射的雷射鑽孔方法來形成通孔孔洞VH。
參考圖12，所述方法可包括：形成遮罩圖案MP；以及形成第一重佈線圖案151/152及障壁層160。包括遮罩開口MOP的遮罩圖案MP可形成在第一絕緣層141上。舉例來說，遮罩圖案MP可包括光致抗蝕劑。第一重佈線圖案151/152及障壁層160可被形成為完全填充通孔孔洞VH，同時填充遮罩開口MOP的至少一部分。第一重佈線圖案151/152可包括：通孔151，分別形成在通孔孔洞VH中的選擇的通孔孔洞中同時分別連接至連接接墊111及晶片接墊122中的對應接墊；以及配線層152，具有各自形成在遮罩圖案MP的相鄰部分之間的部分，以連接至通孔151中的對應一者。障壁層160可包括通孔161，分別形成在通孔孔洞VHa中；以及板層163，具有分別形成在遮罩開口MOP中的部分以連接至通孔161中的對應通孔。在示例性實施例中，障壁層160可不包括通孔161，而包括板層163。當自第一絕緣層141省略通孔孔洞VHa時，亦可省略通孔161。板層163可被形成為具有較第一重佈線圖案151/152的配線層152更大的水平面積。板層163可被形成為與內部半導體晶片120的多個晶片接墊122垂直交疊。舉例來說，當在俯視圖中觀察時，與板層163垂直交疊的多個晶片接墊122可以晶格圖案的形式排列（參見例如圖17）。
舉例來說，第一重佈線圖案151/152及障壁層160可包含銅。在形成第一重佈線圖案151/152及障壁層160之後，可藉由灰化或剝離來移除遮罩圖案MP。
在示例性實施例中，可藉由鍍覆方法來形成第一重佈線圖案151/152及障壁層160。舉例來說，用於形成第一重佈線圖案151/152及障壁層160的鍍覆方法可包括電鍍方法、無電鍍覆方法及/或浸鍍方法。當藉由鍍覆方法形成第一重佈線圖案151/152及障壁層160時，可在形成遮罩圖案MP之前形成覆蓋框架105的連接接墊111及內部半導體晶片120的晶片接墊122的晶種層。
參考圖13，所述方法可包括：形成第二絕緣層143、第二重佈線圖案153/154、第三絕緣層145及UBM接墊155，從而形成下部重佈線層140/150/160。第二絕緣層143及第二重佈線圖案153/154可以與第一絕緣層141及第一重佈線圖案151/152相同的方式形成。第二重佈線圖案153/154可電性連接至第一重佈線圖案151/152。障壁層160可與第二重佈線圖案153/154電性絕緣。障壁層160的上表面可被第二絕緣層143完全覆蓋。
第三絕緣層145可被形成為覆蓋第二絕緣層143的上表面以及第二重佈線圖案153/154的上表面及側表面。可在第三絕緣層145處形成貫穿孔，且可在相應的貫穿孔中形成UBM接墊155。舉例來說，第三絕緣層145可為味之素構成膜（ABF）。
參考圖14，所述方法可包括：將第二載體基板CA2貼合至下部重佈線層140/150/160的上表面；以及在框架105的上表面上形成上部重佈線層170/180。第二載體基板CA2可貼合至下部重佈線層140/150/160的上表面，且然後可將在貼合第二載體基板CA2之後獲得的所得結構顛倒，使得下部重佈線層140/150/160及載體基板CA2指向下。此後，可在框架105及內部半導體晶片120的上表面上形成包括絕緣層170及重佈線圖案180的上部重佈線層170/180。形成上部重佈線層170/180的方法可相同或相似於形成下部重佈線層140/150/160的方法。上部重佈線層170/180的重佈線圖案180可包括通孔181、配線層183及連接接墊185。在形成上部重佈線層170/180之後，可移除第二載體基板CA2。
參考圖15，所述方法可包括形成通過其將第二絕緣層143暴露出來的第一開口OP1。在將在移除第二載體基板CA2之後獲得的所得結構顛倒使得下部重佈線層140/150/160指向上之後，可藉由移除第三絕緣層145的一部分來形成第一開口OP1。第一開口OP1可被形成為與障壁層160垂直交疊。
為了形成第一開口OP1，可使用雷射鑽孔方法，所述雷射鑽孔方法使用經最佳化以用於移除第三絕緣層145的雷射及雷射波長。在示例性實施例中，為了形成第一開口OP1，可使用利用CO2 雷射或準分子雷射的雷射鑽孔方法。舉例來說，當第三絕緣層145是味之素構成膜（ABF）時，可使用波長為10.6微米的CO2 雷射來形成第一開口OP1。由於第一開口OP1是藉由雷射形成，因此第三絕緣層145的內側表面可具有傾斜度。
參考圖16，所述方法可包括形成通過其將障壁層160暴露出來的第二開口OP2。移除經由第一開口OP1而被暴露出的第二絕緣層143的一部分以形成第二開口OP2，障壁層160的上表面經由第二開口OP2而被暴露出。第二開口OP2可具有較第一開口OP1的最小水平寬度（第一開口OP1的下端的寬度）小的最大水平寬度（第二開口OP2的上端的寬度）。界定第二開口OP2的第二絕緣層143的上表面可經由第一開口OP1而被暴露出。在示例性實施例中，第二開口OP2的最大水平寬度可實質上等於第一開口OP1的最小水平寬度，且因此，第二絕緣層143的上表面可被第三絕緣層145的上表面完全覆蓋。為了形成第二開口OP2，可使用雷射鑽孔方法，所述雷射鑽孔方法使用經最佳化以用於移除第二絕緣層143的雷射及雷射波長。在示例性實施例中，為了形成第二開口OP2，可使用利用CO2 雷射或準分子雷射的雷射鑽孔方法。舉例來說，當第二絕緣層143是感光成像介電質（PID）時，可使用波長為248奈米至308奈米的準分子雷射形成第二開口OP2。由於第二開口OP2是藉由雷射形成，因此第二絕緣層143的內側表面可具有傾斜度。
第一開口OP1及第二開口OP2的水平橫截面積可小於障壁層160的水平橫截面積。第一開口OP1及第二開口OP2可與障壁層160完全垂直交疊。
參考圖17，所述方法可包括：依序形成第三開口OP3及第四開口OP4，從而形成延伸穿過下部重佈線層140/150/160的單個開口OP。可根據通過第二開口OP2而被暴露出的障壁層160的一部分的移除來形成通過其將第一絕緣層141的上表面暴露出來的第三開口OP3。第三開口OP3可具有較第二開口OP2的最小水平寬度（第二開口OP2的下端的寬度）小的最大水平寬度（第三開口OP3的上端的寬度）。在此種情況下，障壁層160的上表面可經由第二開口OP2而被部分地暴露出。為了形成第三開口OP3，可使用雷射鑽孔方法，所述雷射鑽孔方法使用經最佳化以用於移除障壁層160的雷射及雷射波長。在示例性實施例中，為了形成第三開口OP3，可使用利用紫外雷射的雷射鑽孔方法。舉例來說，當障壁層160是銅（Cu）時，可使用波長為355奈米的紫外雷射來形成第三開口OP3。由於第三開口OP3是藉由雷射形成，因此障壁層160的內側表面可具有傾斜度。
在形成開口OP的程序期間，內部半導體晶片120可能經受由雷射引起的熱損傷。結合此種情況，在移除較障壁層160更高水平高度處的絕緣層140期間，鄰近內部半導體晶片120設置的障壁層160可防止藉由雷射向內部半導體晶片120施加熱能。特別地，在形成第一開口OP1及第二開口OP2的雷射鑽孔製程中，障壁層160可防止雷射朝向內部半導體晶片120前進，且因此，可將由雷射鑽孔製程造成的對內部半導體晶片120的熱損傷最小化。
此後，可移除經由第三開口OP3而被暴露出的第一絕緣層141的一部分，以形成第四開口OP4，內部半導體晶片120的表面及晶片接墊122經由第四開口OP4而被暴露出。為了形成第四開口OP4，可使用具有皮秒（picosecond）或飛秒（femtosecond）脈波寬度的雷射。當使用具有皮秒或飛秒脈波寬度的雷射來移除直接接觸內部半導體晶片120的第一絕緣層141時，可將對內部半導體晶片120的熱損傷最小化。由於第四開口OP4是藉由雷射形成，因此第一絕緣層141的內側表面可具有傾斜度。
參考圖18及圖19，所述方法可包括：在開口OP內設置下部半導體晶片200。下部半導體晶片200可安裝在經由開口OP而被暴露出的內部半導體晶片120上。下部半導體晶片200的焊球203可電性連接內部半導體晶片120的晶片接墊211與下部半導體晶片200的本體201。
可形成模製層205，使得模製層205夾置在下部半導體晶片200的本體201與下部重佈線層140/150/160之間。模製層205可被形成為填充開口OP。模製層205可被形成為覆蓋本體201的側表面及下表面、焊球203的被暴露的表面以及下部重佈線層140/150/160的內側表面。舉例來說，模製層205可包含環氧模製化合物（EMC）。
所述方法可包括：在下部重佈線層140/150/160的相應的UBM接墊155上形成連接端子190。舉例來說，每一連接端子190可為凸塊。下部半導體晶片200藉由下部重佈線層140/150/160直接安裝在內部半導體晶片120上，且因此，下部半導體晶片200突出超過絕緣層140的下表面的高度可減小。如此，每一連接端子190的尺寸可對應地減小。結果，半導體封裝的總高度可減小。此外，下部半導體晶片200與內部半導體晶片120之間的佈線距離可減小，且因此，可增強半導體封裝的整體效能。
參考圖20，所述方法可包括：在上部重佈線層170/180上設置連接端子190。再次參考圖2，所述方法可包括：在連接端子190上形成上部半導體封裝300。
在根據本揭露示例性實施例的半導體封裝中，被動元件直接安裝在半導體晶片上，且因此，可減小半導體晶片與被動元件之間的佈線距離，且可改善半導體晶片及被動元件的特性。此外，每一半導體封裝可具有減小的總高度，且因此，可對電子產品具有高實用性。
在根據本揭露示例性實施例的半導體封裝中，用於阻擋雷射的障壁層包括在重佈線層中，且因此，可避免在敞開重佈線層的雷射鑽孔製程中對半導體晶片的熱損傷。
儘管已參考附圖闡述了本揭露的實施例，但熟習此項技術者應理解，在不背離本揭露的範圍且不改變其本質特徵的情況下，可進行各種修改。因此，上述實施例應被認為僅具有闡述性意義，而非用於限制目的。
10、10A、10B、20:半導體封裝 100:下部半導體封裝 105:框架 110:芯體 112:矽穿孔 111、185:連接接墊 120:內部半導體晶片 122:晶片接墊 130:包封體 140、170:絕緣層 141:第一絕緣層 143:第二絕緣層 145:第三絕緣層 150、180:重佈線圖案 151、153、161、181:通孔 152、154、183:配線層 155:凸塊下金屬接墊 160:障壁層 163:板層 190:連接端子 200:下部半導體晶片 201:本體 203:焊球 205、230:模製層 220:內部半導體晶片 300:上部半導體封裝/記憶體半導體封裝 A、B:部分 CA1:第一載體基板 CA2:第二載體基板 CV:空腔 D1:最大水平距離 D2:最小水平距離 HS:上表面 I-I’:線 LS:下表面 MP:遮罩圖案 MOP:遮罩開口 OP:開口 OP1:第一開口 OP2:第二開口 OP3:第三開口 OP4:第四開口 S1、S2、S3、S4:階梯式結構 ST1:第一台階面 ST2:第二台階面 ST3:第三台階面 VH、VHa:通孔孔洞 α°:角度
圖1是根據本揭露示例性實施例的半導體封裝10的示意性俯視圖。 圖2是根據本揭露示例性實施例的半導體封裝10A沿著圖1中的線I-I’截取的剖視圖。 圖3是圖2所示根據本揭露示例性實施例的半導體封裝10A中的一部分A的俯視圖。 圖4是圖2所示根據本揭露示例性實施例的半導體封裝10A中的一部分B的放大圖。 圖5A是根據本揭露示例性實施例的半導體封裝10B沿著圖1中的線I-I’截取的剖視圖。 圖5B是根據本揭露示例性實施例的半導體封裝20的剖視圖。 圖6至圖20是解釋根據本揭露示例性實施例的半導體封裝製造方法的剖視圖。
10A:半導體封裝
100:下部半導體封裝
105:框架
110:芯體
111、185:連接接墊
112:矽穿孔
120:內部半導體晶片
122:晶片接墊
130:包封體
140、170:絕緣層
141:第一絕緣層
143:第二絕緣層
145:第三絕緣層
150、180:重佈線圖案
151、153、181:通孔
152、154、183:配線層
155:凸塊下金屬接墊
160:障壁層
190:連接端子
200:下部半導體晶片
201:本體
203:焊球
205:模製層
300:上部半導體封裝/記憶體半導體封裝
A、B:部分
CV:空腔
HS:上表面
LS:下表面
I-I’:線

Claims (20)

  1. 一種封裝積體電路裝置，包括： 框架，具有空腔； 內部半導體晶片，在所述空腔內； 下部重佈線層，鄰近所述內部半導體晶片及所述框架的下表面延伸，所述下部重佈線層具有在其中至少部分地暴露出所述內部半導體晶片的所述下表面的開口；以及 下部半導體晶片，鄰近所述內部半導體晶片的所述下表面，且位於所述下部重佈線層中的所述開口內，所述下部重佈線層包括：（i）覆蓋所述框架的所述下表面的絕緣層、（ii）設置在所述絕緣層上的重佈線圖案以及（iii）設置在所述絕緣層上且圍繞所述下部半導體晶片的至少一部分的障壁層。
  2. 如請求項1所述的封裝積體電路裝置，其中當自俯視平面圖角度觀察時，所述障壁層具有大致四邊形的輪緣形狀。
  3. 如請求項1所述的封裝積體電路裝置，其中所述下部半導體晶片包括： 本體，設置在所述內部半導體晶片的所述下表面上； 焊球，電性連接所述本體與所述內部半導體晶片；以及 模製層，在所述本體與所述下部重佈線層之間延伸。
  4. 如請求項3所述的封裝積體電路裝置，其中所述模製層延伸穿過所述下部重佈線層時，所述模製層填充所述開口且完全覆蓋所述本體的側表面。
  5. 如請求項4所述的封裝積體電路裝置，其中所述下部重佈線層的所述開口的上表面包括第一台階面，所述障壁層的上表面在所述第一台階面處被部分地暴露出。
  6. 如請求項5所述的封裝積體電路裝置，其中所述下部重佈線層的所述開口的所述上表面更包括第二台階面，所述絕緣層的上表面在所述第二台階面處被部分地暴露出。
  7. 如請求項1所述的封裝積體電路裝置，其中所述障壁層具有傾斜的側表面。
  8. 如請求項1所述的封裝積體電路裝置，其中所述絕緣層的內側表面以約60°至約80°的角度傾斜。
  9. 如請求項1所述的封裝積體電路裝置，更包括： 上部重佈線層，設置在所述框架及所述內部半導體晶片上，所述上部重佈線層包括重佈線圖案及絕緣層；以及 上部半導體晶片，設置在所述上部重佈線層上。
  10. 如請求項9所述的封裝積體電路裝置，更包括： 矽穿孔，延伸穿過所述框架且電性連接所述下部重佈線層的所述重佈線圖案與所述上部重佈線層的所述重佈線圖案。
  11. 一種封裝半導體裝置，包括： 框架，具有空腔； 內部半導體晶片，在所述框架內； 下部重佈線層，鄰近所述內部半導體晶片及所述框架的下表面延伸，所述下部重佈線層包括覆蓋所述內部半導體晶片的所述下表面的至少一部分的第一絕緣層、設置在所述第一絕緣層上的重佈線圖案、設置在所述第一絕緣層上的障壁層以及設置在所述障壁層上同時部分地暴露出所述障壁層的上表面的第二絕緣層；以及 下部半導體晶片，鄰近所述內部半導體晶片的所述下表面； 其中所述下部重佈線層的所述第一絕緣層、所述重佈線圖案、所述障壁層及所述第二絕緣層包括階梯式結構。
  12. 如請求項11所述的封裝半導體裝置，其中所述階梯式結構包括圍繞所述下部半導體晶片的至少四個階梯式結構。
  13. 如請求項11所述的封裝半導體裝置，其中所述下部半導體晶片包括： 本體，設置在所述內部半導體晶片的所述下表面上； 焊球，電性連接所述本體與所述內部半導體晶片；及 模製層，在所述本體與所述下部重佈線層之間延伸。
  14. 如請求項13所述的封裝半導體裝置，其中所述模製層的上表面連接所述下部重佈線層的邊緣與所述下部半導體晶片的所述本體的邊緣。
  15. 如請求項13所述的封裝半導體裝置，其中所述模製層的上表面相對於所述內部半導體晶片的所述下表面具有傾斜度。
  16. 如請求項13所述的封裝半導體裝置，其中所述重佈線圖案電性連接至所述內部半導體晶片，且所述障壁層與所述內部半導體晶片電性絕緣。
  17. 如請求項13所述的封裝半導體裝置，其中所述下部半導體晶片的至少一部分與所述下部重佈線層的一部分垂直交疊。
  18. 一種封裝半導體裝置，包括： 框架，具有空腔； 內部半導體晶片，在所述框架的所述空腔內； 下部重佈線層，在所述內部半導體晶片及所述框架的下表面上延伸；以及 下部半導體晶片，在所述內部半導體晶片的所述下表面的至少一部分上延伸， 其中所述下部重佈線層具有在其中至少部分地暴露出所述內部半導體晶片的所述下表面的開口， 其中所述下部半導體晶片在所述開口內延伸， 其中所述下部重佈線層包括： 第一絕緣層，覆蓋所述框架的所述下表面； 重佈線圖案，設置在所述第一絕緣層上； 障壁層，設置在所述第一絕緣層上；以及 第二絕緣層，設置在所述障壁層上， 其中所述下部半導體晶片包括： 本體，設置在所述內部半導體晶片的所述下表面上； 焊球，電性連接所述本體與所述內部半導體晶片；以及 模製層，夾置在所述本體與所述下部重佈線層之間， 其中當在俯視圖中觀察時，所述障壁層圍繞所述下部半導體晶片，且 其中所述障壁層的上表面的一部分接觸所述模製層。
  19. 如請求項18所述的封裝半導體裝置，其中當自俯視平面圖角度觀察時，所述本體的側表面與所述障壁層的內側表面之間的最大水平距離小於所述本體的所述側表面與所述第二絕緣層的內側表面之間的最小水平距離。
  20. 如請求項18所述的封裝半導體裝置，其中所述第一絕緣層包含感光成像介電質（PID），且其中所述障壁層包含銅。
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