TW202238878A - 封裝結構及其製作方法 - Google Patents
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- TW202238878A TW202238878A TW110131749A TW110131749A TW202238878A TW 202238878 A TW202238878 A TW 202238878A TW 110131749 A TW110131749 A TW 110131749A TW 110131749 A TW110131749 A TW 110131749A TW 202238878 A TW202238878 A TW 202238878A
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- 238000004519 manufacturing process Methods 0.000 title description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 197
- 239000000463 material Substances 0.000 claims abstract description 115
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 230000017525 heat dissipation Effects 0.000 claims abstract description 63
- 238000005538 encapsulation Methods 0.000 claims description 19
- 238000004806 packaging method and process Methods 0.000 claims description 14
- 238000005192 partition Methods 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 description 32
- 230000008569 process Effects 0.000 description 29
- 238000001465 metallisation Methods 0.000 description 21
- 229910052802 copper Inorganic materials 0.000 description 15
- 239000010949 copper Substances 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 238000013461 design Methods 0.000 description 12
- 101001046426 Homo sapiens cGMP-dependent protein kinase 1 Proteins 0.000 description 11
- 102100022422 cGMP-dependent protein kinase 1 Human genes 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 101001046427 Homo sapiens cGMP-dependent protein kinase 2 Proteins 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 102100022421 cGMP-dependent protein kinase 2 Human genes 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000011231 conductive filler Substances 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 241000724291 Tobacco streak virus Species 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000004927 clay Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 150000002484 inorganic compounds Chemical class 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
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Abstract
一種封裝結構包括線路基底、半導體封裝、熱介面材料、蓋結構及散熱結構。所述半導體封裝設置在所述線路基底上且電性連接到所述線路基底。所述熱介面材料設置在所述半導體封裝上。所述蓋結構設置在所述線路基底上且環繞所述半導體封裝,其中所述蓋結構包括局部地覆蓋所述熱介面材料且與所述熱介面材料物理接觸的支撐部。所述散熱結構設置在所述蓋結構上且與所述蓋結構的所述支撐部物理接觸。
Description
在各種電子應用(例如,手機及其他移動電子設備)中使用的半導體元件及積體電路通常製造在單個半導體晶圓上。晶圓的晶粒可與其他半導體器件或晶粒一起以晶圓層級進行處理及封裝,且已經開發出用於晶圓層級封裝的各種技術。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。下文闡述元件及排列的具體實例以簡化本公開。當然,這些僅是實例且不旨在進行限制。舉例來說,在以下說明中,在第一特徵之上或在第一特徵上形成第二特徵可包括其中第二特徵與第一特徵被形成為直接接觸的實施例,且還可包括其中在第二特徵與第一特徵之間可形成附加特徵、進而使得所述第二特徵與所述第一特徵可能不直接接觸的實施例。另外,本公開可在各種實例中重複使用元件符號和/或字母。此種重複使用是出於簡單及清晰的目的,且自身並不指示所論述的各種實施例和/或配置之間的關係。
此外,為易於說明,本文中可能使用例如“在……下面(beneath)”、“在……下方(below)”、“下部的(lower)”、“上(on)”、“之上(over)”、“上覆在……之上(overlying)”、“在……上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示出的一個元件或特徵與另一(其他)元件或特徵的關係。除圖中所繪示的取向以外,所述空間相對性用語還旨在囊括器件在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或處於其他取向),且本文中所使用的空間相對性闡述語可同樣相應地進行解釋。
在當前的應用中,一些封裝被設計成具有直接貼合到半導體封裝的散熱結構(例如,散熱器(heat sink))。然而,散熱結構的存在可能引起施加到半導體封裝的巨大的力或應力,從而導致對封裝結構的損壞並導致可靠性問題。在本公開的一些實施例中,封裝中的蓋結構的設計被修改並用於支撐散熱結構。施放在半導體封裝上的應力可減小,同時封裝結構的翹曲(warpage)也可被適當地控制。
圖1A到圖1I是根據本公開一些示例性實施例的製作半導體封裝的方法中的各種階段的示意性俯視圖及剖視圖。參照圖1A,提供中介層結構100。在一些實施例中,中介層結構100包括核心部分102以及形成在其中的多個穿孔104及導電焊盤106。在一些實施例中,核心部分102是例如塊狀半導體基底、絕緣體上矽(silicon on insulator,SOI)基底或多層式半導體材料基底等基底。基底(核心部分102)的半導體材料可為矽、鍺、矽鍺、碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦、銻化銦、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其組合。在一些實施例中,核心部分102是經摻雜的或未經摻雜的。
在一些實施例中,在核心部分102的第一表面102a上形成導電焊盤106。在一些實施例中,在核心部分102中形成穿孔104,且將穿孔104與導電焊盤106連接。在一些實施例中,穿孔104以特定深度延伸到核心部分102中。在一些實施例中,穿孔104是基底穿孔。在一些實施例中,當核心部分102是矽基底時,穿孔104是矽穿孔。在一些實施例中,通過在核心部分102中形成孔或凹槽,且接著利用導電材料填充凹槽來形成穿孔104。在一些實施例中,通過例如蝕刻、銑削、雷射鑽孔或類似製程來形成凹槽。在一些實施例中,通過電化學鍍覆製程、化學氣相沉積(chemical vapor deposition,CVD)、原子層沉積(atomic layer deposition,ALD)或物理氣相沉積(physical vapor deposition,PVD)來形成導電材料,且導電材料可包括銅、鎢、鋁、銀、金或其組合。在一些實施例中,將與穿孔104連接的導電焊盤106形成為在中介層結構100上形成的重佈線層的導電部。在一些實施例中,導電焊盤106包括凸塊下金屬(under bump metallurgy,UBM)。在某些實施例中,中介層結構100可進一步包括主動元件或被動元件,例如形成在核心部分102中的電晶體、電容器、電阻器或二極體被動元件。
如圖1A中所示,核心部分102具有多個封裝區PKR及將所述多個封裝區PKR中的每一者分開的切割道(dicing lane)DL。在封裝區PKR內的核心部分102中形成穿孔104及導電焊盤106。在一些實施例中,在中介層結構100上或在封裝區PKR內的核心部分102上設置多個半導體晶粒21(第一半導體晶粒)及多個半導體晶粒22(第二半導體晶粒)。半導體晶粒21及半導體晶粒22是從晶圓單體化而成的各別晶粒。在一些實施例中,半導體晶粒21包含相同的電路系統(例如器件及金屬化圖案),或者半導體晶粒21是相同類型的晶粒。在一些實施例中,半導體晶粒22包含相同的電路系統,或者半導體晶粒22是相同類型的晶粒。在某些實施例中,半導體晶粒21及半導體晶粒22具有不同的電路系統或者是不同類型的晶粒。在一些實施例中,半導體晶粒21與半導體晶粒22可具有相同的電路系統。
在一些實施例中,半導體晶粒21是主晶粒(major die),而半導體晶粒22是分支晶粒(tributary die)。如圖1B中所示,在每一封裝區PKR中在中介層結構100的中心區100A中的核心部分102上佈置主晶粒(半導體晶粒21)。在中介層結構100的週邊區100B之上設置並且與主晶粒並排且間隔開地佈置分支晶粒(半導體晶粒22)。在一些實施例中,在主晶粒旁邊且圍繞或環繞主晶粒佈置分支晶粒。在一個實施例中,每一個封裝區PKR圍繞主晶粒中的每一者佈置四個、六個或八個分支晶粒。舉例來說,如圖1B中所示,在一個示例性實施例中,四個半導體晶粒22(分支晶粒)環繞每一個封裝區PKR中的每一個半導體晶粒21(主晶粒)。
重新參照圖1A,在一些實施例中,半導體晶粒21具有較半導體晶粒22的表面積大的表面積。此外,在一些實施例中,半導體晶粒21與半導體晶粒22具有不同的大小,包括不同的表面積和/或不同的厚度。在一些實施例中,半導體晶粒21是包括中央處理器(central processing unit,CPU)晶粒、圖形處理單元(graphics processing unit,GPU)晶粒、系統晶片(system-on-a-chip,SoC)晶粒、微控制器或類似物在內的邏輯晶粒。在一些實施例中,半導體晶粒21是例如電源管理積體電路(power management integrated circuit,PMIC)晶粒等電源管理晶粒。在一些實施例中,半導體晶粒22是包括動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(static random access memory,SRAM)晶粒或高頻寬記憶體(high bandwidth memory,HBM)晶粒在內的記憶體晶粒。在一些實施例中,半導體晶粒22是不執行任何電功能的虛設晶粒。本公開不限於此,且設置在核心部分102上的半導體晶粒的數目、大小及類型可基於產品要求適當地調整。
如圖1A中所示,半導體晶粒21包括本體210及形成在本體210的主動表面211上的連接焊盤212。在某些實施例中,連接焊盤212可進一步包括用於將半導體晶粒21結合到其他結構的柱結構。在一些實施例中,半導體晶粒22包括本體220及形成在本體220的主動表面221上的連接焊盤222。在其他實施例中,連接焊盤222可進一步包括用於將晶粒22結合到其他結構的柱結構。
在一些實施例中,例如是借助於電性連接件110通過倒裝晶片結合(flip-chip bonding)的方式將半導體晶粒21及半導體晶粒22貼合到核心部分102的第一表面102a。通過回焊製程(reflow process),在連接焊盤212、222與導電焊盤106之間形成電性連接件110,且電性連接件110將半導體晶粒21、22物理連接到中介層結構100的核心部分102。在一些實施例中,電性連接件110位於半導體晶粒21、22與中介層結構100之間。在某些實施例中,通過電性連接件110將半導體晶粒21、22電性連接到穿孔104及導電焊盤106。在一些實施例中,當半導體晶粒22是虛設晶粒時,可在不與電性連接件110建立電性連接的條件下通過物理連接將半導體晶粒22貼合到電性連接件110。換句話說,半導體晶粒22的連接焊盤222可例如為虛設焊盤。
在一個實施例中,電性連接件110是微凸塊,例如具有銅金屬柱的微凸塊。在另一實施例中,電性連接件110是焊料凸塊、無鉛焊料凸塊或微凸塊,例如受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊或包含銅柱的微凸塊。在一些實施例中,半導體晶粒21、22與核心部分102之間的結合是焊料結合。在一些實施例中,半導體晶粒21、22與核心部分102之間的結合例如是銅對銅結合(copper-to-copper bonding)等直接金屬對金屬的結合。
參照圖1C,在一些實施例中,可形成底部填充結構112以覆蓋所述多個電性連接件110,且填充滿半導體晶粒21、22與中介層結構100之間的空間。在一些實施例中,底部填充結構112進一步覆蓋半導體晶粒21、22的側壁,且位於封裝區PKR內。此後,可在中介層結構100之上(或在核心部分102之上)形成絕緣包封體114(或模制化合物)以覆蓋底部填充結構112並環繞半導體晶粒21及22。
在一些實施例中,在封裝區PKR中的核心部分102的第一表面102a上及在切割道DL之上形成絕緣包封體114。在一些實施例中,通過例如壓縮模制製程(compression molding process)或轉移模制(transfer molding)來形成絕緣包封體114。在一個實施例中,執行固化製程以固化絕緣包封體114。在一些實施例中,通過絕緣包封體114來包封半導體晶粒21、22及電性連接件110。在一些實施例中,執行平坦化製程(包括研磨或拋光)以局部地移除絕緣包封體114,從而暴露出半導體晶粒21、22的背側表面21S、22S。因此,半導體晶粒21、22的背側表面21S、22S與絕緣包封體114的頂表面114a齊平。頂表面114a與絕緣包封體114的背側表面114b相對,其中背側表面114b與核心部分102接觸。在一些實施例中,半導體晶粒21、22的背側表面21S、22S不從絕緣包封體114暴露出,且由絕緣包封體114很好地保護起來。
在一些實施例中,絕緣包封體114的材料包括聚合物(例如環氧樹脂、酚醛樹脂、含矽樹脂或其他適合的樹脂)、具有低介電係數(Dk)及低損耗角正切(Df)性質的介電材料或其他合適的材料。在另一實施例中,絕緣包封體114可包含可接受的絕緣包封材料。在一些實施例中,絕緣包封體114可進一步包含可被添加到其中以優化絕緣包封體114的熱膨脹係數(coefficient of thermal expansion,CTE)的無機填料或無機化合物(例如,二氧化矽、黏土等等)。本公開不限於此。
參照圖1D,將圖1C所示的結構上下顛倒或翻轉,並放置在載體Cx上,以使得載體Cx直接接觸半導體晶粒21、22的背側表面21S、22S及絕緣包封體114的頂表面114a。如圖1D中所示,在此處理階段處,中介層結構100尚未薄化且具有厚度Tx。換句話說,穿孔104不被顯露出,且被嵌置在中介層結構100的核心部分102中。
參照圖1E,對中介層結構100執行薄化製程,以局部地移除或薄化中介層結構100的核心部分102,直到穿孔104被暴露出且核心部分102的第二表面102b被形成為止。在一些實施例中,薄化製程可包括背面研磨製程、拋光製程或蝕刻製程。在一些實施例中,在薄化製程之後,將中介層結構100薄化至厚度Ty。在一些實施例中,厚度Ty對厚度Tx的比率的範圍介於約0.1至約0.5。
參照圖1F,在封裝區PKR中的核心部分102的第二表面102b上且在切割道DL之上形成重佈線結構116。第二表面102b與核心部分102的第一表面102a相對。在一些實施例中,重佈線結構116、核心部分102、穿孔104及導電焊盤106構成中介層結構100’。在一些實施例中,重佈線結構116對穿孔104進行電性連接和/或對穿孔104與外部器件進行電性連接。在某些實施例中,重佈線結構116包括至少一個介電層116a及位於介電層116a中的金屬化圖案116b。在一些實施例中,金屬化圖案116b可包括焊盤、通孔和/或跡線,以對穿孔104進行內連,並進一步將穿孔104連接到一個或多個外部器件。儘管在圖1F中示出一層介電層116a及一層金屬化圖案116b,然而應注意,介電層116a及金屬化圖案116b的層數不限於此,且此可基於要求來進行調整。
在一些實施例中,介電層116a的材料包括氧化矽、氮化矽、碳化矽、氮氧化矽或低介電常數(low-K)介電材料(例如磷矽酸鹽玻璃(phosphosilicate glass,PSG)材料、氟矽酸鹽玻璃材料、硼磷矽酸鹽玻璃材料、SiOC、旋塗玻璃材料、旋塗聚合物或矽碳材料)。在一些實施例中,通過旋轉塗布(spin-coating)或包括化學氣相沉積(CVD)、等離子體增強型化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、高密度等離子體化學氣相沉積(high density plasma-CVD,HDP-CVD)或類似製程在內的沉積來形成介電層116a。在一些實施例中,金屬化圖案116b包括凸塊下金屬(UBM)。在一些實施例中,金屬化圖案116b的形成可包括使用微影技術以及一個或多個蝕刻製程來圖案化介電層以及將金屬材料填充到經圖案化的介電層的開口中。例如,可使用化學機械拋光製程移除介電層上的任何過量的導電材料。在一些實施例中,金屬化圖案116b的材料包括銅、鋁、鎢、銀及其組合。
在圖1F中進一步示出,在金屬化圖案116b上設置多個導電端子118,並將所述多個導電端子118電耦合到穿孔104。在一些實施例中,將導電端子118放置在重佈線結構116的頂表面116s上,並在封裝區PKR內通過金屬化圖案116b電性連接到穿孔104。在某些實施例中,將導電端子118定位在金屬化圖案116b上且物理貼合到金屬化圖案116b。在一些實施例中,導電端子118包括無鉛焊球、焊球、球柵陣列(ball grid array,BGA)球、凸塊、C4凸塊或微凸塊。在一些實施例中,導電端子118可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫或其組合等導電材料。在一些實施例中,通過透過例如蒸鍍、電鍍、印刷或焊料轉移在重佈線結構116上形成焊料膏且然後回焊成所期望凸塊形狀來形成導電端子118。在一些實施例中,通過植球(ball placement)或類似製程將導電端子118放置在重佈線結構116上。在其他實施例中,通過透過濺鍍、印刷、無電鍍覆或電鍍或者CVD形成無焊料金屬柱(例如銅柱)且然後透過在金屬柱上鍍覆形成無鉛頂蓋層來形成導電端子118。導電端子118可用於結合到外部器件或附加的電元件。在一些實施例中,導電端子118用於結合到線路基底、半導體基底或封裝基底。
參照圖1G,在隨後的步驟中,剝離載體Cx。舉例來說,剝離製程包括將例如雷射或紫外(ultra-violet,UV)光等光投射在貼合到載體Cx(未示出)的剝離層(例如,光熱轉換釋放層(light-to-heat-conversion release layer))上,以使得可容易地將載體Cx與剝離層一起移除。在一些實施例中,半導體晶粒21、22的背側表面21S、22S在剝離製程之後顯露出。
參照圖1H,在剝離載體Cx之後,將圖1G中所示結構貼合到由框架FR支撐的膠帶TP上(例如,切割膠帶(dicing tape))。隨後,沿切割道DL對圖1G中所示結構進行切割或單體化,以形成多個半導體封裝SM。舉例來說,執行切割製程以切削穿過重佈線結構116、核心部分102及絕緣包封體114,以沿切割道DL移除重佈線結構116、核心部分102及絕緣包封體114的部分。在一些實施例中,切割製程或單體化製程通常涉及利用旋轉刀片或雷射光束進行切割。換句話說,切割或單體化製程是例如雷射切削製程、機械鋸切製程或其他適合的製程。在剝離載體Cx之後,可獲得圖1I中所示的經單體化的半導體封裝SM。
圖2是根據本公開一些其他示例性實施例的半導體封裝的示意性剖視圖。圖2中所示半導體封裝SM2相似於圖1I中所示半導體封裝SM。因此,相同元件符號可用於表示相同或類似的元件,且本文將不再予以贅述。實施例之間的不同在於,圖1I中所示中介層結構100’被圖2中所示重佈線層RDL替換。如圖2中所示,重佈線層RDL設置在絕緣包封體114上,並通過電性連接件110電性連接到半導體晶粒21、22。
在一些實施例中,重佈線層RDL是通過交替地依序形成一個或多個介電層101A以及一個或多個導電層101B來形成。在某些實施例中,導電層101B夾在介電層101A之間,且電性連接到及物理連接到電性連接件110。在示例性實施例中,包括在重佈線層RDL中的介電層101A及導電層101B的數目不限於此,且可基於設計要求來指定及選擇。舉例來說,介電層101A及導電層101B的數目可為一個或多於一個。
在一些實施例中,介電層101A的材料是可使用微影和/或蝕刻製程來圖案化的聚醯亞胺、聚苯並噁唑(polybenzoxazole,PBO)、苯並環丁烯(benzocyclobutene,BCB)、氮化物(例如氮化矽)、氧化物(例如氧化矽)、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)、其組合或類似物。在一些實施例中,介電層DI1的材料是通過例如旋轉塗布、化學氣相沉積(CVD)、等離子體增強型化學氣相沉積(PECVD)或類似製程等適合的製作技術來形成。本公開不限於此。
在一些實施例中,導電層101B的材料由可使用微影及蝕刻製程來圖案化的例如鋁、鈦、銅、鎳、鎢和/或其合金等通過電鍍或沉積形成的導電材料製成。在一些實施例中,導電層101B可為經圖案化銅層或者其他適合的經圖案化金屬層。在說明書通篇中,用語“銅”旨在包括實質上純的元素銅、含有不可避免的雜質的銅以及含有少量元素(例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等)的銅合金。
在某些實施例中,重佈線層RDL進一步包括設置在導電層101B上用於與導電端子118電性連接的多個導電焊盤101C。在一些實施例中,導電焊盤101C的材料可包括銅、鎳、鈦、鎢或其合金或者類似物,且可通過例如電鍍製程來形成。導電焊盤101C的數目在本公開中不受限制,且可基於設計佈局來選擇。在一些實施例中,可省略導電焊盤101C。換句話說,在後續步驟中形成的導電端子118可直接設置在重佈線層RDL的導電層101B上。
圖3到圖5B是根據本公開一些示例性實施例的製作封裝結構的方法中的各種階段的示意性俯視圖、剖視圖及三維圖。參照圖3,在一些實施例中,通過導電端子118將圖1I中獲得的半導體封裝SM安裝或貼合到線路基底300上。在一些實施例中,線路基底300包括接觸焊盤310、接觸焊盤320、金屬化層330及通孔(未示出)。在一些實施例中,接觸焊盤310與接觸焊盤320分別分佈在線路基底300的兩個相對的側上,且被暴露出以與稍後形成的元件/特徵電性連接。在一些實施例中,金屬化層330及通孔嵌置在線路基底300中,且一起為線路基底300提供佈線功能,其中金屬化層330及通孔電性連接到接觸焊盤310及接觸焊盤320。換句話說,接觸焊盤310中的至少一些接觸焊盤310通過金屬化層330及通孔電性連接到接觸焊盤320中的一些接觸焊盤320。在一些實施例中,接觸焊盤310及接觸焊盤320可包括金屬焊盤或金屬合金焊盤。在一些實施例中,金屬化層330及通孔的材料可與接觸焊盤310及接觸焊盤320的材料實質上相同或相似。
此外,在一些實施例中,通過對導電端子118與接觸焊盤310進行物理連接將半導體封裝SM結合到線路基底300,以形成堆疊結構。在某些實施例中,將半導體封裝SM電性連接到線路基底300。在一些實施例中,線路基底300是例如有機柔性基底或印刷電路板。在此種實施例中,導電端子118是例如晶片連接件。在一些實施例中,在基底300上分別形成多個導電球340。如圖3中所示,舉例來說,將導電球340連接到線路基底300的接觸焊盤320。換句話說,通過接觸焊盤320將導電球340電性連接到線路基底300。通過接觸焊盤310及接觸焊盤320,導電球340中的一些導電球340電性連接到半導體封裝SM(例如,其中所包括的半導體晶粒21及22)。在一些實施例中,導電球340是例如焊球或BGA球。在一些實施例中,通過透過基底上晶圓上晶片(chip on wafer on substrate,CoWoS)封裝製程對導電端子118與線路基底300的接觸焊盤310進行物理連接來將半導體封裝SM結合到線路基底300。另外,如圖3中所示,可在線路基底300上安裝被動元件PDX(集成被動元件或表面安裝器件)。舉例來說,可通過焊接製程在線路基底300的接觸焊盤310上安裝被動元件PDX。本公開不限於此。在某些實施例中,可在環繞半導體封裝SM的線路基底上安裝被動元件PDX。在一些實施例中,省略了被動元件PDX。
如圖3中進一步所示,在一些實施例中,形成底部填充結構350以填充滿線路基底300與半導體封裝SM之間的空間。在某些實施例中,底部填充結構350填充滿相鄰導電端子118之間的空間並覆蓋導電端子118。舉例來說,底部填充結構350環繞所述多個導電端子118。在一些實施例中,被動元件PDX由底部填充結構350暴露出,且與底部填充結構350保持一定距離。換句話說,底部填充結構350不覆蓋被動元件PDX。
參照圖4A,在隨後的步驟中,在線路基底300上設置蓋結構500。在一些實施例中,在線路基底300上安裝蓋結構500之前,在半導體晶粒21、22的背側表面21S、22S上安裝熱介面材料TX。在一些實施例中,熱介面材料TX可為具有良好導熱率(Tk)的聚合物,所述導熱率可在約3瓦/米開爾文(W/mK)到約5 W/mK之間。在一些實施例中,熱介面材料TX可包括具有導熱填料的聚合物。導熱填料可將熱介面材料TX的有效Tk增加到約10 W/mK到約50 W/mK或大於50 W/mK之間。適用的導熱填料可包括氧化鋁、氮化硼、氮化鋁、鋁、銅、銀、銦、其組合或類似物。在其他實施例中,熱介面材料TX可包括其他材料,例如包括銀、銦膏或類似物在內的金屬系或焊料系材料。
如圖4A中所示,通過黏合材料AX將蓋結構500貼合到線路基底300。在一些實施例中,蓋結構500包括側壁部510及支撐部520。舉例來說,側壁部510設置在線路基底300上並通過黏合材料AX貼合到線路基底300,且環繞半導體封裝SM。此外,支撐部520設置在側壁部510上且與側壁部510物理接觸。在一些實施例中,支撐部520包括第一部分520A及第二部分520B。第一部分520A與熱介面材料TX物理接觸,且與半導體封裝SM交疊。第二部分520B在與被動元件PDX交疊的同時不與半導體封裝SM交疊。
如圖4A中所示,且從圖4B中所示蓋結構500的三維圖來看,蓋結構500包括第一開口OP1。舉例來說,蓋結構500的支撐部520包括第一開口OP1。在一些實施例中,第一開口OP1顯露出熱介面材料TX的部分。換句話說,熱介面材料TX1被第一開口OP1局部地暴露出來,但同時由蓋結構500局部地覆蓋。在某些實施例中,第一開口OP1在與所述多個第二半導體晶粒22不交疊的同時與所述多個第一半導體晶粒21交疊。如圖4C(其為圖4A中所示蓋結構500的俯視圖)中進一步所示,第一開口OP1包括為WC1的寬度及為LC1的長度。在一些實施例中,寬度WC1及長度LC1實質上對應於位在中介層結構100’的中心區100A(在圖1B中示出)之上的所述兩個第一半導體晶粒21的寬度之總和及長度之總和。寬度WC1及長度LC1的尺寸可依據所使用的第一半導體晶粒21的大小而變化,且並無特別限制。換句話說,第一開口OP1的面積實質上對應於由第一半導體晶粒21所佔用的面積。在示例性實施例中,第一開口OP1的面積實質上對應於由第一半導體晶粒21所佔用的面積,以使得可獲得封裝結構的應力減輕效果與散熱效果之間的合適平衡。
參照圖5A,在隨後的步驟中,在蓋結構500上設置散熱結構600。舉例來說,散熱結構600設置在蓋結構500上,且與蓋結構500的支撐部520物理接觸。在一些實施例中,散熱結構600是包括多個鰭結構610、鰭基底620、台階結構630及突出部分640的散熱器。鰭基底620支撐所述多個鰭結構610。在一些實施例中,鰭結構610均勻地分佈在鰭基底620的表面之上。此外,台階結構630支撐鰭基底620,且突出部分640設置在台階結構630上。在一些實施例中,突出部分640延伸並填充到蓋結構500的第一開口OP1中,且與熱介面材料TX物理接觸。在某些實施例中,突出部分640由蓋結構500的支撐部520環繞。
如圖5A中所示,且如圖5B中的散熱結構600的三維圖中所示,台階結構630的寬度小於鰭基底620的寬度,且突出部分640的寬度小於台階結構630的寬度。在一些實施例中,台階結構630的佔用體積小於鰭基底620的佔用體積,且突出部分640的佔用體積小於台階結構630的佔用體積。在一些實施例中,突出部分640具有為WN的寬度及為LN的長度。舉例來說,突出部分640的寬度WN及長度LN實質上對應於第一開口OP1的寬度WC1及長度LC1。換句話說,突出部分640的頂表面的面積實質上對應於由第一半導體晶粒21在中介層結構100’的中心區100A(在圖1B中示出)之上所佔用的面積。在另一實施例中,突出部分640的尺寸(長度及寬度)略微小於第一開口OP1的尺寸(長度及寬度),以使得突出部分640可容易地設置在第一開口OP1內。舉例來說,突出部分640的尺寸(長度及寬度)對第一開口OP1的尺寸(長度及寬度)的比率可在0.9:1到0.99:1的範圍內。在一些其他實施例中,可選地,可使用黏合劑(或熱膠帶)來將散熱結構600貼合到蓋結構500上。
在一些實施例中,鰭結構610具有為H1的高度,鰭基底620具有為H2的高度,台階結構630具有為H3的高度,且突出部分640具有為H4的高度。在一些實施例中,高度H2、H3、H4小於高度H1。在某些實施例中,高度H2實質上等於高度H3及H4,但本公開不限於此。在一些實施例中,可適當地調整高度H2、H3、H4,只要其小於高度H1即可。在一些實施例中,突出部分640的高度H4實質上等於蓋結構500的支撐部520的厚度500H。換句話說,突出部分640的高度H4可依據支撐部520的設計而變化。此外,在一些實施例中,熱介面材料TX的厚度TH小於高度H1~H4,且小於支撐部520的厚度500H。
在蓋結構500之上設置散熱結構600之後,實現了根據本公開的一些實施例的封裝結構PKG1。在圖5A中所示封裝結構PKG1中,蓋結構500的支撐部520提供增強的支撐,以減小在半導體封裝SM及線路基底300上實施的應力。因此,在封裝上引起的應力或力可減輕,同時封裝結構PKG1的翹曲也可被適當地控制。
圖6到圖8B是根據本公開一些示例性實施例的製作封裝結構的方法中的各種階段的示意性俯視圖、剖視圖及三維圖。制作圖6到圖8B中所示封裝結構的方法相似於制作圖1A到圖1I及圖3到圖5B中所示封裝結構的方法。因此,相同的元件符號將用於表示相同或類似的元件,且於本文中將不再予以贅述。
圖6是相似於圖1B中所示階段的製造封裝結構的階段。實施例之間的不同在於,存在更多設置在中介層結構100上的半導體晶粒21(第一半導體晶粒)。舉例來說,如圖6中所示,在中介層結構100的中心區100A中在核心部分102上佈置四個半導體晶粒21,同時在週邊區100B中在所述四個半導體晶粒21旁邊佈置八個半導體晶粒22。
參照圖7A,在中介層結構100上設置半導體晶粒21及22之後,可重複進行圖1C到圖1I中所示步驟以形成半導體封裝SM’。此後,可以圖3中所述的相似方式將所獲得的半導體封裝SM’安裝或貼合到線路基底300上。在一些實施例中,熱介面材料TX安裝在半導體晶粒21、22的背側表面21S、22S上,同時蓋結構500安裝在線路基底300上以局部地覆蓋熱介面材料TX。
在示例性實施例中,蓋結構500包括側壁部510、支撐部520及多個分割部530。側壁部510及支撐部520的細節已參照圖4A進行了闡述,因此本文中將不再重複。在一些實施例中,參照圖7A,且如圖7B中所示的三維圖及圖7C中所示的俯視圖中所示,蓋結構500的分割部530在第一開口OP1中界定多個子開口OPS1。舉例來說,分割部530與支撐部520的第一部分520A連結,以界定所述多個子開口OPS1。在一些實施例中,第一開口OP1通過分割部530分割成四個子開口OPS1。在某些實施例中,所述多個子開口OPS1的尺寸對應於半導體晶粒21的尺寸。換句話說,子開口OPS1中的每一者的長度及寬度實質上對應於位於下方的半導體晶粒21中的每一者的長度及寬度。
參照圖8A,在隨後的步驟中,在蓋結構500上設置散熱結構600。舉例來說,散熱結構600設置在蓋結構500上,且與蓋結構500的支撐部520物理接觸。如圖8A中所示,且如圖8B中散熱結構600的三維圖中所示,散熱結構600是包括相似於以上在圖5A中所述的鰭結構610、鰭基底620、台階結構630及突出部分640的散熱器。在示例性實施例中,散熱結構600的突出部分640填充到子開口OPS1中的每一者中。舉例來說,突出部分640進一步包括填充到子開口OPS1中的每一者中以接觸熱介面材料TX的多個突出子部分640X。突出子部分640X通過分割部530彼此分開。在某些實施例中,突出子部分640X 中的每一者的面積實質上對應於由半導體晶粒21中的每一者在中介層結構100’的中心區100A(在圖1B中示出)之上所佔用的面積。
在蓋結構500之上設置散熱結構600之後,實現了根據本公開的一些實施例的封裝結構PKG2。在圖8A中所示封裝結構PKG2中,蓋結構500的支撐部520及分割部530提供增強的支撐,以減小實施在半導體封裝SM’及線路基底300上的應力。因此,在封裝上引起的應力或力可減輕,同時封裝結構PKG2的翹曲也可被適當地控制。
圖9A到圖10B是根據本公開一些示例性實施例的製作封裝結構的方法中的各種階段的示意性剖視圖及三維圖。制作圖9到圖10B中所示封裝結構的方法相似於制作圖1A到圖1I及圖3到圖5B中所示封裝結構的方法。因此,相同的元件符號將用於表示相同或類似的元件,且於本文中將不再予以贅述。
參照圖9A,在一些實施例中,重複進行圖1A到圖1I中所示步驟以形成半導體封裝SM,由此將所獲得的半導體封裝SM被安裝或貼合到線路基底300上。在一些實施例中,熱介面材料TX安裝在半導體晶粒21、22的背側表面21S、22S上,同時蓋結構500安裝在線路基底300上以局部地覆蓋熱介面材料TX。
在示例性實施例中,蓋結構500包括側壁部510、支撐部520及支撐條540。側壁部510及支撐部520的細節已參照圖4A進行了闡述,因此本文中將不再予以贅述。在一些實施例中,參照圖9A,且如圖9B中所示三維圖中所示,支撐條540設置在支撐部520上並從支撐部520突出出來。舉例來說,支撐條540的內側壁與支撐部520的內側壁對準。在某些實施例中,第一開口OP1由支撐部520及支撐條540的側壁界定。
參照圖10A,在隨後的步驟中,在蓋結構500上設置散熱結構600。舉例來說,散熱結構600設置在蓋結構500上並填充到第一開口OP1中。在一些實施例中,散熱結構600與蓋結構500的支撐部520及支撐條540物理接觸。如圖10A中所示,且如圖10B中散熱結構600的三維圖中所示,散熱結構600是包括如以上在圖5A中所述的鰭結構610、鰭基底620、台階結構630及突出部分640的散熱器。在示例性實施例中,散熱結構600進一步包括環繞突出部分640的下凹部分600-CV。舉例來說,蓋結構500的支撐條540朝下凹部分600-CV突出,並填充到下凹部分600-CV中以環繞散熱結構600的突出部分640。在某些實施例中,台階結構630進一步環繞蓋結構500的支撐條540。
在蓋結構500之上設置散熱結構600之後,實現了根據本公開的一些實施例的封裝結構PKG3。在圖10A中所示封裝結構PKG3中,蓋結構500的支撐部520及支撐條540提供增強的支撐,以減小實施在半導體封裝SM及線路基底300上的應力。因此,在封裝上引起的應力或力可減輕,同時封裝結構PKG3的翹曲也可被適當地控制。
圖11是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。圖11中所示封裝結構PKG4相似於圖10A中所示封裝結構PKG3。因此,相同的元件符號將用於表示相同或類似的元件,且於本文中將不再予以贅述。實施例之間的不同在於,圖11所示蓋結構500包括側壁部510、支撐部520、分割部530及支撐條540。
舉例來說,參照圖11中所示封裝結構PKG4,蓋結構500設置在線路基底300上以環繞半導體封裝SM’並局部地覆蓋熱介面材料TX。在一些實施例中,蓋結構500的分割部530在第一開口OP1中界定多個子開口OPS1(相似於圖7B中所示的情況)。此外,支撐條540設置在支撐部520上並從支撐部520突出出來。在一些實施例中,圖11所示散熱結構600進一步包括環繞突出部分640的下凹部分600-CV。舉例來說,蓋結構500的支撐條540朝下凹部分600-CV突出,並填充到下凹部分600-CV中以環繞散熱結構600的突出部分640。此外,散熱結構600的突出部分640進一步包括多個突出子部分640X,所述多個突出子部分640X填充到子開口OPS1中的每一者中以接觸熱介面材料TX。
在蓋結構500之上設置散熱結構600之後,實現了根據本公開的一些實施例的封裝結構PKG4。在圖11中所示封裝結構PKG4中,蓋結構500的支撐部520、分割部530及支撐條540提供進一步增強的支撐,以減小實施在半導體封裝SM及線路基底300上的應力。因此,在封裝上引起的應力或力可減輕,同時封裝結構PKG4的翹曲也可被適當地控制。
圖12A是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。圖12B是圖12A所示封裝結構中的熱介面材料的俯視圖。圖12A中所示封裝結構PKG5相似於圖5A中所示封裝結構PKG1。因此,相同的元件符號將用於表示相同或類似的部分,且於本文中將不再予以贅述。實施例之間的不同在於,圖12A及圖12B所示熱介面材料TX進一步包括第一熱介面材料TX-1及第二熱介面材料TX-2。
如圖12A中所示,且從圖12B中所示俯視圖來看,熱介面材料TX包括覆蓋半導體晶粒21的第一熱介面材料TX-1及覆蓋半導體晶粒22的第二熱介面材料TX-2。舉例來說,第一熱介面材料TX-1與半導體晶粒21以及散熱結構600的突出部分640物理接觸。此外,第二熱介面材料TX-2與第二半導體晶粒22以及蓋結構500的支撐部520(第一部分520A)物理接觸。在一些實施例中,第一熱介面材料TX-1的熱傳導係數大於第二熱介面材料TX-2的熱傳導係數。舉例來說,第一熱介面材料TX-1具有大於20 W/mK的熱傳導係數,且第二熱介面材料TX-2具有大於3 W/mK且小於20 W/mk的熱傳導係數。在某些實施例中,第二熱介面材料TX-2環繞第一熱介面材料TX-1。在一些實施例中,蓋結構500的第一開口OP1的尺寸實質上對應於第一熱介面材料TX-1的尺寸。換句話說,第一開口OP1顯露出第一熱介面材料TX-1,且不顯露出第二熱介面材料TX-2。
相似於以上實施例,在圖12A中所示封裝結構PKG5中,蓋結構500的支撐部520提供增強的支撐,以減小實施在半導體封裝SM及線路基底300上的應力。因此,在封裝上引起的應力或力可減輕,同時封裝結構PKG5的翹曲也可被適當地控制。此外,使用第一熱介面材料TX-1(熱傳導係數< 20 W/mK)來選擇性地覆蓋半導體晶粒21會為半導體晶粒21(邏輯晶粒)提供更好的散熱效果。
圖13A是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。圖13B是圖13A所示封裝結構中的熱介面材料的俯視圖。圖13A中所示封裝結構PKG6相似於圖8A中所示封裝結構PKG2。因此,相同的元件符號將用於表示相同或類似的元件,且於本文中將不再予以贅述。實施例之間的不同在於,圖13A及圖13B的熱介面材料TX進一步包括第一熱介面材料TX-1及第二熱介面材料TX-2。
如圖13A中所示,且從圖13B中所示俯視圖來看,熱介面材料TX包括覆蓋半導體晶粒21的第一熱介面材料TX-1及覆蓋半導體晶粒22且環繞第一熱介面材料TX-1的第二熱介面材料TX-2。在示例性實施例中,蓋結構500包括界定子開口OPS1的多個分割部530。在一些實施例中,第一熱介面材料TX-1包括對應於子開口OPS1的多個第一熱介面材料區段TX-1A。換句話說,第一熱介面材料區段TX-1A中的每一者的尺寸實質上對應於子開口OPS1中的每一者的尺寸。在某些實施例中,第一熱介面材料區段TX-1A的長度及寬度實質上對應於位於下方的半導體晶粒21中的每一者的長度及寬度。在一些實施例中,第一熱介面材料TX-1與半導體晶粒21以及散熱結構600的突出部分640(突出子部分640X)物理接觸。此外,第二熱介面材料TX-2與第二半導體晶粒22、蓋結構500的支撐部520(第一部分520A)及分割部530物理接觸。
與以上實施例相似,在圖13A中所示封裝結構PKG6中,蓋結構500的支撐部520、分割部530及支撐條540提供進一步增強的支撐,以減小實施在半導體封裝SM’及線路基底300上的應力。因此,在封裝上引起的應力或力可減輕,同時封裝結構PKG6的翹曲也可被適當地控制。此外,使用第一熱介面材料TX-1(熱傳導係數< 20 W/mK)來選擇性地覆蓋半導體晶粒21會為半導體晶粒21(邏輯晶粒)提供更好的散熱效果。
圖14是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。圖15A到圖15B是根據圖14所示封裝結構的蓋結構的各種設計的示意性俯視圖。圖14中所示封裝結構PKG7相似於圖5A中所示封裝結構PKG1。因此,相同的元件符號用於表示相同或類似的部件。實施例之間的不同在於蓋結構500的設計。在圖5A所示封裝結構PKG1中,第一開口OP1的面積實質上對應於由第一半導體晶粒21所佔用的面積。然而,本公開不限於此。舉例來說,如圖14所示封裝結構PKG7中所示,第一開口OP1的面積大於由第一半導體晶粒21所佔用的面積。
參照圖15A及圖15B,在其中第一開口OP1的面積大於由第一半導體晶粒21所佔用的面積的實施例中,蓋結構500可被設計成使得寬度WC1和/或長度LC1可分別大於位於下方的所述兩個第一半導體晶粒21的寬度之總和及長度之總和。在一些實施例中,第一開口OP1被設計成具有矩形形狀(圖15A),但本公開不限於此。在一些實施例中,第一開口OP1被設計成具有橢圓形狀(圖15B),由此蓋結構的支撐部520具有彎曲側壁以界定第一開口OP1。換句話說,第一開口OP1的設計可被適當地調整,只要蓋結構500仍然包括支撐部520以減小實施在半導體封裝SM上的應力即可。
相似於以上實施例,在圖14中所示封裝結構PKG7中,支撐部520提供增強的支撐,以減小實施在半導體封裝SM及線路基底300上的應力。因此,在封裝上引起的應力或力可減輕,同時封裝結構PKG7的翹曲也可被適當地控制。然而,如與具有較小第一開口OP1的封裝結構PKG1相比,封裝結構PKG7的較大第一開口OP1可維持散熱效果,但應力減輕效果可能會略微降低。
圖16是根據本公開一些示例性實施例的蓋結構的另一種設計的示意性俯視圖。圖16中所示蓋結構500相似於圖15A及圖15B中所示蓋結構500。因此,相同的元件符號將用於表示相同或類似的元件,且於本文中將不再予以贅述。在先前的實施例中,蓋結構500被設計成使得第一開口OP1的面積實質上對應於或大於由第一半導體晶粒21所佔用的面積。然而,本公開不限於此。舉例來說,如圖16的蓋結構500中所示,第一開口OP1的面積是小於由第一半導體晶粒21所佔用的面積。
與以上實施例相似,圖16所示蓋結構500提供增強的支撐,以減小實施在半導體封裝SM及線路基底300上的應力。因此,在封裝上引起的應力或力可減輕,同時封裝結構的翹曲也可被適當地控制。然而,與具有擁有較大第一開口OP1的蓋結構500的封裝結構PKG1相比,蓋結構500的較小第一開口OP1可維持應力減輕效果,但散熱效果可能會略微降低。
圖17是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。圖17中所示封裝結構PKG8相似於圖5A中所示封裝結構PKG1。因此,相同的元件符號將用於表示相同或類似的元件,且於本文中將不再予以贅述。實施例之間的不同在於,圖2中的半導體封裝SM2用於替換圖5A中的半導體封裝SM。半導體封裝SM2的細節可參照圖2的說明,因此本文中將不再予以贅述。在先前的實施例中,作為實例,蓋結構500及散熱結構600的各種設計被應用於半導體封裝SM/SM’。然而,本公開不限於此。舉例來說,蓋結構500及散熱結構600的各種設計也可應用並設置在半導體封裝SM2之上,以實現相同的應力減輕效果及散熱效果,同時控制封裝結構的翹曲。
在上述實施例中,封裝結構包括具有局部地覆蓋熱介面材料且與熱介面材料物理接觸的支撐部的蓋結構以及設置在蓋結構的支撐部上的散熱結構。因此,在封裝上引起的應力或力可減輕,同時封裝結構的翹曲也可被適當地控制。綜上所述,封裝結構的可靠性可增強。
根據本公開的一些實施例,一種封裝結構包括線路基底、半導體封裝、熱介面材料、蓋結構以及散熱結構。所述半導體封裝設置在所述線路基底上且電性連接到所述線路基底。所述熱介面材料設置在所述半導體封裝上。所述蓋結構設置在所述線路基底上且環繞所述半導體封裝,其中所述蓋結構包括局部地覆蓋所述熱介面材料且與所述熱介面材料物理接觸的支撐部。所述散熱結構設置在所述蓋結構上且與所述蓋結構的所述支撐部物理接觸。
根據本公開的一些其他實施例,一種封裝結構包括線路基底、中介層結構、多個半導體晶粒、絕緣包封體、蓋結構以及散熱結構。所述中介層結構設置在所述線路基底上且電性連接到所述線路基底。所述半導體晶粒設置在所述中介層結構的第一表面上且電性連接到所述中介層結構。所述絕緣包封體設置在所述中介層結構的所述第一表面上且環繞所述半導體晶粒。所述蓋結構設置在所述線路基底上且環繞所述中介層結構及所述半導體晶粒,其中所述蓋結構包括與所述半導體晶粒局部地交疊的第一開口。所述散熱結構設置在所述蓋結構上,其中所述散熱結構包括填充到所述蓋結構的所述第一開口中的突出部分。
根據本公開的又一實施例,一種封裝結構包括線路基底、中介層結構、多個第一半導體晶粒、多個第二半導體晶粒、蓋結構以及散熱結構。所述中介層結構設置在所述線路基底上。所述第一半導體晶粒設置在所述中介層結構的中心區之上。所述第二半導體晶粒設置在所述中介層結構的週邊區之上,且在所述第一半導體晶粒旁邊。所述蓋結構設置在所述線路基底上且環繞所述中介層結構、所述第一半導體晶粒及所述第二半導體晶粒,其中所述蓋結構包括在顯露出所述中介層結構的所述中心區的同時覆蓋所述週邊區的支撐部。所述散熱結構設置在所述蓋結構上,其中所述散熱結構包括由所述蓋結構的所述支撐部環繞的突出部分,且所述突出部分的頂表面的面積實質上對應於由位於所述中介層結構的所述中心區之上的所述第一半導體晶粒所佔用的面積。
還可包括其他特徵及製程。舉例來說,可包括測試結構來説明對三維(three dimensional,3D)封裝或三維積體電路(3D integrated circuit,3DIC)器件進行驗證測試。測試結構可包括例如形成在重佈線層中或形成在基底上的測試焊盤,所述測試焊盤使得能夠測試3D封裝或3DIC、能夠使用探針和/或探針卡以及進行類似操作。可對中間結構以及最終結構執行驗證測試。另外,本文中所公開的結構及方法可與包括對已知良好晶粒進行中間驗證的測試方法結合使用來提高良率(yield)及降低成本。
前述內容概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本公開的各方面。所屬領域中的技術人員應理解,他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應意識到,此種等效構造並不背離本公開的精神及範圍,且他們可在不背離本公開的精神及範圍的條件下在本文中作出各種改變、取代及變更。
21:第一半導體晶粒/半導體晶粒
21S、22S、114b:背側表面
22:半導體晶粒/第二半導體晶粒/晶粒
100、100’:中介層結構
100A:中心區
100B:週邊區
101A、116a:介電層
101B:導電層
101C、106:導電焊盤
102:核心部分
102a:第一表面
102b:第二表面
104:穿孔
110:電性連接件
112、350:底部填充結構
114:絕緣包封體
114a、116s:頂表面
116:重佈線結構
116b:金屬化圖案
118:導電端子
210、220:本體
211、221:主動表面
212、222:連接焊盤
300:基底/線路基底
310、320:接觸焊盤
330:金屬化層
340:導電球
500:蓋結構
500H、TH、Tx、Ty:厚度
510:側壁部
520:支撐部
520A:第一部分
520B:第二部分
530:分割部
540:支撐條
600:散熱結構
600-CV:下凹部分
610:鰭結構
620:鰭基底
630:台階結構
640:突出部分
640X:突出子部分
AX:黏合材料
Cx:載體
DL:切割道
FR:框架
H1、H2、H3、H4:高度
LC1、LN:長度
OP1:第一開口
OPS1:子開口
PDX:被動元件
PKG1、PKG2、PKG3、PKG4、PKG5、PKG6、PKG7、PKG8:封裝結構
PKR:封裝區
RDL:重佈線層
SM、SM’、SM2:半導體封裝
TP:膠帶
TX:熱介面材料
TX-1A:第一熱介面材料區段
TX-1:第一熱介面材料
TX-2:第二熱介面材料
WC1、WN:寬度
參照附圖閱讀以下詳細說明,會最好地理解本公開的各個方面。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的臨界尺寸。
圖1A到圖1I是根據本公開一些示例性實施例的製作半導體封裝的方法中的各種階段的示意性俯視圖及剖視圖。
圖2是根據本公開一些其他示例性實施例的半導體封裝的示意性剖視圖。
圖3到圖5B是根據本公開一些示例性實施例的製作封裝結構的方法中的各種階段的示意性俯視圖、剖視圖及三維圖。
圖6到圖8B是根據本公開一些示例性實施例的製作封裝結構的方法中的各種階段的示意性俯視圖、剖視圖及三維圖。
圖9A到圖10B是根據本公開一些示例性實施例的製作封裝結構的方法中的各種階段的示意性剖視圖及三維圖。
圖11是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
圖12A是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
圖12B是圖12A所示封裝結構中的熱介面材料的俯視圖。
圖13A是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
圖13B是圖13A所示封裝結構中的熱介面材料的俯視圖。
圖14是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
圖15A到圖15B是根據圖14所示封裝結構的蓋結構的各種設計的示意性俯視圖。
圖16是根據本公開一些示例性實施例的蓋結構的另一種設計的示意性俯視圖。
圖17是根據本公開一些其他示例性實施例的封裝結構的示意性剖視圖。
21:第一半導體晶粒/半導體晶粒
22:半導體晶粒/第二半導體晶粒/晶粒
100’:中介層結構
102:核心部分
104:穿孔
106:導電焊盤
110:電性連接件
112、350:底部填充結構
114:絕緣包封體
116:重佈線結構
116a:介電層
116b:金屬化圖案
118:導電端子
300:基底/線路基底
310、320:接觸焊盤
330:金屬化層
340:導電球
500:蓋結構
500H、TH:厚度
510:側壁部
520:支撐部
520A:第一部分
520B:第二部分
600:散熱結構
610:鰭結構
620:鰭基底
630:台階結構
640:突出部分
AX:黏合材料
H1、H2、H3、H4:高度
OP1:第一開口
PDX:被動元件
PKG1:封裝結構
SM:半導體封裝
TX:熱介面材料
Claims (20)
- 一種封裝結構,包括: 線路基底; 半導體封裝,設置在所述線路基底上且電性連接到所述線路基底; 熱介面材料,設置在所述半導體封裝上; 蓋結構,設置在所述線路基底上且環繞所述半導體封裝,其中所述蓋結構包括局部地覆蓋所述熱介面材料且與所述熱介面材料物理接觸的支撐部;以及 散熱結構,設置在所述蓋結構上且與所述蓋結構的所述支撐部物理接觸。
- 如請求項1所述的封裝結構,其中所述散熱結構是散熱器,所述散熱器包括: 鰭結構; 鰭基底,支撐所述鰭結構; 台階結構,支撐所述鰭基底;以及 突出部分,設置在所述台階結構上,其中所述突出部分與所述熱介面材料物理接觸。
- 如請求項2所述的封裝結構,其中所述突出部分由所述蓋結構的所述支撐部環繞。
- 如請求項2所述的封裝結構,其中所述台階結構的寬度小於所述鰭基底的寬度,且所述突出部分的寬度小於所述台階結構的所述寬度。
- 如請求項1所述的封裝結構,其中所述熱介面材料包括具有大於20 W/mK的熱傳導係數的第一熱介面材料及具有大於3 W/mK且小於20 W/mk的熱傳導係數的第二熱介面材料,且其中所述第二熱介面材料環繞所述第一熱介面材料。
- 如請求項1所述的封裝結構,其中所述蓋結構進一步包括:側壁部,設置在所述線路基底上且環繞所述半導體封裝,且其中所述支撐部設置在所述側壁部上且與所述側壁部物理接觸。
- 如請求項6所述的封裝結構,其中所述蓋結構進一步包括: 支撐條,設置在所述支撐部上且從所述支撐部突出出來,其中所述支撐條環繞所述散熱結構的一部分且與所述散熱結構的所述部分物理接觸。
- 一種封裝結構,包括: 線路基底; 中介層結構,設置在所述線路基底上且電性連接到所述線路基底; 多個半導體晶粒,設置在所述中介層結構的第一表面上且電性連接到所述中介層結構; 絕緣包封體,設置在所述中介層結構的所述第一表面上且環繞所述多個半導體晶粒; 蓋結構,設置在所述線路基底上且環繞所述中介層結構及所述多個半導體晶粒,其中所述蓋結構包括與所述多個半導體晶粒局部地交疊的第一開口;以及 散熱結構,設置在所述蓋結構上,其中所述散熱結構包括填充到所述蓋結構的所述第一開口中的突出部分。
- 如請求項8所述的封裝結構,進一步包括設置在所述多個半導體晶粒與所述散熱結構之間的熱介面材料,其中填充到所述第一開口中的所述突出部分與所述熱介面材料物理接觸。
- 如請求項9所述的封裝結構,其中所述熱介面材料包括具有大於20 W/mK的熱傳導係數的第一熱介面材料及具有大於3 W/mK且小於20 W/mk的熱傳導係數的第二熱介面材料,其中所述第二熱介面材料環繞所述第一熱介面材料,且所述突出部分與所述第一熱介面材料物理接觸。
- 如請求項8所述的封裝結構,其中所述蓋結構進一步包括在所述第一開口中界定多個子開口的多個分割部,且其中所述多個子開口的尺寸對應於所述多個半導體晶粒的尺寸。
- 如請求項8所述的封裝結構,其中所述散熱結構進一步包括環繞所述突出部分的下凹部分,且所述蓋結構進一步包括朝所述下凹部分突出以環繞所述突出部分的支撐條。
- 如請求項8所述的封裝結構,其中所述多個半導體晶粒包括多個第一半導體晶粒及多個第二半導體晶粒,所述第一開口與所述多個第一半導體晶粒交疊且不與所述多個第二半導體晶粒交疊。
- 如請求項13所述的封裝結構,其中所述多個第一半導體晶粒是邏輯晶粒,且所述多個第二半導體晶粒是記憶體晶粒。
- 一種封裝結構,包括: 線路基底; 中介層結構,設置在所述線路基底上; 多個第一半導體晶粒,設置在所述中介層結構的中心區之上; 多個第二半導體晶粒,設置在所述中介層結構的週邊區之上,且在所述多個第一半導體晶粒旁邊; 蓋結構,設置在所述線路基底上且環繞所述中介層結構、所述多個第一半導體晶粒及所述多個第二半導體晶粒,其中所述蓋結構包括在顯露出所述中介層結構的所述中心區的同時覆蓋所述週邊區的支撐部;以及 散熱結構,設置在所述蓋結構上,其中所述散熱結構包括由所述蓋結構的所述支撐部環繞的突出部分,且所述突出部分的頂表面的面積實質上對應於由位於所述中介層結構的所述中心區之上的所述多個第一半導體晶粒所佔用的面積。
- 如請求項15所述的封裝結構,其中所述散熱結構是散熱器,所述散熱器包括: 鰭結構; 鰭基底,支撐所述鰭結構; 台階結構,支撐所述鰭基底;以及 所述突出部分,設置在所述台階結構上,其中所述突出部分的高度小於所述鰭結構的高度。
- 如請求項15所述的封裝結構,進一步包括設置在所述多個第一半導體晶粒與所述散熱結構之間以及所述多個第二半導體晶粒與所述散熱結構之間的熱介面材料,其中所述突出部分與所述熱介面材料物理接觸。
- 如請求項17所述的封裝結構,其中所述熱介面材料包括: 第一熱介面材料,與所述多個第一半導體晶粒以及所述散熱結構的所述突出部分物理接觸;以及 第二熱介面材料,與所述多個第二半導體晶粒以及所述蓋結構的所述支撐部物理接觸。
- 如請求項15所述的封裝結構,其中所述突出部分包括多個突出子部分,且所述多個突出子部分中的每一者的面積實質上對應於由位於所述中介層結構的所述中心區之上的所述多個第一半導體晶粒中的每一者所佔用的面積。
- 如請求項19所述的封裝結構,其中所述蓋結構進一步包括與所述支撐部連結且將所述多個突出子部分彼此分開的多個分割部。
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2021
- 2021-07-04 US US17/367,401 patent/US11756854B2/en active Active
- 2021-08-26 TW TW110131749A patent/TWI773500B/zh active
- 2021-09-01 CN CN202111020887.7A patent/CN114725025A/zh active Pending
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- 2023-07-18 US US18/353,901 patent/US20230378019A1/en active Pending
Also Published As
Publication number | Publication date |
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CN114725025A (zh) | 2022-07-08 |
TWI773500B (zh) | 2022-08-01 |
US11756854B2 (en) | 2023-09-12 |
US20230378019A1 (en) | 2023-11-23 |
US20220301971A1 (en) | 2022-09-22 |
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