TW202118060A - 可阻擋逆電流之金氧半電晶體 - Google Patents

可阻擋逆電流之金氧半電晶體 Download PDF

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TW202118060A
TW202118060A TW108137167A TW108137167A TW202118060A TW 202118060 A TW202118060 A TW 202118060A TW 108137167 A TW108137167 A TW 108137167A TW 108137167 A TW108137167 A TW 108137167A TW 202118060 A TW202118060 A TW 202118060A
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semiconductor device
schottky
voltage semiconductor
voltage
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TW108137167A
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TWI761712B (zh
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黃宗義
許峻銘
黃炯福
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通嘉科技股份有限公司
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Priority to US17/038,159 priority patent/US11658249B2/en
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Abstract

本發明實施例提供一高壓半導體元件，包含有一金氧半電晶體以及一肖特基二極體。該金氧半電晶體的一半導體基底為一第一型態。一第二型態之一深井形成於該半導體基底上。該第一型態之一基體形成於該深井上。該第二型態之一重摻雜源設於該基體上，且該重摻雜源與該基體電性上相短路。該肖特基二極體具有一金屬層，作為該肖特基二極體之一陽極，形成於該深井上。該金屬層與該深井形成一肖特基接面。

Description

可阻擋逆電流之金氧半電晶體
本發明大致係關於耐高壓之金氧半電晶體，尤指整合有一肖特基二極體的金氧半電晶體，可以阻擋逆電流。
高壓MOSFET是一種半導體元件，一般是指可以耐受超過5V以上之汲源極跨壓(drain-to-source voltage)的一MOSFET。應用上，可以用來切換負載，或是用於電源管理上之在不同電壓準位間的轉換，或是做為高功率放大器中的功率元件。
基於規格要求，高壓MOSFET需要具備有相當高的汲源極跨壓的崩潰電壓。此外，往往因為應用上的不同，高壓MOSFET更需要有一些特別的規格。舉例來說，有的高壓MOSFET需要有低的閘極至源極電容(gate-to-source capacitance)，可以適用於高速切換。
本發明實施例提供一高壓半導體元件，包含有一金氧半電晶體以及一肖特基二極體。該金氧半電晶體的一半導體基底為一第一型態。一第二型態之一深井形成於該半導體基底上。該第一型態之一基體形成於該深井上。該第二型態之一重摻雜源設於該基體上，且該重摻雜源與該基體電性上相短路。該肖特基二極體具有一金屬層，作為該肖特基二極體之 一陽極，形成於該深井上。該金屬層與該深井形成一肖特基接面。
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10‧‧‧電源供應器
12‧‧‧同步整流控制器
14‧‧‧一次側控制器
16‧‧‧負載
18‧‧‧變壓器
28‧‧‧接地線
62a、62b、62c‧‧‧隔離區
66‧‧‧P型重摻雜區
68a、68b‧‧‧N型重摻雜源
68c‧‧‧N型重摻雜汲
70a、70b‧‧‧控制閘
72‧‧‧金屬層
78A、78G、78SB‧‧‧金屬栓塞
80‧‧‧P型輕摻雜區
82‧‧‧空洞
84‧‧‧P型深埋輕摻雜層
100、100a、100b、100c‧‧‧高壓半導體元件
102‧‧‧MOS
104‧‧‧肖特基二極體
106‧‧‧P型半導體基底
108‧‧‧P型基體
110‧‧‧N型深井
A‧‧‧陽極
CVCC‧‧‧操作電源電容
D‧‧‧汲極
D1、D2‧‧‧二極體
DET‧‧‧偵測接腳
DM‧‧‧DMOS區
DRV‧‧‧驅動接腳
GATE‧‧‧閘極
GND‧‧‧接地接腳
HVR‧‧‧高壓充電接腳
IPRI‧‧‧電流
ISEC‧‧‧電流
LP‧‧‧一次側線圈
LS‧‧‧二次側線圈
NMP‧‧‧主功率開關
NMS‧‧‧同步整流開關
Pth‧‧‧主要路徑
RDT‧‧‧電阻
SD‧‧‧肖特基區
SFLBK‧‧‧信號
SPKNE‧‧‧負突波
SSYN‧‧‧控制信號
S/B‧‧‧源基極
TCYC‧‧‧開關週期
TOFF‧‧‧關閉時間
TON‧‧‧開啟時間
VCC‧‧‧操作電源接腳
VDS‧‧‧通道電壓
VHVR‧‧‧信號
VIN‧‧‧輸入電壓
VIN‧‧‧輸入電源接腳
VOUT‧‧‧輸出電壓
第1圖顯示依據本發明所實施的同步整流控制器12。
第2A圖之上半部顯示高壓半導體元件100a的上視圖，而下半部顯示沿著上視圖中之AA線，高壓半導體元件100a的剖面圖。
第2B圖上半部也一樣顯示高壓半導體元件100a的上視圖，但下半部顯示沿著上視圖中之BB線，高壓半導體元件100a的剖面圖。
第3圖顯示依據本發明所實施的電源供應器10。
第4圖顯示第3圖中，一次側之信號SFLBK與二次側之信號VHVR的信號波形。
第5圖之上半部顯示高壓半導體元件100b的上視圖，而下半部顯示沿著上視圖中之CC線，高壓半導體元件100b的剖面圖。
第6圖顯示高壓半導體元件100c的剖面圖。
在本說明書中，有一些相同的符號，其表示具有相同或是類似之結構、功能、原理的元件，且為業界具有一般知識能力者可以依據本說明書之教導而推知。為說明書之簡潔度考量，相同之符號的元件將不再重述。
本發明之一實施例提供一高壓MOSFET，其整合有一金氧半場效電晶體(metal oxide semiconductor，MOS)與一肖特基二極體(Schottky Diode)，具有一共用半導體層，該共用半導體層係作為該肖特基二極體之一陰極，也作為該MOS電晶體之一汲極。該肖特基二極體順向偏壓時，該MOS可以耐受高汲源極跨壓。當該肖特基二極體逆向偏壓時，該肖特基二極體可以阻擋該高壓MOSFET中之二極體順向偏壓所可能產生的逆電流。
第1圖顯示依據本發明所實施的同步整流控制器12，可以採用一單晶晶片封裝所產生。如同第1圖所示，同步整流控制器12具有，但是不限於，驅動接腳DRV、高壓充電接腳HVR、偵測接腳DET、輸入電源接腳VIN、操作電源接腳VCC、以及接地接腳GND。
同步整流控制器12內部可以有以半導體製程技術製作的高壓半導體元件100。高壓半導體元件100可以是一高壓MOSFET，如同第1圖所示的，整合有MOS 102與肖特基二極體104。在第1圖中，MOS 102是一N型MOS，源極(source)跟基極(base)電性連接在一起，統稱為源基極S/B，電性連接到操作電源接腳VCC。MOS 102之汲極D到源基極S/B連接有二極體D1，汲極D到接地接腳GND之間有二極體D2，MOS 102之汲極D到高壓充電接腳HVR之間有肖特基二極體104。肖特基二極體104的陽極A電連接到高壓充電接腳HVR。當高壓充電接腳HVR上的信號VHVR為負值時，肖特基二極體104可以阻擋從二極體D1、D2來的逆電流，防止同步整流控制器12燒毀。
第2A圖之上半部顯示高壓半導體元件100a的上視圖，而下半部顯示沿著上視圖中之AA線，高壓半導體元件100a的剖面圖。第2B圖上半部也一樣顯示高壓半導體元件100a的上視圖，但下半部顯示沿著上視圖中之BB線，高壓半導體元件100a的剖面圖。第2A圖與第2B圖中都有輔助的 虛線，以表明上視圖與剖面圖中，相對應元件或是結構的位置關係。在一實施例中，高壓半導體元件100以高壓半導體元件100a實現。
高壓半導體元件100a的上視圖大致可以區隔成主要的兩區域：肖特基區SD以及DMOS區DM。肖特基區SD被隔離區62a所環繞，主要用來架構出第1圖中的肖特基二極體104。DMOS區DM大致從隔離區62a的邊界延伸到第2A圖的最右側，主要用來架構出第1圖中的MOS 102。
請參閱第2A圖中的剖面圖。P型半導體基底106上形成有N型深井110。在DMOS區DM中，P型基體108設於N型深井110上，而P型基體108內形成有N型重摻雜源68a、68b以及P型重摻雜區66。在上視圖中，隔絕區62c所圍繞的區域中有部分的N型深井110、P型基體108、N型重摻雜源68a、68b以及P型重摻雜區66。控制閘70a，可以是一圖案化的多晶矽，電隔絕的形成於N型重摻雜源68a、P型基體108、與N型深井110的上方，也覆蓋了部分的隔絕區62c。控制閘70b電隔絕的形成於N型重摻雜源68b、P型基體108、與N型深井110的上方，也覆蓋了部分的隔絕區62c。隔絕區62c圍繞N型重摻雜汲68c，其圍繞了隔離區62a。N型重摻雜源68a、68b以及P型重摻雜區66透過金屬連接短路在一起，作為MOS 102的源基極S/B。透過P型重摻雜區66，N型重摻雜源68a、68b與P型基體108電性上相短路。N型重摻雜汲68c作為MOS 102的汲極D。控制閘70a作為MOS 102的閘極GATE，可以控制N型重摻雜源68a到N型深井110之間的電性連接。控制閘70b可以透過金屬連接與控制閘70a短路在一起，用以增加MOS 102的電流驅動力。
儘管第2A與2B圖中，N型重摻雜源68a、68b、N型重摻雜汲68c分別在上視圖中不同的位置，但是他們都是經歷相同的製造過程所同時 產生，所以享有許多共同的特性。舉例來說，他們都具有相同的摻雜物、相同的摻雜濃度、相同的深度。類似的，隔絕區62a、62b、62c彼此也是經歷相同的製造過程所同時產生，享有一樣的絕緣物與一樣的厚度。如同一般半導體製程所知的，控制閘70a、70b只是在上視圖中具有不同的位置與大小，他們也是經歷相同的製造過程所同時產生，所以享有許多共同的特性。
肖特基區SD被隔離區62a所環繞，在第2A圖之上視圖中，包含有三個不相連接之隔絕區62b。肖特基區SD內之N型深井110表面上形成有金屬層72，作為肖特基二極體104之陽極A。金屬層72與N型深井110形成一肖特基接面，可以提供整流功能。肖特基區SD內之N型深井110作為肖特基二極體104之陰極。透過深井110，肖特基二極體104之陰極短路到MOS 102的汲極D。換言之，深井110是肖特基二極體104與MOS 102共用的半導體層。
金屬層72可以是自我對準金屬矽化物(self-aligned silicide，Salicide)製程中所產生的金屬矽化物(silicide)，也可以是接觸洞(contact hole)中的金屬栓塞(metal plug)。肖特基區SD中可以選擇性的形成有電阻保護氧化物(resist protect oxide，RPO)。當肖特基區SD中沒有RPO時，肖特基接面由金屬矽化物與N型深井110接觸所產生。當肖特基區SD中有RPO時，肖特基接面由金屬栓塞與N型深井110接觸所產生。
隔絕區62b到隔離區62a之間的距離，可以最佳化來設定肖特基二極體104的崩潰電壓(breakdown voltage)。隔絕區62b到隔離區62a之間的距離越近，肖特基二極體104之崩潰電壓越高。
N型重摻雜汲68c為浮動，意味著N型重摻雜汲68c上方並沒 有任何的金屬連接，使其電性連接到固定電位。只是，N型重摻雜汲68c等於電性短路到N型深井110，所以N型重摻雜汲68c可能受到N型深井110的影響而有固定的電位。
第2A圖中也顯示了當閘極GATE有適當的偏壓時，電子流從N型重摻雜源68a、經過P型基體108、N型深井110、到肖特基區SD中的金屬層72之主要路徑Pth。浮動的N型重摻雜汲68c的存在可以調整主要路徑Pth的位置，降低主要路徑Pth的等效電阻。
第2A圖與第2B圖之上視圖也顯示了許多的金屬栓塞78A、78G、78SB，用來提供肖特基二極體104之陽極A、MOS 102的閘極GATE、以及MOS 102的源基極S/B對外的金屬連接。
當第1圖之高壓半導體元件100以第2A圖與第2B圖之高壓半導體元件100a實現時，P型半導體基底106電連接至接地接腳GND、陽極A電連接至高壓充電接腳HVR、源基極S/B電連接至操作電源接腳VCC。第1圖中的二極體D1寄生於P型基體108與N型深井110之間的接面，而二極體D2寄生於P型半導體基底106與N型深井110之間的接面。
第3圖顯示依據本發明所實施的電源供應器10，其採用第1圖之同步整流控制器12。
電源供應器10有變壓器18，具有相互電感耦合的一次側線圈LP以及二次側線圈LS，分為位於相互直流隔離的一次側以及二次側。在一次側有一次側控制器14，其以信號SFLBK開關主功率開關NMP，藉以控制流經一次側線圈LP的電流IPRI。在二次側的同步整流控制器12控制同步整流開關NMS，對流經二次側線圈LS的電流ISEC整流，以產生輸出電壓VOUT，對負 載16供電。
同步整流控制器12的驅動接腳DRV提供控制信號SSYN，開啟或關閉同步整流開關NMS，控制二次側線圈LS與二次側之接地線28之間的電性連接。為了正確的整流，所以當同步整流開關NMS的通道電壓VDS為負時，同步整流開關NMS應該被開啟，將二次側線圈LS與接地線28短路。當同步整流開關NMS的通道電壓VDS為正時，同步整流開關NMS應該被關閉，避免損耗輸出電壓VOUT的電能。
高壓充電接腳HVR電性連接到二次側線圈LS與同步整流開關NMS之間的接點，其上有信號VHVR。偵測接腳DET與高壓充電接腳HVR之間連接有電阻RDT。輸入電源接腳VIN接收輸出電壓VOUT。操作電源接腳VCC連接至操作電源電容CVCC。接地接腳GND連接至接地線28。
第4圖顯示第3圖中，一次側之信號SFLBK與二次側之信號VHVR的信號波形。
信號SFLBK可以定義出開關週期TCYC、開啟時間TON、以及關閉時間TOFF。在開啟時間TON時，信號VHVR的電壓比輸出電壓VOUT高出很多，反映一次側的輸入電壓VIN。關閉時間TOFF剛開始時，因為一些寄生元件效應，信號VHVR會先出現大負電壓的負突波SPKNE。之後，隨著變壓器18放電，信號VHVR會是負值，但非常接近0V。變壓器18放電完畢之後，信號VHVR震盪，直到下一個開啟時間TON開始。
在開啟時間TON時，同步整流控制器12可以提供適當的偏壓至閘極GATE，開啟高壓半導體元件100，從信號VHVR汲取電流，對連接在操作電源接腳VCC上的操作電源電容CVCC充電，來提供同步整流控制器12 所需要的電能。高壓半導體元件100也可以耐受開啟時間TON時，信號VHVR所出現的高電壓。
在關閉時間TOFF時，同步整流控制器12中的肖特基二極體104，可以阻擋信號VHVR之負突波SPKNE所可能導致的逆電流。如果沒有肖特基二極體104，阻擋信號VHVR之負突波SPKNE可能導致二極體D1與D2順向偏壓，產生相當大的逆電流，可能燒毀同步整流控制器12中的元件。因為肖特基二極體104的存在，當負突波SPKNE出現時，肖特基二極體104逆偏壓，所以阻擋了逆電流的發生。
第5圖之上半部顯示高壓半導體元件100b的上視圖，而下半部顯示沿著上視圖中之CC線，高壓半導體元件100b的剖面圖。高壓半導體元件100b可以是作為第1圖中的高壓半導體元件100。第5圖與第2A、2B圖相似或是相同部分，可以參考先前對高壓半導體元件100a之說明得知，不再累述。
第5圖中的高壓半導體元件100b，僅僅跟第2A、2B圖中之高壓半導體元件100a，差異在於肖特基區SD內的架構。第2A、2B圖的肖特基區SD內有數個隔絕區62b。跟第2A、2B圖的肖特基區SD不同的，第5圖中的肖特基區SD，具有P型輕摻雜區80。P型輕摻雜區80可以在輕微摻雜汲極法(lightly-doped drain，LDD)製程中，針對降低PMOS電晶體電場製作的P型輕摻雜區時，一起形成。在第5圖的上視圖中，P形輕摻雜區80包圍有數個空洞(void)82，不形成P型輕摻雜區處。在第5圖之剖面圖中，空洞82內的金屬層72與N型深井110形成肖特基接面，P型輕摻雜區80與N型深井110形成PN接面。空洞82的大小可以設定肖特基二極體104的崩潰電壓 (breakdown voltage)。空洞82越小，空洞82下方兩旁的PN接面所形成的空乏區越容易連接在一起，肖特基二極體104之崩潰電壓就越高。
第5圖中的肖特基區SD內可以選擇性的形成有電阻保護氧化物。當肖特基區SD中沒有RPO時，肖特基接面由金屬矽化物與N型深井110接觸所產生。當肖特基區SD中有RPO時，肖特基接面由金屬栓塞與N型深井110接觸所產生。
第6圖顯示高壓半導體元件100c的剖面圖。第6圖與第5圖相似或是相同部分，可以參考先前對高壓半導體元件100a與100b之說明得知，不再累述。第6圖之高壓半導體元件100c可以與第5圖的高壓半導體元件100b共用一上視圖。比起第5圖之高壓半導體元件100b，第6圖之高壓半導體元件100c多了P型深埋輕摻雜層84，形成N型深井110內，於P型輕摻雜區80之下方，且大致跟P形輕摻雜區80對齊。P型深埋輕摻雜層84的存在，可以增加空洞82下方兩旁的PN接面所形成的空乏區的深度，更提高肖特基二極體104之崩潰電壓。第6圖中的肖特基區SD內也可以選擇性的形成有電阻保護氧化物。
以上實施例中隔絕區62a、62b、62c雖然以淺溝隔離(shallow trench isolation，STI)作為例子，但本發明不限於此。隔絕區62a、62b、62c也可以採用場氧化層(field oxide)來實施。
以上實施例中，N型重摻雜源68a、68b、N型重摻雜汲68c都可以在產生NMOS電晶體之源汲極重摻雜區時，同時形成。P型重摻雜區66可以在PMOS電晶體之源汲極重摻雜區時，同時形成。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
62a、62b、62c‧‧‧隔離區
66‧‧‧P型重摻雜區
68a、68b‧‧‧N型重摻雜源
68c‧‧‧N型重摻雜汲
70a、70b‧‧‧控制閘
72‧‧‧金屬層
78A、78G、78SB‧‧‧金屬栓塞
100a‧‧‧高壓半導體元件
106‧‧‧P型半導體基底
108‧‧‧P型基體
110‧‧‧N型深井
A‧‧‧陽極
D‧‧‧汲極
DM‧‧‧DMOS區
GATE‧‧‧閘極
Pth‧‧‧主要路徑
SD‧‧‧肖特基區
S/B‧‧‧源基極

Claims (10)

  1. 一種高壓半導體元件，包含有：
    一金氧半電晶體，包含有：
    一半導體基底，為一第一型態；
    一深井，為一第二型態，相反於該第一型態，形成於該半導體基底上；
    一基體(body)，為該第一型態，形成於該深井上；
    一重摻雜源，為該第二型態，設於該基體上，且該重摻雜源與該基體電性上相短路；以及
    一控制閘，形成於該基體上，用以控制該重摻雜源與該深井之間的電性連接；以及
    一肖特基二極體(Schottky Diode)，包含有：
    一金屬層，作為該肖特基二極體之一陽極，形成於該深井上，該金屬層與該深井形成一肖特基接面。
  2. 如申請專利範圍第1項之該高壓半導體元件，其中，該金氧半電晶體包含有：
    一重摻雜汲，為該第二型態，電性浮動地形成於該深井上。
  3. 如申請專利範圍第2項之該高壓半導體元件，其中，在一上視圖中，該肖特基二極體形成於一肖特基區，且該重摻雜汲環繞該肖特基二極體。
  4. 如申請專利範圍第2項之該高壓半導體元件，其中，在該上視圖中，該重摻雜汲環繞一隔絕區，其環繞該肖特基區。
  5. 如申請專利範圍第4項之該高壓半導體元件，其中，該隔絕區為一第一 隔絕區，且於該上視圖中，該肖特基區包含有一第二隔絕區，被該第一隔絕區所環繞。
  6. 如申請專利範圍第2項之該高壓半導體元件，其中，在一上視圖中，該控制閘至少部分重疊於一隔絕區、該深井、該基體、以及該重摻雜源。
  7. 如申請專利範圍第2項之該高壓半導體元件，其中，在一上視圖中，該肖特基二極體形成於一肖特基區，其另包含有一輕摻雜區，為該第一型態，且該輕摻雜區環繞該肖特基接面。
  8. 如申請專利範圍第7項之該高壓半導體元件，其中，在一剖面圖中，該肖特基二極體另包含有一深埋摻雜層，為該第一型態，形成於該輕摻雜區下方。
  9. 如申請專利範圍第8項之該高壓半導體元件，其中，該深埋摻雜層大致與該輕摻雜區對齊。
  10. 一種同步整流控制器，為一積體電路，適用於一電源供應器(power supply)，其包含有一變壓器以及一同步整流開關，該變壓器包含有一一次側線圈以及一二次側線圈，彼此相電感耦合，該同步整流開關與該二次側線圈相串聯，該同步整流控制器包含有：
    一驅動接腳，耦合至該同步整流開關，該同步整流控制器透過該驅動接腳，控制該二次側線圈與一電源線之間的電性連接；
    一高壓充電接腳，耦合至該二次側線圈與該同步整流開關之間的一接點；以及
    如申請專利範圍第1項之該高壓半導體元件，其中，該高壓充電接腳電連接至該陽極，該基體可電連接至一操作電源電容；
    透過該高壓半導體元件，該同步整流控制器可對該操作電源電容充電。
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