TW202101709A - 電子封裝結構及其晶片 - Google Patents
電子封裝結構及其晶片 Download PDFInfo
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Abstract
本發明公開一種電子封裝結構及其晶片。電子封裝結構包括基板、晶片、多條信號線以及核心接地線。晶片設置於基板上,並電性連接於基板。晶片的頂面設有一核心線路區以及一輸入輸出焊墊區。輸入輸出焊墊區位於核心線路區與晶片的一邊緣之間。晶片包括多個信號焊墊以及核心接地墊。多個信號焊墊設置在輸入輸出焊墊區,而核心接地墊靠近其中一信號焊墊,而設置在核心線路區內。多條信號線分別連接於多個信號焊墊。核心接地線連接於核心接地墊,並鄰近於其中一信號線,以提供屏蔽。
Description
本發明涉及一種電子封裝結構及其晶片,特別是涉及一種應用打線接合(wire bonding)的電子封裝結構及其晶片。
通過打線接合封裝技術而形成的積體電路封裝元件,在積體電路晶片的表面會具有核心區(core region)以及圍繞核心區設置的輸入/輸出焊墊陣列。另外,積體電路封裝元件中通常會包括多個分別連接於多個輸入/輸出焊墊的多條焊線,以使積體電路晶片(IC chip)通過打線而電性連接於基板或其他電子元件。
一般而言,多條焊線中包括一部分接地焊線,以避免其他用以傳輸信號的多條信號焊線之間相互串擾,而影響信號傳輸品質。然而,隨著積體電路晶片所要求的功能越來越多,在積體電路晶片上所需要設置的輸入/輸出焊墊的數量也越來越多。
若要兼顧多條信號焊線的信號傳輸完整性,需要額外地增加接地焊墊以及接地焊線的數量,來減少信號焊線的信號傳輸損耗或者是信號耦合。然而,在核心區周圍所能設置輸入/輸出焊墊的數量受限於積體電路晶片的尺寸。若要增加接地焊墊的數量,也意味著積體電路晶片的尺寸必須增加。如此,不僅使成本大幅增加,也難以符合積體電路封裝元件朝向輕薄短小發展的趨勢。
然而,若是為了避免使積體電路晶片的面積增加,而避免增加接地焊墊的數量,部分用於傳輸信號的信號焊線容易相互耦合,而降低信號傳輸品質。
本發明所要解決的技術問題在於,針對現有技術的不足提供一種電子封裝結構及其晶片,以在不增加晶片面積的情況下,維持較好的信號傳輸品質。
為了解決上述的技術問題,本發明所採用的其中一技術方案是,提供一種電子封裝結構,其包括基板、晶片、多條信號線以及核心接地線。晶片設置於基板上,並電性連接於基板。晶片的頂面設有一核心線路區以及一輸入輸出焊墊區,輸入輸出焊墊區位於核心線路區與晶片的一邊緣之間。晶片包括多個信號焊墊以及核心接地墊,多個信號焊墊設置於輸入輸出焊墊區內,且核心接地墊設置於核心線路區內,且靠近至少一信號焊墊。多條信號線分別連接於多個信號焊墊。核心接地線連接於核心接地墊,並鄰近於其中一信號線,以提供屏蔽。
為了解決上述的技術問題,本發明所採用的另外一技術方案是,提供一種晶片,晶片的頂面設有核心線路區、輸入輸出焊墊區、多個信號焊墊以及核心接地墊。 多個信號焊墊設置在輸入輸出焊墊區內。核心接地墊設置在核心線路區內,且靠近至少一信號焊墊。
本發明的其中一有益效果在於,本發明所提供的電子封裝結構及其晶片,其能通過“核心接地墊設置在核心線路區內,並靠近至少一信號焊墊”的技術方案,使核心接地墊及其所連接的核心接地線,對其中一信號焊墊及其所連接的信號線提供屏蔽,進而可在不增加晶片面積的情況下,維持較佳的信號完整性。
為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與圖式,然而所提供的圖式僅用於提供參考與說明,並非用來對本發明加以限制。
以下是通過特定的具體實施例來說明本發明所公開有關“電子封裝結構及其晶片”的實施方式,本領域技術人員可由本說明書所公開的內容瞭解本發明的優點與效果。本發明可通過其他不同的具體實施例加以施行或應用,本說明書中的各項細節也可基於不同觀點與應用,在不悖離本發明的構思下進行各種修改與變更。另外,本發明的附圖僅為簡單示意說明,並非依實際尺寸的描繪,事先聲明。以下的實施方式將進一步詳細說明本發明的相關技術內容,但所公開的內容並非用以限制本發明的保護範圍。
應當可以理解的是,雖然本文中可能會使用到“第一”、“第二”、“第三”等術語來描述各種元件或者信號,但這些元件或者信號不應受這些術語的限制。這些術語主要是用以區分一元件與另一元件,或者一信號與另一信號。另外,本文中所使用的術語“或”,應視實際情況可能包括相關聯的列出項目中的任一個或者多個的組合。
[第一實施例]
參閱圖1至圖2所示,本發明第一實施例提供一種電子封裝結構Z1,其包括:晶片10A、基板20、多條信號線300S以及核心接地線301G。
晶片10A可以是系統單晶片(system on chip)、微處理晶片、動態隨機記憶體晶片或者是其他元件,本發明並不限制。晶片10A設置於基板20上,並電性連接於基板20。在本實施例中,晶片10A的頂面10s設有核心線路區CR、輸入輸出焊墊區PR、多個信號焊墊100S以及至少一核心接地墊101G。
核心線路區CR位於晶片10A頂面10s的中央區域,而輸入輸出焊墊區PR則位於核心線路區CR的周圍。進一步而言,輸入輸出焊墊區PR是位於核心線路區CR與晶片10A的一邊緣之間。需先說明的是,在本實施例中,為了便於說明,只繪示位於核心線路區CR其中一側的輸入輸出焊墊區PR。在其他實施例中,輸入輸出焊墊區PR會環繞核心線路區CR。
請參照圖1,多個信號焊墊100S設置於輸入輸出焊墊區PR內。另外,根據晶片10A的功能,多個信號焊墊100S可被指定為不同的信號連接端,如:接入電壓端(VCC)、工作電壓端(VDD)或者公共接地端電壓(VSS)、電源、時脈信號端(clock)、位址信號端(address signals)等等。在一實施例中,晶片10A還包括至少一接地焊墊100G,且接地焊墊100G與多個信號焊墊100S共同設置在輸入輸出焊墊區PR內。
在其他實施例中,晶片10A可包括多個接地焊墊100G以及多個信號焊墊100S,且多個接地焊墊100G與多個信號焊墊100S排列成一焊墊陣列。進一步而言,多個接地焊墊100G與多個信號焊墊100S會在平行晶片10A邊緣的方向(即第一方向D1)上排成m行,以及在垂直於晶片10A邊緣的方向(即第二方向D2)上,排列成n列。
需先說明的是,圖1中僅以簡化後的焊墊陣列為例,來說明本發明之概念,並非實際的焊墊陣列。也就是說,在圖1中,僅繪示沿著核心線路區CR的一側邊排成一行的多個信號焊墊100S以及接地焊墊100G。
另外,核心接地墊101G設置在核心線路區CR內,並靠近至少一信號焊墊100S。進一步而言,核心接地墊101G會靠近於需要被屏蔽的信號焊墊100S。在圖1的實施例中,假設位於輸入輸出焊墊區PR內的焊墊陣列中,最遠離接地焊墊100G的信號焊墊100S最需要被屏蔽,核心接地墊101G會鄰近於最遠離接地焊墊100G的信號焊墊100S設置。
換言之,核心接地墊101G與待屏蔽的信號焊墊100S之間的直線距離,會小於核心接地墊101G與其他信號焊墊100S之間的直線距離。在一實施例中,前述的直線距離,可以被定義為核心接地墊101G的幾何中心與信號焊墊100S的幾何中心之間的最短距離。
在本實施例中,晶片10A還包括設置在核心線路區CR內的多條接地跡線G1以及多條電源跡線P1,且多條接地跡線G1與多條電源跡線P1交替地排列。
在一實施例中,多條接地跡線G1與多條電源跡線P1的排列方向與信號焊墊100S的排列方向大致相同,但多條接地跡線G1與多條電源跡線P1的延伸方向不平行於信號焊墊100S的排列方向。舉例而言,在圖1中,位於輸入輸出焊墊區PR內的多個信號焊墊100S是在第一方向D1上排成至少一行。多條接地跡線G1與多條電源跡線P1在第一方向D1上交替地排列,並且都沿著第二方向D2延伸。另外,核心接地墊101G是設置在最靠近於待屏蔽的信號焊墊100S的其中一接地跡線G1的端部上,並且該端部較靠近輸入輸出焊墊區PR。
然而,在其他實施例中,多條接地跡線G1與多條電源跡線P1的延伸方向也可以大致平行於信號焊墊100S的排列方向。也就是說,多條接地跡線G1與多條電源跡線P1都沿著第一方向D1延伸,但在第二方向D2上交替地排列。
在這個情況下,核心接地墊101G仍設置在最靠近於待屏蔽的信號焊墊100S的其中一接地跡線G1上。但是,核心接地墊101G不一定會設置在接地跡線G1的端部。也就是說,核心接地墊101G在接地跡線G1上的位置是根據待屏蔽的信號焊墊100S的位置來調整。因此,核心接地墊101G也可能設置於接地跡線G1的中間部分。
請參照圖1,基板20可以是電路板、陶瓷基板、金屬基板或者是複合材基板。在本實施例中,基板20為電路板,並具有一承載面20s,且晶片10A設置於承載面20s上。基板20內已預先配置多條線路(圖未示)以及位於承載面20s上的多個接墊。在圖1中,多個接墊會分別對應於晶片10A上的多個信號焊墊100S、接地焊墊100G以及核心接地墊101G的位置來配置。因此,在本實施例中,多個接墊可被區分為信號接墊200S、第一接地墊200G以及第二接地墊201G。
另外,如圖1所示,電子封裝結構Z1還包括多條信號線300S、至少一接地線300G以及至少一核心接地線301G。每一個信號焊墊100S會通過對應的信號線300S,而連接位於基板20上的對應的信號接墊200S。接地焊墊100G會通過對應的接地線300G,而連接位於基板20上的第一接地墊200G。另外,核心接地墊101G會通過對應的核心接地線301G,而連接對應的第二接地墊201G。
據此,在本實施例中,晶片10A的信號焊墊100S、接地焊墊100G以及核心接地墊101G是分別通過對應的信號線300S、對應的接地線300G以及對應的核心接地線301G,電性連接於基板20的電路。
然而,在其他實施例中,信號焊墊100S、接地焊墊100G與核心接地墊101G也可分別通過對應的信號線300S、對應的接地線300G以及對應的核心接地線301G,而電性連接於另一電子元件。因此,本發明並未限制晶片10A只能電性連接於基板20。
須說明的是,在本實施例中,位於輸入輸出焊墊區PR的接地焊墊100G及其所連接的接地線300G,會電性連接於基板20的一接地平面。因此,接地焊墊100G以及其所連接的接地線300G可以對鄰近的信號線300S提供屏蔽,以減少信號線300S之間的串擾。然而,由於信號焊墊100S的數量會大於接地焊墊100G的數量,因此不一定所有的信號線300S都能夠被接地線300G所屏蔽。
據此,在本發明實施例中,通過在核心線路區CR內設置一核心接地墊101G及其所連接的核心接地線301G,來對至少一信號焊墊100S及其所連接的信號線300S提供屏蔽。因此,參照圖1以及圖2,核心接地線301G會鄰近於所要屏蔽的信號線300S設置。
在一實施例中,可以通過執行模擬測試,來得到每一個信號線300S的訊號傳輸模擬結果。之後,可根據訊號傳輸模擬結果,來決定待屏蔽的信號焊墊100S及其所連接的信號線300S。進一步而言,核心接地墊101G及其所連接的核心接地線301G,可以對訊號傳輸品質最差的信號線300S及其所連接的信號焊墊100S提供屏蔽,來減少串擾以及提升訊號傳輸品質。
在圖1的實施例中,假設在同一行中,最遠離接地焊墊100G的信號焊墊100S及其所連接的信號線300S的訊號傳輸品質最差。因此,核心接地墊101G是鄰近於最遠離接地焊墊100G的其中一信號焊墊100S設置。然而,在其他實施例中,根據訊號傳輸模擬結果,待屏蔽的信號焊墊100S(及其所連接的信號線300S)不一定是最遠離接地焊墊的信號焊墊100S。因此,核心接地墊101G的位置以及數量可能根據實際需求而調整,本發明並不限制。
須說明的是,核心線路區CR內因設有多條接地跡線G1以及多條電源跡線P1,因此不論核心線路區CR內是否設置核心接地墊101G,核心線路區CR本身都會佔據晶片10A既定的面積。
據此,當在核心線路區CR內設置核心接地墊101G時,不需要為了增加核心接地墊101G的設置空間,而進一步增加晶片10A的尺寸。也就是說,在本發明中,通過在核心線路區CR內設置核心接地墊101G及其所連接的核心接地線301G,可以在不增加晶片10A尺寸的情況下,改善信號線300S之間串擾的問題。
特別是對於信號焊墊100S的數量與接地焊墊100G的數量之間的比值較大的焊墊陣列而言,本發明之技術手段所達到的效果更加明顯。另外,核心接地墊101G的數量可大於或等於接地焊墊100G的數量。
[第二實施例]
請參照圖3,本實施例的電子封裝結構Z2與第一實施例的電子封裝結構Z1相同或相似的元件具有相同標號,且相同的部分不再贅述。本實施例中,在晶片10B的核心線路區CR中,設置兩個核心接地墊101G,且兩個核心接地墊101G分別通過兩條核心接地線301G,連接於基板20上的兩個第二接地墊201G。此外,兩個核心接地墊101G是分別設置於兩條不同的接地跡線G1上,並分別靠近於兩個待屏蔽的信號焊墊100S。
據此,兩個核心接地墊101G及其所分別連接的兩條核心接地線301G,可分別對不同的兩條信號線300S提供屏蔽。也就是說,核心接地墊101G與核心接地線301G的位置以及數量可能根據實際需求而調整,本發明並不限制。
[第三實施例]
請參照圖4,本實施例的電子封裝結構Z3與第二實施例的電子封裝結構Z2相同或相似的元件具有相同標號,且相同的部分不再贅述。在本實施例中,晶片10C的核心線路區CR內設置兩個核心接地墊101G、101G’。 在兩個核心接地墊101G、101G’中,其中一個核心接地墊101G’是對應於兩相鄰的信號焊墊100S設置,且核心接地墊101G’的俯視形狀面積大於另一核心接地墊101G的俯視形狀面積。
在本實施例中,核心接地線301G的數量大於核心接地墊101G的數量。詳細而言,電子封裝結構Z3包括三條核心接地線301G。其中一條核心接地線301G連接於其中一個核心接地墊101G,而另外兩條核心接地線302G、303G共同連接於俯視形狀面積較大的另一核心接地墊101G’。 據此,連接於同一核心接地墊101G’的兩條核心接地線302G、303G,可以分別對兩條信號線300S提供屏蔽。
另外,本實施例的基板20包括三個第二接地墊201G、202G、203G。其中一個第二接地墊201G對應於核心接地墊101G設置,而另外兩個核心接地墊202G、203G對應於另一個核心接地墊101G’設置。據此,核心接地墊101G通過對應的核心接地線301G而連接於對應的第二接地墊201G,且另一核心接地墊101G’可通過對應的兩條核心接地線302G、303G,而分別連接於兩個第二接地墊202G、203G。
也就是說,在不增加核心接地墊101G的數量的情況下,通過增加核心接地墊101G的俯視面積,可以增加連接於核心接地墊101G的核心接地線301G的數量,以對更多的信號線300S提供屏蔽。據此,在本發明實施例中,並不限定一個核心接地墊101G只能連接於一條核心接地線。
[第四實施例]
請參照圖5,本實施例的電子封裝結構Z4與第一實施例的電子封裝結構Z1相同或相似的元件具有相同標號,且相同的部分不再贅述。在本實施例中,晶片10D的輸入輸出焊墊區包括圍繞核心線路區CR的多個子區域PR1~PR4,且多個信號焊墊100S以及多個接地焊墊100G被區分為多個焊墊組,且每一焊墊組設置在對應的子區域PR1~PR4內。
詳細而言,本實施例的輸入輸出焊墊區包括四個彼此分離的子區域PR1~PR4,且四個子區域PR1~PR4分別設置在核心線路區CR的四個側邊。
另外,晶片10D還包括多個核心接地墊101G(圖5中繪示4個),且每一核心接地墊101G會分別靠近核心線路區CR的四個側邊,並對相對應的子區域PR1~PR4內的至少一信號焊墊100S提供屏蔽。據此,在本實施例中,多個核心接地墊101G是分別設置於不同的接地跡線G1上,並分別對應於所要屏蔽的多個信號焊墊100S的位置。
基板20並具有多個第二接地墊201G,這些第二接地墊201G分別對應這些核心接地墊101G的位置,而設置在承載面20s上。在本實施例中,第二接地墊201G分別設置在晶片10D的四個側邊。另外,每一核心接地墊101G會通過對應的核心接地線301G連接至對應的第二接地墊201G。據此,每一核心接地墊101G及其所連接的核心接地線301G,可對於對應的信號焊墊100S及其所連接的信號線提供屏蔽,以減少串擾。
[實施例的有益效果]
本發明的其中一有益效果在於,本發明所提供的電子封裝結構及其晶片,其能通過“核心接地墊101G設置在核心線路區CR內,並靠近至少一信號焊墊100S”的技術方案,使核心接地墊101G及其所連接的核心接地線301G,對其中一信號焊墊100S及其所連接的信號線300S提供屏蔽,進而可在不增加晶片面積的情況下,維持較佳的信號完整性。
更進一步來說,在本發明中,是通過在核心線路區CR內設置核心接地墊101G及其所連接的核心接地線301G,而不是在輸入輸出焊墊區PR內增加接地焊墊100G的數量,來解決信號線300S之間的串擾的問題。因此,不需要為了增加接地焊墊100G設置的空間,而增加晶片10A的尺寸。如此,可避免在提升訊號傳輸品質時,增加晶片的成本。
另外,在本發明中,可以根據最需要被屏蔽的信號焊墊100S及其所連接的信號線300S的位置,來設置核心接地墊101G及核心接地線301G的數量以及位置。通過核心接地墊101G以及接地焊墊100G的相互配合,即便接地焊墊100G的數量小於信號焊墊100S的數量,也可減少串擾並提升訊號傳輸品質。
以上所公開的內容僅為本發明的優選可行實施例,並非因此侷限本發明的申請專利範圍,所以凡是運用本發明說明書及圖式內容所做的等效技術變化,均包含於本發明的申請專利範圍內。
Z1~Z4:電子封裝結構10A~10D:晶片10s:頂面CR:核心線路區PR:輸入輸出焊墊區PR1~PR4:子區域100G:接地焊墊100S:信號焊墊101G、101G’:核心接地墊G1:接地跡線P1:電源跡線20:基板20s:承載面200S:信號接墊200G:第一接地墊201G、202G、203G:第二接地墊300S:信號線300G:接地線301G、302G、303G:核心接地線D1:第一方向D2:第二方向
圖1為本發明第一實施例的電子封裝結構的局部俯視示意圖。
圖2為本發明第一實施例的電子封裝結構的局部側視示意圖。
圖3為本發明第二實施例的電子封裝結構的局部俯視示意圖。
圖4為本發明第三實施例的電子封裝結構的局部俯視示意圖。
圖5為本發明第四實施例的電子封裝結構的局部俯視示意圖。
Z1:電子封裝結構
10A:晶片
10s:頂面
CR:核心線路區
PR:輸入輸出焊墊區
100G:接地焊墊
100S:信號焊墊
101G:核心接地墊
G1:接地跡線
P1:電源跡線
20:基板
20s:承載面
200S:信號接墊
200G:第一接地墊
201G:第二接地墊
300S:信號線
300G:接地線
301G:核心接地線
D1:第一方向
D2:第二方向
Claims (10)
- 一種電子封裝結構,其包括: 一基板; 一晶片,其設置於所述基板上,並電性連接於所述基板,其中,所述晶片的頂面設有一核心線路區以及一輸入輸出焊墊區,所述輸入輸出焊墊區位於所述核心線路區與所述晶片的一邊緣之間,且所述晶片包括: 多個信號焊墊,其設置於所述輸入輸出焊墊區內;以及 一核心接地墊,其設置於所述核心線路區內,且靠近至少一所述信號焊墊; 多條信號線,其分別連接於多個所述信號焊墊;以及 一核心接地線,其連接於所述核心接地墊,並鄰近於其中一所述信號線,以提供屏蔽。
- 如申請專利範圍第1項所述的電子封裝結構,其中,所述晶片還進一步包括至少一接地焊墊,至少一所述接地焊墊與所述多個信號焊墊設置在所述輸入輸出焊墊區內,並沿著所述核心線路區的一側邊排列成至少一行,其中,所述核心接地墊鄰近於最遠離所述接地焊墊的其中一所述信號焊墊設置。
- 如申請專利範圍第1項所述的電子封裝結構,其中,多個所述信號焊墊沿著所述核心線路區的一側邊排列成至少一行,且所述核心接地墊對應於兩個相鄰的所述信號焊墊設置。
- 如申請專利範圍第3項所述的電子封裝結構,還進一步包括:另一核心接地線,其中,兩個所述核心接地線連接於同一所述核心接地墊,以分別對兩相鄰的所述信號線提供屏蔽。
- 如申請專利範圍第1項所述的電子封裝結構,其中,所述晶片還進一步包括多條接地跡線以及多條電源跡線,多條所述接地跡線與多條所述電源跡線交替地設置於所述核心線路區內,且所述核心接地墊設置於其中一所述接地跡線上。
- 如申請專利範圍第1項所述的電子封裝結構,其中,所述輸入輸出焊墊區包括圍繞所述核心線路區的多個子區域,多個所述信號焊墊被區分為多個焊墊組,且每一所述焊墊組設置在對應的所述子區域內。
- 如申請專利範圍第6項所述的電子封裝結構,其中,所述晶片還進一步包括: 另外多個核心接地墊,其設置於所述核心線路區內並靠近所述核心線路區的側邊,其中,每一所述核心接地墊靠近相對應的所述子區域的其中一所述信號焊墊。
- 一種晶片,其包括: 一核心線路區,其位於所述晶片的一頂面; 一輸入輸出焊墊區,其位於所述晶片的一頂面,並位於所述核心線路區與所述晶片的一邊緣之間; 多個信號焊墊,其設置於所述輸入輸出焊墊區內;以及 一核心接地墊,其設置於所述核心線路區內,且靠近至少一所述信號焊墊。
- 如申請專利範圍第8項所述的晶片,還進一步包括:至少一接地焊墊,至少一所述接地焊墊與所述多個信號焊墊設置在所述輸入輸出焊墊區內,並沿著所述核心線路區的其中一側邊排列成至少一行,其中,所述核心接地墊鄰近於最遠離所述接地焊墊的其中一所述信號焊墊設置。
- 如申請專利範圍第8項所述的晶片,還進一步包括:多條接地跡線以及多條電源跡線,多條所述接地跡線與多條所述電源跡線交替地設置於所述核心線路區內,且所述核心接地墊設置於其中一所述接地跡線上。
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