TW202101618A - 半導體封裝和電子系統 - Google Patents

半導體封裝和電子系統 Download PDF

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Publication number
TW202101618A
TW202101618A TW109120852A TW109120852A TW202101618A TW 202101618 A TW202101618 A TW 202101618A TW 109120852 A TW109120852 A TW 109120852A TW 109120852 A TW109120852 A TW 109120852A TW 202101618 A TW202101618 A TW 202101618A
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Taiwan
Prior art keywords
lead terminal
semiconductor package
pad
semiconductor
outer end
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TW109120852A
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English (en)
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TWI794610B (zh
Inventor
張晉強
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聯發科技股份有限公司
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Publication of TWI794610B publication Critical patent/TWI794610B/zh

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Abstract

本發明公開一種半導體封裝，包括：至少一個晶粒附接焊盤；至少一個半導體晶粒，安裝在該至少一個晶粒附接焊盤上；以及複數個引線端子，佈置在該至少一個晶粒附接焊盤周圍，並透過多條接合導線電連接到該至少一個半導體晶粒上相應的輸入/輸出焊盤，其中，該複數個引線端子包括沿著該半導體封裝的至少一個側面以三排結構佈置第一引線端子、第二引線端子和第三引線端子，並且其中該每個第一引線端子、第二引線端子和第三引線端子在相應的切割端均具有暴露的基底金屬。

Description

半導體封裝和電子系統
本發明涉及半導體技術領域，尤其涉及一種半導體封裝和電子系統。
掌上型（handheld）消費市場在電子產品的小型化方面是積極進取的（aggressive）。主要受到蜂窩電話（cellular phone）和數位助理（digital assistant）市場的推動，這些設備的製造商面臨格式（format）不斷縮小以及對更多類似PC（Personal Computer，個人計算機）功能的需求的挑戰。只有高性能的邏輯IC（integrated circuit，積體電路）伴隨著增加的存儲能力，才能實現附加功能。以較小的PC板形式組合在一起的這一挑戰，對表面貼裝元件製造商提出了壓力，要求表面貼裝元件製造商的產品設計必須佔據最小的面積。
在當今的掌上型設備市場中，廣泛使用的許多部件已從傳統的引腳框架（leaded frame）設計遷移到無引腳（non-leaded）形式。掌上型設備製造商的主要驅動力是這些部件較小的安裝區域所節省的PC板空間。此外，大多數部件的重量和高度也有所降低，並且電氣性能得到改善。當關鍵的晶片級封裝轉換為無引腳設計時，可以將節省的額外空間分配給新部件，以增加設備功能。
此外，當前引腳框架封裝的I / O（input/output，輸入/輸出）密度仍然很低。儘管先進QFN（先進四方平面無引線，advanced Quad Flat No-lead，aQFN）封裝可以提供高I / O密度，但傳統的aQFN封裝仍存在SMT（Surface Mount Technology，表面安裝技術）焊接（solder）檢查（inspection）問題。無引線設計使用導線接合（wire bond）作為IC與框架之間的主要互連（interconnection）。但是，由於獨特的地面幾何形狀（land site geometry）和形狀係數（form factor）密度，傳統的導線接合製程可能無法產生高產（high yielding）生產。對於這些設計，需要額外的導線接合功能以產生可接受的產量。
有鑑於此，本發明提供一種半導體封裝和電子系統，以提高產量。
根據本發明的第一方面，公開一種半導體封裝，包括：
至少一個晶粒附接焊盤；
至少一個半導體晶粒，安裝在該至少一個晶粒附接焊盤上；以及
複數個引線端子，佈置在該至少一個晶粒附接焊盤周圍，並透過多條接合導線電連接到該至少一個半導體晶粒上相應的輸入/輸出焊盤，其中，該複數個引線端子包括沿著該半導體封裝的至少一個側面以三排結構佈置第一引線端子、第二引線端子和第三引線端子，並且其中該每個第一引線端子、第二引線端子和第三引線端子在相應的切割端均具有暴露的基底金屬。
根據本發明的第二方面，公開一種半導體封裝，包括：
晶粒附接焊盤；
半導體晶粒，安裝在該晶粒附接焊盤上；以及
引線端子，佈置在該晶粒附接焊盤周圍，並透過接合導線電連接到該半導體晶粒上的輸入/輸出焊盤，其中，該引線端子的外端具有暴露的基底金屬。
根據本發明的第三方面，公開一種電子系統，包括：
如上所述的一種半導體封裝；以及
印刷電路板，其中該半導體封裝安裝在該印刷電路板上。
本發明的半導體封裝由於每個第一引線端子、第二引線端子和第三引線端子在相應的切割端均具有暴露的基底金屬，因此，在後續的製程中安裝到系統板或電路板時可以在該暴露的基底金屬的上形成焊料填角，這樣在檢查的時候就可以方便查看，從而可以快速方便的確定半導體封裝與系統板或電路板之間的電連接是否可靠，提高生產效率，以提高生產量。
以下描述是實施本發明的最佳構想模式。進行該描述是為了說明本發明的一般原理，而不應被認為是限制性的。本發明的範圍由所附申請專利範圍書確定。
以下將針對特定實施例並參考某些附圖來描述本發明，但是本發明不限於此，而僅由申請專利範圍書限定。所描述的附圖僅是示意性的而非限制性的。在附圖中，出於說明的目的，一些元件的尺寸可能被放大並且未按比例繪製。在本發明的實踐中，尺寸和相對尺寸不對應於實際尺寸。
為了說明的目的，本文使用的術語“水平”被定義為平行於本發明的平面或表面的平面，而不管其取向如何。術語“垂直”是指與剛剛定義的水平方向垂直的方向。諸如“在...上”、“在上方”、“在下方”、“底部”、“頂部”、“側面”（如在“側壁”中）、“高於”、“低於”、“上方”、“在…上面”和“在…下面”之類的術語相對於水平面定義的。
如本文所用，術語“在...上”是指以及指代元件之間的直接接觸或間接接觸。本文所用的術語“加工”包括衝壓、鍛造、圖案化、曝光、顯影、蝕刻、清潔和/或去除材料或根據形成所述結構所需的鐳射修整等等。如本文所用，術語“系統”是指以及指代根據使用該術語的上下文的本發明的方法和裝置。
本發明的內容涉及一種改進的鋸齒型QFN半導體封裝（或QFN封裝、半導體封裝），其具有沿著鋸齒型QFN半導體封裝的至少一側佈置的多排端子。使用本發明是有利的，因為可以減小封裝尺寸（尺寸減小約20％），並且由於導線接合（接合導線）長度的減小可以提高半導體封裝的性能（例如提高訊號傳遞速度和減小訊號傳遞途中被干擾的可能性）。
通常，引線框架帶（leadframe strip）中裝有複數個引線框架。半導體晶粒或微電子器件可以安裝在每個引線框架上，並用模塑料密封。引線框架在分割期間被分割開，以形成單獨的半導體封裝。半導體封裝的一種類型是平面封裝（flat-pack）無引線（no-lead）封裝。本實施例中每個安裝有半導體晶粒或微電子件的引線框架在分割期間被分割開之後，每個引線端子在封裝的底部和側面暴露。本實施例中，在分割引線框架帶期間的鋸切過程導致引線端子在每個引線端子的切割端（cut end）（切割端未必一定是切割或分割而留下的端，也可以是經過其他製程而形成的端，例如光刻、蝕刻、研磨等等）或每個引線端子的側面上具有至少一些暴露的基底金屬（base metal）。本實施例前述切割端（本發明上下文中也可以稱為外端或引線端子的外端）與封裝的側壁表面或模塑料的側壁表面垂直齊平，或者切割端（外端）與模塑料的側壁表面不齊平，例如相對於模塑料的側壁表面向內凹陷，形成缺口（即相對於模塑料的側壁表面凹陷的缺口）。
焊料填角（solder fillet）是平面封裝無引線封裝的每個引線端子的末端或側面的焊點的延伸（焊料填角又可稱為焊接圓角、焊錫焊腳或焊料焊腳）。焊料填角的存在與否可以證明平面封裝無引線封裝的端子與印刷電路板（PCB）之間的電連接品質（例如當查看到有焊料填角時，可以說明該封裝與PCB之間的連接較可靠，連接品質較好）。然而對於常規的aQFN半導體封裝，在目視檢查（visual inspection）過程中可能看不到焊料填角，例如安裝到PCB之後，檢查時看不到焊料填角，這樣在目視檢查時無法判斷封裝與PCB之間的電連接品質是否良好，從而影響了檢查的效率，進一步導致產量難以提升。因此，傳統的aQFN封裝具有SMT焊料檢查問題，並且這種問題影響了效率和產量。
第1圖是根據本發明的一個實施例的具有多排引線端子的示例性鋸齒型四方平面無引線（QFN）半導體封裝的示意性透視俯視圖，其中第1圖可以是尚未將邊緣進行切割的狀態。第2圖是沿著第1圖中的虛線I-I’截取的示意性截面圖，其中第2圖僅是為了展示橫截面的一些示意，例如引線端子的結構和與半導體晶粒的連接，不代表本實施例的所有結構均如第2圖所示，例如模塑料可以包圍引線端子的側面。例如，第1圖中的示例性鋸齒型QFN半導體封裝（以下稱為QFN封裝）可以具有92個引線端子（或針腳（pin）），並且QFN封裝尺寸為8.7mm x 6.0mm。但是，應當理解，引線端子的數量和QFN封裝的尺寸僅用於說明目的。
如第1圖和第2圖所示，QFN封裝1（也可以稱為半導體封裝1）包括複數個引線端子200，這些引線端子200圍繞晶粒附接焊盤210佈置，該晶粒附接焊盤210在中央區域中由在QFN封裝1四個角處延伸的四個魚尾拉杆（fishtail tie-bar）230支撐。 QFN封裝1具有矩形輪廓並且具有四個側面S1 〜S4 。第一側面S1 與第三側面S3 相對，第二側面S2 與第四側面S4 相對。可選地，接地環220可以設置在複數個引線端子200和晶粒附接焊盤210之間。接地環220可以減小引線端子200與晶粒之間傳輸訊號時所受的干擾。晶粒附接焊盤210可以是引線框架的，例如在引線框架上。
根據一個實施例，至少一個半導體晶粒10安裝在晶粒附接焊盤210的頂表面210a上。複數個引線端子200、半導體晶粒10、晶粒附接焊盤210和魚尾拉杆230由模塑料302封裝。複數個引線端子200中的每個引線端子在每個引線端子200的外端或側面上具有至少一個暴露的基底金屬200a。晶粒附接焊盤210的底表面210b（如第2圖所示）可以從QFN封裝1的底部暴露出來，並且可以連接到印刷電路板（PCB）中的接地平面和/或散熱插頭（未示出）。根據一個實施例，接地環220從QFN封裝1的底部被半蝕刻（half-etch）並且不從底部暴露。
根據一個實施例，複數個引線端子200包括佈置在第一排（或外排（outer row））中的複數個第一引線端子201，第一排（或第一引線端子201）沿著QFN封裝1的四個側面S1 〜S4 佈置。在一個實施例中，複數個引線端子200包括佈置在第二排（或中間排）中的複數個第二引線端子202，第二排（或第二引線端子202）可以沿著四個側面中的至少一個（例如，第一側面S1 、第二側面S2 、第四側面S4 ）佈置。根據一個實施例，複數個引線端子200包括佈置在第三排（或內排）中的複數個第三引線端子203，第三排（或第三引線端子203）可以沿著 QFN封裝1的四個側面中的至少一個（例如第一側面S1 ）佈置。因此，QFN封裝1在第一側面S1 上可以包括三排引線配置，在第二側面S2和第四側面S4上可以包括兩排引線配置，並且第三側面S3 上可以包括一排引線配置。
半導體晶粒10包括沿著半導體晶粒10的周邊設置的複數個輸入/輸出（I/O）焊盤101〜104。根據非限制性實施例，例如，半導體晶粒10的I/O焊盤101可以沿著QFN封裝1的第一側面S1 佈置，並且可以透過接合導線131電連接到第一側面S1 上的引線端子200。根據非限制性實施例，接合導線131可以是銅線。由於內排的第三引線端子203靠近I/O焊盤101，因此可以減小接合導線131的長度，並且可以改善QFN封裝1的電性能，例如提高訊號傳遞速度和減小訊號傳遞途中被干擾的可能性。
根據非限制性實施例，例如，半導體晶粒10的I/O焊盤102和104可以分別沿著QFN封裝1的第二側面S2和第四側面S4 設置，並且可以分別透過接合導線132和134電連接到第二側面S2和第四側面S4 上的引線端子200。例如，I / O焊盤102和104可以包括數位焊盤，但不限於此。
根據非限制性實施例，例如，半導體晶粒10的I/O焊盤103可以沿著QFN封裝1的第三側面S3 設置，並且可以透過接合線133電連接到第三側面S3 上的引線端子200。例如，I/O焊盤103可以包括類比或射頻（radio-frequency，RF）焊盤，但不限於此。
如在第1圖和第2圖中可見，每個第三引線端子203包括用於導線接合的焊盤部分203p。焊盤部分203p連接到連接拉杆（connection tie-bar）203a。連接拉杆203a在外端（outer end）或側面（flank）具有暴露的基底金屬200a。連接拉杆203a在中間排的第二引線端子202與外排的第一引線端子201之間延伸（例如與第二引線端子202大致平行的方向延伸，當然未必一定平行）。同樣，中間排中的每個第二引線端子202由焊盤部分202p和連接拉杆202a組成，連接拉杆202a的外端或側面具有暴露的基底金屬200a。在一些實施例中，當從上方觀察時，連接拉杆202a可以是線性的或者非線性的。例如，連接拉杆202a可以是直線或直杆形狀的，或者連接拉杆202a可具有彎曲（cure）形狀或蛇形（serpentine）形狀，半導體封裝1上的連接拉桿也可以一些具有直杆形狀，另一些具有其他形狀例如彎曲或蛇形等形狀。第一引線端子201可以包括焊盤部分201p，可以具有或不具有連接拉杆的部分。
根據一個實施例，內排中的焊盤部分203p，中間排中的焊盤部分202p和外排中的第一引線端子201可以以交錯的方式佈置，其中交錯佈置可以指以上三者中任意兩者之間具有不重疊的部分（沿垂直於相應的側面的方向，例如垂直於第一側面S1 的方向），在完全交錯的示例中，以上三者中任意兩者之間可以均沒有重疊的部分，在部分交錯的示例中，以上三者中至少有兩者之間可以部分地重疊，例如焊盤部分203p與焊盤部分202p部分重疊，焊盤部分203p與第一引線端子201可以不具有重疊。根據非限制性實施例，例如，每個焊盤部分203p的表面積可以大於每個焊盤部分202p的表面積。根據非限制性實施例，例如，每個焊盤部分202p的表面積可以大於每個第一引線端子201的表面積。當從上方觀察時，連接拉杆203a比焊盤部分203p窄，連接拉杆202a比焊盤部分202p窄。
第3圖是示出在將QFN封裝安裝到系統板或PCB上之後，包括QFN封裝和與引線端子的切割端（外端）上的基底金屬直接接觸的焊料填角的電子系統的相關部分的示意性放大圖。如第3圖所示，電子系統（或稱為電子封裝、電子元件封裝、電子組件封裝等）P包括安裝在系統板或PCB 40上的如第1圖所示的多排鋸齒型QFN半導體封裝1。系統板或PCB 40具有上表面40a和與上表面40a相對的下表面40b。對應於晶粒附接焊盤210的焊盤410和對應於第三引線端子203的至少一個指狀焊盤413設置在上表面40a上。至少一個指狀焊盤413可以限定在阻焊膜430的開口430a內。根據非限制性實施例，例如，可以透過使用黏合層402將晶粒附接焊盤210黏附至焊盤410，但不限於此。根據非限制性實施例，例如，黏合層402可以是導電黏合層，例如環氧銀，但不限於此。根據非限制性實施例，例如，第三引線端子203透過焊膏（solder paste）420接合到至少一個指狀焊盤413。焊膏420的爬錫（Wicking，或稱為毛細、芯吸）至在第三引線端子203的切割端（外端）上的基底金屬200a，形成焊料填角420s，以使焊點（solder joint）的證據易於由檢查員或自動檢查工具檢查。具體而言，本實施例中由於引線端子的切割端（外端）為金屬材質（例如銅或合金等），使得半導體封裝安裝在PCB或系統板之後，半導體封裝與PCB或系統板之間的焊膏420可以延伸（或擠壓）出來並且易於附著於引線端子的外端，從而形成焊料填角420s。在先前技術中，在切割分割為單獨的半導體封裝時，從模塑料切割後，會有模塑料覆蓋引線端子的外端，無法暴露引線端子的外端（也無法從側面暴露引線端子和基底金屬）。因此先前技術中分割之後的半導體封裝由於模塑料覆蓋了引線端子的切割端（外端），使得目視無法查看到引線端子的切割端（外端）。而本發明中形成為單獨的半導體封裝之後，引線端子的切割端（外端）沒有模塑料覆蓋，因此在目視時可以查看到引線端子的切割端（外端），從而易於目視檢查（目視即可區分模塑料與引線端子的外端的基底金屬）。並且先前技術中由於模塑料覆蓋引線端子的外端，因此在將半導體封裝安裝在PCB或系統板之後，延伸（或擠壓）出來焊膏不易於附著於覆蓋引線端子的外端的模塑料（焊膏為金屬而模塑料是非金屬，兩者黏合不穩定，焊膏難以黏附），導致無法形成焊料填角或無法形成易於目視查看的焊料填角，因此先前技術中在將半導體封裝安裝到PCB或系統板之後，目視可能無法或難以查看到焊料填角，進而難以難以判斷半導體封裝安裝到PCB或系統板的電連接品質，影響生產效率和產量。而本發明中在將半導體封裝安裝到PCB或系統板之後，由於焊膏與引線端子均為金屬材質（例如分別包括錫和銅），因此延伸或擠壓出的焊膏可以穩定的附著在引線端子的外端的基底金屬（或引線端子的外端），從而形成易於目視的並且較明顯的焊料填角。因此，相對於先前技術，本發明具有如上所述顯著的優勢。
本實施例中，引線端子的外端可以與模塑料的側壁表面齊平，例如切割時一起切割，使得引線端子的外端可以與模塑料的側壁表面齊平。當然引線端子的外端也可以與半導體封裝的側壁表面齊平，其中半導體封裝的側壁表面可以是模塑料的側壁表面，或者半導體封裝的側壁表面可以是引線端子的外端的表面。引線端子的外端可以與模塑料的側壁表面齊平可以方便生產，提高生產效率，只需要一起切割即可形成（切割後即露出了引線端子的外端）；同時焊膏也可以易於附著於引線端子的外端的表面，以形成焊料填角，方便目視檢查。另外，本實施例中，引線端子的外端可以與模塑料的側壁表面不齊平（或者引線端子的切割端（外端）可以與半導體封裝的側壁表面不齊平），例如第3圖所示（第3圖為本發明其中一個示例的示意圖，引線端子的外端與模塑料的側壁表面的高低關係不限於第3圖所示），引線端子的切割端可以具有缺口或開口，該缺口或開口使得引線端子的外端相對於模塑料的側壁表面向內凹陷，也即引線端子的外端的表面低於模塑料的側壁表面。當半導體封裝的側壁表面可以是模塑料的側壁表面時，引線端子的外端的表面低於半導體封裝的側壁表面。當引線端子的外端的表面低於模塑料的側壁表面（或半導體封裝的側壁表面）時，在半導體封裝安裝在PCB或系統板之後，延伸（或擠壓）出來的焊膏420可以被容納於該缺口或開口處（由於引線端子的外端的表面低於模塑料的側壁表面而形成的缺口或開口），這樣使得延伸（或擠壓）出來的焊膏更加穩定的固定於引線端子的外端（具有容納擠壓出來的焊膏的缺口並且金屬之間更易黏合），使形成的焊料填角420s更加穩固，防止意外剝離或掉落等情況；並且該方式還具有以下優點：在切割引線端子之後，可能由於切割導致引線端子的金屬污染封裝的側面，導致相鄰的引線端子之間短路或其他問題。而本實施例在上述一起切割之後，通過進一步的製程步驟（例如蝕刻等）使得引線端子的外端的表面低於模塑料的側壁表面，在此過程中可以清除掉因切割而留下的污染切割端面的金屬，因此本實施例中通過引線端子的外端的表面低於模塑料的側壁表面來清理掉可能造成污染的金屬，避免這些金屬雜質污染而導致的短路等問題，提高半導體封裝生產的良率。
此外，本實施例中，引線端子的外端在不同的半導體封裝的側面可以指相應的引線端子的外端，例如在側面S1 可以是指第一引線端子201的外端、第二引線端子202的外端和第三引線端子203的外端，在側面S2 和S4 可以是指一引線端子201的外端和第二引線端子202的外端，在側面S3 可以是指第一引線端子201的外端。此外，本實施例中，每個側面也可以均只有一排引線端子，例如其他側面S1 、S2 、S4 也如側面S3 的那樣，當然也可以均有兩排或更多排的引線端子，在這種情況下，引線端子的外端也可以如上所述的那樣，例如暴露基底金屬，以及與模塑料的側壁表面齊平或低於模塑料的側壁表面；也就是說，無論半導體晶粒的周邊有多少排引線端子，引線端子的外端均可以如上所述的暴露基底金屬，以及與模塑料的側壁表面齊平或低於模塑料的側壁表面。每個側面設置的引線端子的排數可以相等或不等，半導體封裝的側面設置的引線端子的排數可以是例如一排、兩排、三排或更多排。例如，本實施例中半導體封裝包括：晶粒附接焊盤；安裝在該晶粒附接焊盤上的半導體晶粒；引線端子，佈置在該晶粒附接焊盤周圍（例如位於半導體晶粒任意一個或複數個側面上，在任意一個側面上可以具有一排或多排引線端子），並透過接合導線電連接到該半導體晶粒上的輸入/輸出焊盤；該引線端子的外端具有暴露的基底金屬。同樣的，引線端子的外端與該模塑料的側壁表面齊平；或者，引線端子的外端的表面低於該模塑料的側壁表面。並且也可以具有如上所述的半導體封裝的其他特點。
第4圖是根據本發明的一個實施例的具有多排引線端子的示例性鋸齒型QFN半導體封裝的示意性俯視圖，其中，相同的元件，層或區域由相同的數字標記表示。如第4圖所示，示例性的鋸齒型QFN半導體封裝2具有兩個晶粒附接焊盤210和510，在晶粒附接焊盤210和510上分別安裝有第一半導體晶粒10（半導體晶粒10）和第二半導體晶粒50。根據非限制性實施例，例如，第一半導體晶粒10可以包括處理器晶片或控制器，但不限於此。根據非限制性實施例，例如，第二半導體晶粒50可以包括WiFi（Wireless Fidelity，無線上網）和藍牙晶片組；在其他示例中，第二半導體晶粒50可以包括記憶體晶片組，諸如DRAM（動態隨機存取記憶體，Dynamic Random Access Memory，DRAM）記憶體或快閃（Flash）記憶體，但不限於此。
鋸齒型QFN半導體封裝2沿其四個側面S1 〜S4 具有三排引線配置，以實現更高的I/O密度（在0.63mm的間距（例如兩個引線之間的間距）下最多有242個導線數量）。值得注意的是，沿著第二半導體晶粒50的邊緣設置且直接面對第一半導體晶粒10的I/O焊盤501和沿著第一半導體晶粒10的邊緣設置且與直接面對第二半導體晶粒50的I/O焊盤101，均可以導線接合到第一半導體晶粒10和第二半導體晶粒50之間的中間焊盤530。例如第一半導體晶粒10的I/O焊盤101透過接合導線131電連接到中間焊盤530，第二半導體晶粒50的I/O焊盤501透過接合導線531電連接到中間焊盤530。
第5圖是示出了根據本發明的另一實施例的多晶片QFN封裝的示意性截面圖，其中，相同的元件，層或區域由相同的標號表示。根據另一實施例，在晶粒附接焊盤210的頂表面210a上可以有兩個或更多個半導體晶粒10。如第5圖所示，QFN封裝1a包括直接安裝在其頂部的第二半導體晶粒11。例如，根據非限制性實施例，第一半導體晶粒10（半導體晶粒10）可以包括處理器晶片或控制器，但不限於此。根據非限制性實施例，例如，第二半導體晶粒11可以包括WiFi和藍牙晶片組；在另一示例中，第二半導體晶粒11可以包括記憶體晶片組，諸如DRAM記憶體或快閃記憶體，但不限於此。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:QFN封裝； 10、50:半導體晶粒； 11:第二半導體晶粒； 101、102、103、104、501:I/O焊盤； 131、132、133、134、531:接合導線； 200:引線端子； 200a:基底金屬； 201:第一引線端子； 201p、202p、203p:焊盤部分； 202:第二引線端子； 202a、203a:連接拉杆； 203:第三引線端子； 210、510:晶粒附接焊盤； 220:接地環； 230:魚尾拉杆； 302:模塑料； S1、S2、S3、S4:側面； 40:PCB； 40a:上表面； 40b:下表面； 402:黏合層； 410:焊盤； 413:指狀焊盤； 420:焊膏； 420s:焊料填角； 430:阻焊膜； 430a:開口； 50:第二半導體晶粒； 530:中間焊盤。
透過閱讀後續的詳細描述和實施例可以更全面地理解本發明，本實施例參照附圖給出，其中： 第1圖是根據本發明的一個實施例的具有多排（multi-row）引線端子的示例性鋸齒型（sawed-type）QFN（四方平面無引線，quad flat non-leaded）半導體封裝的示意性俯視透視圖； 第2圖是沿第1圖中的虛線I-I'截取的示意性剖視圖； 第3圖是示出了在將QFN封裝安裝在系統板或PCB（印刷電路板，Printed circuit board）上之後的焊料填角（solder fillet）的示意性放大圖； 第4圖是根據本發明的一個實施例的具有多排引線端子的示例性鋸齒型QFN半導體封裝的示意性俯視圖； 第5圖是示出根據本發明的另一實施例的多晶片QFN封裝的示意性截面圖。
1:QFN封裝
10:半導體晶粒
101、102、103、104:I/O焊盤
131、132、133、134:接合導線
200:引線端子
200a:基底金屬
201:第一引線端子
201p、202p、203p:焊盤部分
202:第二引線端子
202a、203a:連接拉杆
203:第三引線端子
210:晶粒附接焊盤
220:接地環
230:魚尾拉杆
302:模塑料
S1、S2、S3、S4:側面

Claims (18)

  1. 一種半導體封裝，包括： 至少一個晶粒附接焊盤； 至少一個半導體晶粒，安裝在該至少一個晶粒附接焊盤上；以及 引線端子，佈置在該至少一個晶粒附接焊盤周圍，並透過接合導線電連接到該至少一個半導體晶粒上相應的輸入/輸出焊盤，其中，該引線端子包括沿著該半導體封裝的至少一個側面以三排結構佈置第一引線端子、第二引線端子和第三引線端子，並且其中該第一引線端子、第二引線端子和第三引線端子在相應的外端均具有暴露的基底金屬。
  2. 如申請專利範圍第1項所述的半導體封裝，其中，該外端與該半導體封裝的側壁表面齊平；或者，該外端的表面低於該半導體封裝的側壁表面。
  3. 如申請專利範圍第1項所述的半導體封裝，還包括： 模塑料，封裝該至少一個半導體晶粒、該至少一個晶粒附接焊盤、該接合導線和該引線端子。
  4. 如申請專利範圍第3項所述的半導體封裝，其中，該外端與該模塑料的側壁表面齊平；或者，該外端的表面低於該模塑料的側壁表面。
  5. 如申請專利範圍第1項所述的半導體封裝，其中，該第一引線端子、第二引線端子和第三引線端子以交錯的方式佈置。
  6. 如申請專利範圍第1項所述的半導體封裝，其中，該第三引線端子佈置在靠近該至少一個半導體晶粒上的該輸入/輸出焊盤的內排中，該第二引線端子佈置在中間排中，並且該第三引線端子佈置在外排中，其中該中間排位於該外排與內排之間。
  7. 如申請專利範圍第6項所述的半導體封裝，其中，該第三引線端子具有用於導線接合的焊盤部分和連接拉杆，其中，該外端設置在該連接拉杆的端部上。
  8. 如申請專利範圍第7項所述的半導體封裝，其中，該連接拉杆在該第二引線端子與該第一引線端子之間延伸。
  9. 如申請專利範圍第7項所述的半導體封裝，其中，該連接拉杆為線性形狀、彎曲形狀或蛇形形狀。
  10. 如申請專利範圍第7項所述的半導體封裝，其中，該第二引線端子具有用於導線接合的焊盤部分和連接拉杆。
  11. 申請專利範圍第10項所述的半導體封裝，其中，該第三引線端子的焊盤部分的表面積大於該第二引線端子的焊盤部分的表面積。
  12. 如申請專利範圍第1項所述的半導體封裝，還包括： 圍繞該晶粒附接焊盤的接地環。
  13. 如申請專利範圍第12項所述的半導體封裝，其中，該接地環被半蝕刻並且沒有從該半導體封裝的底部暴露。
  14. 一種半導體封裝，包括： 晶粒附接焊盤； 半導體晶粒，安裝在該晶粒附接焊盤上；以及 引線端子，佈置在該晶粒附接焊盤周圍，並透過接合導線電連接到該半導體晶粒上的輸入/輸出焊盤，其中，該引線端子的外端具有暴露的基底金屬。
  15. 一種電子系統，包括： 如申請專利範圍第1項至第14項任一一項所述的一種半導體封裝；以及 印刷電路板，其中該半導體封裝安裝在該印刷電路板上。
  16. 如申請專利範圍第15項所述的電子系統，其中，該印刷電路板包括：對應於該晶粒附接焊盤的焊盤；以及對應於該引線端子中的至少一個的至少一個指狀焊盤。
  17. 如申請專利範圍第16項所述的電子系統，其中，透過黏合層將該晶粒附接焊盤黏附至該焊盤。
  18. 如申請專利範圍第16項所述的電子系統，其中，該引線端子中的至少一個透過焊膏結合到該至少一個指狀焊盤，並且其中，該焊膏爬錫至該外端上的該基底金屬，形成焊料填角。
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