TW202041711A - Flexible circuit board for carrying chip and manufacturing method thereof - Google Patents

Abstract

The invention provides a flexible circuit board for carrying a chip. The manufacturing method thereof comprises the following steps: (a) providing a conductive copper layer having a wiring pattern on an insulating substrate; (b) forming a first solder resist layer partially covering the wiring pattern; (c) forming a first tin layer on the conductive copper layer using the first solder resist layer as a mask; (d) forming a second tin layer on the conductive copper layer using the first solder resist layer as a mask; and (e) forming a second solder resist layer partially covering the second tin layer and at least partially covering the first solder resist layer.

Description

Soft circuit substrate for carrying wafer and manufacturing method thereof

The present invention relates to flexible circuit substrates, and particularly to flexible circuit substrates capable of carrying semiconductor chips.

The flexible circuit substrates used to carry wafers are mostly reel-shaped films. In the industry, the combination of flexible circuit substrates and chips has various names according to different assembly modes, such as TCP (Tape Carrier Package) or COF (Chip On Film). Both TCP and COF use a flexible circuit substrate as the carrier of the packaged chip. The gold bumps (Gold Bμmp) on the chip are bonded to the inner lead of the copper wiring pattern on the flexible circuit board by thermocompression bonding. .

In order to connect the flexible substrate circuit with the gold bumps of the chip, there must be a gold-tin eutectic. The gold is provided by the gold bumps of the chip, and the tin is supplied by the tin formed on the surface of the inner pin. Therefore, the inner The surface of the pin is plated with a tin layer. In addition to the inner pins, the copper wiring pattern also has outer pins and other conductive terminals connected to other electronic components. These terminals usually also have a tin-plated layer. The non-lead area on the copper wiring pattern will be covered with solder resist ink to protect it.

Conventional flexible substrate circuits are prone to the following problems. One is that whiskers are formed on the surface of the tin-plated layer, which causes short circuits between adjacent circuits; the other is that the interface between the solder mask and the tin-plated layer produces cavities, which causes the circuit to break. Patent Document 1 (Japanese Patent JP3061613) discloses a scheme in the copper wiring pattern A thin tin-plated layer (a) is formed on the entire surface, and then solder resist ink is applied to the non-lead area of the wiring pattern, and then a thick tin-plated layer (b) is formed on the lead area. Patent Document 1 believes that the thin tin-plated layer (a) formed on the entire surface of the copper wiring pattern can prevent the generation of cavities and the thick tin-plated layer (b) can prevent the generation of whiskers. Patent Document 2 (Taiwan Patent TW531864) discloses another method, which is to sequentially form a first solder mask on the non-lead area, form a thin tin layer on the lead area, and then form a second solder mask ink to cover the first solder mask. At the junction of the ink and the thin tin layer, and finally a thick tin plating layer is formed on the thin tin layer.

After research, the inventor of this case found that the above-mentioned conventional technology still has many problems in practice. For example, Patent Document 1 has a thin tin-plated layer formed on the entire surface of the copper wiring pattern, which is disadvantageous for products that need to be bent, because the hardness of the tin-plated layer is usually high. Moreover, both Patent Document 1 and Patent Document 2 teach that a thick tin-plated layer is formed after the solder resist ink is finally applied. Therefore, the solder resist ink on the top layer will still be immersed in the tin plating bath for a period of time, especially for thick tin plating. The time is longer, which increases the chance of cavities at the interface between the top solder mask and the thick tin layer. In addition, Patent Document 2 has the process of applying solder resist ink twice before entering the tin bath, which results in high costs for cleaning the tin bath contaminated by the solder resist ink. In addition, patent document 2 teaches two solder resist inks and two tin plating staggered processes. In fact, it is easy to confuse the production line arrangement.

In view of the foregoing, in one aspect, the present invention proposes a novel method for manufacturing a flexible circuit substrate, which does not require two solder mask inks and two tin plating processes. At the same time, the present invention also coats the top solder resist ink after the final tin layer is completed to prevent the top solder resist ink from being immersed in the tin plating tank.

According to one embodiment, the present invention provides a method for manufacturing a flexible circuit substrate for carrying a chip, which sequentially includes the following steps: (a) providing a conductive copper layer with a wiring pattern on an insulating substrate; (b) forming A first solder resist layer partially covers the wiring pattern; (c) using the first solder resist layer as a mask to form a first tin layer on the conductive copper layer; (d) using the first solder resist layer as Mask forming a second tin layer on the first tin layer; and (e) forming a second solder mask to partially cover the second tin layer and at least partially to cover the first solder mask.

According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein there is no step of forming a solder mask between step (c) and step (d).

According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein the first solder mask layer at least partially covers the second tin layer through the step (d).

According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein the interface between the first tin layer and the second tin layer is made conformal to the interface between the first tin layer and the conductive copper layer through the step (d) .

According to an embodiment, the present invention provides the aforementioned manufacturing method, wherein the second solder mask is not in contact with the tin plating solution.

In another aspect, the present invention provides a method for manufacturing a flexible circuit substrate, which reduces the coating area of the first solder mask layer or the second solder mask layer to reduce the contamination of the solder bath with the solder mask ink. For example, the first solder mask can be selectively coated only on the area where the flexible circuit substrate will bend when the product is applied; or the second solder mask can selectively cover the outer edge of the first solder mask , Without the need to completely cover the first solder mask.

According to one embodiment, the present invention provides a method for manufacturing a flexible circuit substrate for carrying a chip, which sequentially includes the following steps: (a) providing a conductive copper layer with a wiring pattern on an insulating substrate, wherein the wiring pattern It has a test lead area, an inner lead area and an outer lead area; (b) a first solder resist layer is formed to partially cover the wiring pattern, and the first solder resist layer does not cover the test lead The wiring pattern between the foot area and the inner lead area; (c) using the first solder mask as a mask to form a first tin layer on the conductive copper layer; (d) using the first solder mask Forming a second tin layer on the first tin layer for the mask; and (e) forming a second solder resist layer to partially cover the second tin layer and at least partially to cover the first solder resist layer.

According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein in step (e) the second solder mask does not completely cover the first solder mask.

In another aspect, the present invention provides a method for manufacturing a flexible circuit substrate, which enables the second tin layer to have a roughened tin surface. The roughened tin surface can provide a larger surface area. When the flexible circuit board is externally connected to other electronic components, the roughened tin surface of the outer lead area can increase the bonding area with the anisotropic conductive film (ACF), thereby making the flexible circuit board and the electronic device more closely fit .

According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein the step (a) further comprises roughening the conductive copper layer so that the conductive copper layer has a roughened copper surface, wherein the roughened copper surface can be The conductive copper layer is formed by treating the conductive copper layer with a chemical solution. Since the tin layer is plated on the roughened copper surface, the first tin layer and the second tin layer will also have roughened surfaces. In this embodiment, the second tin layer has a roughened tin surface, and the surface roughness Rz of the roughened tin surface is in the range of 0.045~0.5μm, preferably in the range of 0.06~0.35μm, more preferably in the range of 0.1~ 0.3μm.

In another aspect, the present invention further includes various structures of flexible circuit substrates formed by the various methods described above.

10‧‧‧Soft circuit board semi-finished products

100‧‧‧Insulating base material

101‧‧‧Transmission hole

110‧‧‧Conductive copper layer

P‧‧‧Wiring pattern

1B‧‧‧Reference Picture

Lo‧‧‧Outer pin area

Ps‧‧‧Non-lead area

Ln‧‧‧Inner pin area

Lt‧‧‧Test pin area

121‧‧‧First solder mask

121a‧‧‧First Edge

131‧‧‧First tin layer

131a‧‧‧First side

Iss‧‧‧Interface

Isc‧‧‧Interface

132‧‧‧Second tin layer

122‧‧‧Second solder mask

122a‧‧‧Second Edge

132a‧‧‧Second side

X‧‧‧Horizontal distance

Y‧‧‧Horizontal distance

161‧‧‧Tin layer

161a‧‧‧Vertical interface

162‧‧‧Solder Protection Layer

162a‧‧‧Edge

163‧‧‧Exposed part

Z‧‧‧Horizontal distance

110’‧‧‧Conductive copper layer

132’‧‧‧Second tin layer

131’‧‧‧The first tin layer

701‧‧‧Roughened copper surface

702‧‧‧Roughened tin surface

703‧‧‧Roughened tin surface

1A is a schematic top view of a semi-finished flexible circuit substrate according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view of a specific area in the semi-finished product of Fig. 1A.

1B and FIGS. 2 to 5 show schematic cross-sectional views of various steps in the manufacturing process of a flexible circuit substrate according to a first embodiment of the present invention.

FIG. 6 is a schematic structural diagram of a flexible circuit substrate according to an embodiment of the present invention.

FIG. 7 is a schematic structural diagram of a flexible circuit substrate according to a second embodiment of the present invention.

Hereinafter, the preferred embodiments of the present invention will be demonstrated with reference to the accompanying drawings. In order to avoid obscuring the content of the present invention, the following description also omits conventional components, related materials, and related processing techniques. At the same time, in order to clearly illustrate the present invention, the various elements in the accompanying drawings may not be drawn according to actual sizes or relative proportions.

Method for manufacturing soft circuit substrate of the present invention

According to the first embodiment, the method for manufacturing a flexible circuit substrate for carrying a chip of the present invention sequentially includes: step (a) providing a conductive copper layer with a wiring pattern on an insulating substrate; step (b) forming a The first solder resist layer partially covers the wiring pattern; step (c) uses the first solder resist layer as a mask to form a first tin layer on the conductive copper layer; step (d) uses the first solder resist layer Forming a second tin layer on the first tin layer for the mask; and step (e) forming a second solder resist layer partially covering the second tin layer and at least partially covering the first solder resist layer.

Step (a) provides a conductive copper layer with a wiring pattern on an insulating substrate.

FIG. 1A is a schematic top view of the semi-finished flexible circuit substrate 10 of the present invention. Referring to FIG. 1A, a plurality of wiring patterns P composed of conductive copper layers 110 are continuously formed on one surface of the thin-film strip-shaped insulating base material 100 of the semi-finished flexible circuit substrate 10. The insulating base 100 has a plurality of driving holes 101 for transfer on the upper and lower sides. The conductive copper layer 110 (or the wiring pattern P) defines a non-lead area Ps (the part framed by a dashed line), and this area will be subsequently covered by a solder mask to protect the circuit. The area outside the non-lead area Ps of the wiring pattern P is the lead area, which can be further divided into an inner lead area Ln, an outer lead area Lo, and a test lead area Lt that exists as needed. The inner lead area Ln will be The chip is connected, the outer pin area Lo will be connected to the circuit board or other electronic devices, and the test pin area Lt is used to connect with the measuring instrument to test the quality of the packaged chip. FIG. 1B is a schematic cross-sectional view of the point indicated by arrow 1B in FIG. 1A (ie, one of the lines of the wiring pattern P). Referring to FIG. 1B, it can be clearly understood that the conductive copper layer 110 is located on the insulating substrate 100. The insulating substrate 100 can be made of materials that are soft and have chemical resistance and heat resistance, such as polyester, polyamide, polyimide, and the like. The thickness of the insulating substrate 100 is generally 12 to 85 μm, preferably 20 to 50μm. The conductive copper layer 110 with the wiring pattern P is formed on the insulating substrate 100 by a conventional photolithography method. The thickness of the conductive copper layer 110 is, for example, 2 to 20 μm, preferably 5 to 12 μm.

Step (b) forming a first solder resist layer partially covering the wiring pattern.

1A and FIG. 2, a first solder mask 121 is formed to at least partially cover the wiring pattern P, for example, to cover a part or all of the non-lead area Ps. In a preferred embodiment, the first solder mask 121 only needs to be applied to certain specific areas of the non-lead area Ps, for example, it only needs to be applied to the bending area generated at the back end of the flexible circuit substrate product. The actual position of the bending area varies depending on the characteristics of the back-end application product. The area between the inner lead area Ln and the outer lead area Lo is the existing common bending area. Therefore, in the preferred embodiment of the present invention, the first solder mask 121 does not cover the non-lead area Ps between the test lead area Lt and the inner lead area Ln, but the present invention is not limited to this. The present invention also has an embodiment in which the first solder mask 121 completely covers all the non-lead regions Ps. The conventional epoxy resin (o-Cresol Novalac/Phenol/DGEBA) type ink or other suitable ink can be used to complete this step by screen printing technology. The thickness of the first solder mask 121 may be in the range of 3 to 15 μm.

Step (c) using the first solder mask as a mask to form a first tin layer on the conductive copper layer.

Referring to FIG. 3, a first tin layer 131 is formed on the conductive copper layer 110 using the first solder mask 121 as a mask. The first tin layer 131 is formed by a conventional electroless plating (ie, chemical plating) technique. For example, the semi-finished product formed in step (b) is immersed in a tin bath containing sulfuric acid, potassium persulfate, or tin fluoroboride tin plating solution for a predetermined period of time, washed with water and blown dry, and then put into an oven for heat treatment. In this step, the first tin layer 131 is not only plated on the surface of the conductive copper layer 110 that is not covered by the first solder mask 121, but also the tin plating solution can intrude into the area under the first edge 121a of the first solder mask 121. The conductive copper layer 110 thus forms a structure in which the first edge 121 a of the first solder mask layer 121 covers the first side 131 a of the first tin layer 131. The thickness of the first tin layer 131 may be in the range of 0.02 to 0.16 μm, and the thickness of the first tin layer 131 in the preferred embodiment is 0.10 μm.

Step (d): use the first solder mask as a mask to form a second tin layer on the first On the tin layer.

Referring to FIG. 4, a second tin layer 133 is formed on the first tin layer 131 using the first solder mask layer 121 as a mask. Preferably, there is no additional step of forming a solder mask between step (c) and step (d). As in step (c), the second solder resist layer 132 may be formed by a conventional electroless plating (ie, chemical plating) technique. For example, the semi-finished product formed in step (c) is immersed in a tin bath containing sulfuric acid, potassium persulfate, or tin fluoroboride tin plating solution for a predetermined period of time, washed with water and then blown dry, and then put into an oven for heat treatment. Step (c) The tin-copper alloy layer obtained by the first tin plating will generate Cu ₃ Sn through high temperature heat treatment, which can slow down the formation and diffusion of Cu ₆ Sn ₅ in the tin layer produced by the second tin plating in step (d) Speed, thereby slowing down the loss rate of the pure tin layer, improving the yield of the eutectic bonding between the circuit and the wafer, and avoiding the generation of tin whiskers. In this step, the tin plating solution can be further penetrated under the first edge 121a of the first solder resist layer 121 to form the first edge 121a of the first solder resist layer 121 to cover the first side 132a of the second tin layer 132 Structure. The thickness of the second tin layer 132 can be in the range of 0.12 to 0.5 μm, and the thickness of the first tin layer 132 in a preferred embodiment is 0.28 μm. Because both steps (c) and (d) use electroless plating (ie, chemical plating) technology, and both use the first solder mask 121 as a mask, the first tin layer 131 will be covered by the second tin in step (d) The layer 132 advances to the area with high copper density, so that the interface Iss between the first tin layer 131 and the second tin layer 132 and the interface Isc between the first tin layer 131 and the conductive copper layer 110 are conformal.

Step (e) forming a second solder resist layer partially covering the second tin layer and at least partially covering the first solder resist layer.

Referring to FIG. 5, a second solder resist layer 122 is formed to partially cover the second tin layer 132 and at least partially cover the first solder resist layer 121. Preferably, in this step, the second solder mask layer 122 is formed to at least cover the contact surface formed by the second tin layer 132 and the first solder mask layer 121 in the step (d). In step (d), the first solder resist layer 121 is immersed in the tin bath, which may weaken the contact surface between the first solder resist layer 121 and the second tin layer 132, so the second solder resist layer 122 covers this contact surface It can prevent the solder mask from peeling off the tin layer. The conventional epoxy resin (o-Cresol Novalac/Phenol/DGEBA type) type ink or other suitable ink can be used to complete this step by screen printing technology. The thickness of the second solder mask 122 may be in the range of 3 to 20 μm. In this embodiment, the second solder mask layer 122 has a full effect on the non-lead area Ps The zone printing therefore completely covers the first solder mask 121, but the present invention is not limited to this. The present invention also includes an embodiment in which the second solder resist layer 122 only partially covers the first solder resist layer 121 (only the outer edge thereof) and the second tin layer 132 partially covers.

Structure of soft circuit substrate of the present invention

1A and 5 at the same time, in the first embodiment, the flexible circuit substrate for carrying a chip of the present invention includes a conductive copper layer 110 with a wiring pattern P on the insulating substrate 100; the first tin layer 131 is located on the conductive copper layer 110 Above; the second tin layer 132 is located above the first tin layer 131; the first solder resist layer 121 covers the conductive copper layer 110 that is not covered by the first tin layer 131 and the second tin layer 132, and the first solder resist layer 121 part And the second solder resist layer 122 partially covers the second tin layer 132 and at least partially covers the first solder resist layer 121.

In another embodiment, referring to FIG. 5, the present invention provides a flexible circuit substrate for carrying a chip, wherein the first solder mask 121 has a first edge 121 a in contact with the second tin layer 132.

In another embodiment, referring to FIG. 5, the present invention provides a flexible circuit substrate for carrying a chip, wherein the first tin layer 131 has a first longitudinal interface 131a in contact with the conductive copper layer 110, and the first solder mask 121 has a first The edge 121a contacts the second tin layer 132, and the lateral distance X between the first longitudinal interface 131a and the first edge 121a is greater than the thickness of the first tin layer 131.

In another embodiment, referring to FIG. 5, the present invention provides a flexible circuit substrate for carrying a chip, wherein the second tin layer 132 has a second longitudinal interface 132a in contact with the first tin layer 131, and the first solder mask 121 covers The second longitudinal interface 132a.

In another embodiment, referring to FIG. 5, the present invention provides a flexible circuit substrate for carrying a chip, wherein the second tin layer 132 has a second longitudinal interface 132a to contact the first tin layer 131, and the second solder mask 122 has a The two edges 122a contact the second tin layer 132, and the lateral distance Y between the second longitudinal interface 132a and the second edge 122a is greater than the thickness of the second tin layer 132.

In another embodiment, referring to FIG. 5, the present invention provides a flexible circuit substrate for carrying a chip, wherein the interface Iss between the first tin layer 131 and the second tin layer 132 is conformal to the first tin layer 131 and the conductive copper layer 110 interface Isc.

6 shows that when the first tin layer 131 and the second tin layer 132 are regarded as the tin layer 161, and the first solder resist layer 121 and the second solder resist layer 122 are regarded as the solder resist layer 162, the present invention is used The structural feature of the flexible circuit substrate carrying the chip is that it includes a conductive copper layer 110 with a wiring pattern P disposed on the insulating substrate 100; a tin layer 161 is located on the conductive copper layer 110, and the conductive copper layer 110 has a tin layer 161 An exposed part 163 covered; and a solder mask 162 covering the exposed part and partially covering the tin layer 161, wherein the tin layer 161 has a longitudinal interface 161a in contact with the conductive copper layer 110, and the solder mask 162 has an edge 162a in contact with tin In the layer 161, the lateral distance Z between the longitudinal interface 161a and the edge 162a is greater than the thickness of the tin layer 161. The thickness of the solder mask ranges from 6 μm to 35 μm. The thickness of the tin layer ranges from 0.14 μm to 0.66 μm. In addition, the present invention also has an embodiment that only performs step (c) without step (d). In this example, the thickness of the tin layer ranges from 0.1 μm to 0.6 μm.

The present invention has a second embodiment, which is different from the first embodiment in that step (a) further includes the step of "roughening the conductive copper layer before tin plating" so that the conductive copper layer has a roughened copper surface. The remaining steps are all The same as the first embodiment. The roughening of the conductive copper layer can be accomplished using any suitable method. For example, after patterning the conductive copper layer 110 to form the wiring pattern P, the conductive copper layer (wiring pattern P) can be formed by treating the conductive copper layer (wiring pattern P) with a chemical solution. In this embodiment, the chemical solution can be, for example, a potassium persulfate (K ₂ S ₂ O ₈ ) solution with a suitable concentration of 30-40 g/L, and a sulfuric acid or hydrochloric acid solution with a suitable concentration of 20-30 g/L. The conductive copper layer (wiring pattern P) can be immersed in the chemical solution for 10 to 30 seconds at room temperature. The longer the contact time with the chemical solution, the greater the surface roughness. FIG. 7 is a schematic diagram of the structure of the tin plating and solder mask layer of the second embodiment. Plating tin on the roughened copper surface will also cause the tin surface to produce a roughened structure similar to the roughened copper surface. As shown in the figure, the roughened conductive copper layer 110' has a roughened copper surface 701, and the subsequently formed first tin layer 131' and second tin layer 132' all have similar roughened surfaces, such as roughened tin Faces 702 and 703. As mentioned above, roughening the tin surface can provide a larger surface area. When the flexible circuit board is externally connected to other electronic components, the roughened tin surface of the outer lead area can increase the bonding area with the anisotropic conductive film (ACF), thereby making the flexible circuit board and the electronic device more closely fit . Preferably, the surface roughness Rz of the roughened tin surface 703 of the second tin layer 132' ranges from 0.045 to 0.5 μm, preferably from 0.06 to 0.35 μm, and more preferably from 0.1 to 0.3 μm. The surface roughness Rz is measured by cutting the tin-plated sample into a size of approximately 5cm×5cm, and measuring it with a non-contact shape measurement laser microscope (KEYENCE Taiwan’s model VK-X100). When measuring, use the laser spot diameter of about 1μm, the objective lens magnification is set to 10X, the field of view is 1350μm x 1012μm, and the objective lens magnification is set to 20X, the field of view is 675μm x 506μm, the scanning time is about 10-20 seconds, and the line pitch is set to 2μm. .

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit of the present invention should be included in the following Within the scope of patent application.

100‧‧‧Insulating base material

110‧‧‧Conductive copper layer

121‧‧‧First solder mask

121a‧‧‧First Edge

122‧‧‧Second solder mask

122a‧‧‧Second Edge

131‧‧‧First tin layer

131a‧‧‧First side

132‧‧‧Second solder mask

132a‧‧‧First side

Ps‧‧‧Non-lead area

Iss‧‧‧Interface

Isc‧‧‧Interface

X‧‧‧Horizontal distance

Y‧‧‧Horizontal distance

Claims (23)

A method for manufacturing a flexible circuit substrate for carrying a chip, which sequentially includes the following steps: (a) providing a conductive copper layer with a wiring pattern on an insulating substrate; (b) forming a first solder mask partially Cover the wiring pattern; (c) use the first solder mask as a mask to form a first tin layer on the conductive copper layer; (d) use the first solder mask as a mask to form a second tin layer On the first tin layer; and (e) forming a second solder resist layer partially covering the second tin layer and at least partially covering the first solder resist layer. The manufacturing method according to claim 1, wherein there is no step of forming a solder mask between step (c) and step (d). The manufacturing method according to claim 1, wherein the first solder resist layer at least partially covers the second tin layer through the step (d). The manufacturing method according to claim 1, wherein through the step (d), the interface between the first tin layer and the second tin layer is made conformal to the interface between the first tin layer and the conductive copper layer. The method for manufacturing a flexible circuit substrate according to claim 1, wherein the wiring pattern has a test area, an inner lead area and an outer lead area, and in the step (b) the first solder mask is not covered with the dielectric The wiring pattern between the test area and the inner lead area. The method for manufacturing a flexible circuit substrate according to claim 1, wherein the step (c) or the step (b) respectively further includes a heat treatment step. The method for manufacturing a flexible circuit substrate according to claim 1, wherein in the step (e), the second solder mask does not completely cover the first solder mask. The manufacturing method according to claim 1, wherein the step (a) further comprises roughening the conductive copper layer so that the conductive copper layer has a roughened copper surface. The manufacturing method according to claim 8, wherein the roughened copper surface is formed by treating the conductive copper layer with a chemical solution. The manufacturing method according to claim 8, wherein the second tin layer has a roughened tin surface, and the surface roughness Rz of the roughened tin surface is in the range of 0.045 to 0.5 μm, preferably in the range of 0.06 to 0.35 μm, A more preferable range is 0.1~0.3μm. A flexible circuit substrate for carrying a chip, comprising: a conductive copper layer with a wiring pattern on an insulating substrate; a first tin layer on the conductive copper layer; a second tin layer on the first tin layer Above; a first solder mask layer covers the conductive copper layer not covered by the first tin layer and the second tin layer, and the first solder mask layer partially covers the second tin layer; and a second solder mask The solder layer partially covers the second tin layer and at least partially covers the first solder resist layer. The flexible circuit substrate according to claim 11, wherein the first solder mask layer has a first edge contacting the second tin layer. The flexible circuit substrate according to claim 11, wherein the first tin layer has a first longitudinal interface contacting the conductive copper layer, the first solder resist layer has a first edge contacting the second tin layer, and the first The lateral distance between the longitudinal interface and the first edge is greater than the thickness of the first tin layer. The flexible circuit substrate according to claim 11, wherein the second tin layer has a second longitudinal interface contacting the first tin layer, and the first solder mask layer covers the second longitudinal interface. The flexible circuit substrate according to claim 11, wherein the second tin layer has a second longitudinal interface contacting the first tin layer, the second solder resist layer has a second edge contacting the second tin layer, and the first tin layer The lateral distance between the two longitudinal interfaces and the two edges is greater than the thickness of the second tin layer. The flexible circuit substrate according to claim 11, wherein the interface between the first tin layer and the second tin layer is conformal to the interface between the first tin layer and the conductive copper layer. The flexible circuit substrate according to claim 11, wherein the wiring pattern has a test pin area, an inner pin area and an outer pin area, and the first solder mask does not cover between the test pin area and The wiring pattern between the inner lead regions. The flexible circuit substrate according to claim 11, wherein the conductive copper layer has a roughened copper surface. The flexible circuit substrate of claim 11, wherein the second tin layer has a roughened tin surface, and the surface roughness Rz of the roughened tin surface is in the range of 0.045~0.5μm, preferably in the range of 0.06~0.35μm , The more preferable range is 0.1~0.3μm. A flexible circuit substrate for carrying a chip, comprising: a conductive copper layer with a wiring pattern arranged on an insulating substrate; a tin layer located above the conductive copper layer, wherein the conductive copper layer is not covered by the tin layer An exposed part of the cover; and A solder mask layer covers the exposed portion and partially covers the tin layer, wherein the tin layer has a longitudinal interface contacting the conductive copper layer, the solder mask layer has an edge contacting the tin layer, wherein the longitudinal interface and the edge The lateral distance is greater than the thickness of the tin layer. The flexible circuit substrate according to claim 20, wherein the thickness of the solder resist layer ranges from 6 μm to 35 μm. The flexible circuit substrate according to claim 20, wherein the thickness of the tin layer ranges from 0.1 μm to 0.6 μm. The flexible circuit substrate according to claim 20, wherein the tin layer has a roughened tin surface, and the surface roughness Rz of the roughened tin surface is in the range of 0.045~0.5μm, preferably in the range of 0.06~0.35μm, more The preferred range is 0.1~0.3μm.

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