TW202040783A - 封裝結構及其製造方法 - Google Patents
封裝結構及其製造方法 Download PDFInfo
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- TW202040783A TW202040783A TW108125362A TW108125362A TW202040783A TW 202040783 A TW202040783 A TW 202040783A TW 108125362 A TW108125362 A TW 108125362A TW 108125362 A TW108125362 A TW 108125362A TW 202040783 A TW202040783 A TW 202040783A
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Abstract
一種封裝結構包括半導體晶粒、重佈線路結構及連接墊。重佈線路結構位於半導體晶粒上且電連接到半導體晶粒。連接墊嵌入在重佈線路結構中且電連接到重佈線路結構,且連接墊包括阻障膜及位於阻障膜之下的導電圖案,其中阻障膜的表面與重佈線路結構的外表面實質上齊平。
Description
半導體裝置及積體電路通常是在單個半導體晶圓上製造。晶圓的晶粒可以晶圓級(wafer level)來與其他半導體裝置或晶粒一起進行處理及封裝,且已針對晶圓級封裝(wafer level packaging)開發了各種技術。另外,這種封裝可在切割之後被進一步整合到半導體基底或載體。因此,每一個封裝內的導電端子與內部元件(例如,重佈線路結構)之間的電連接的可靠性變得重要。
以下揭露內容提供用於實施所提供標的物的不同特徵的許多不同實施例或實例。下文描述組件及佈置的特定實例以簡化本揭露。當然,此等特定實例僅為實例且不意欲為限制性的。舉例而言,在以下描述中,第一特徵在第二特徵上方或第二特徵上方上形成可包含第一特徵與第二特徵直接接觸地形成的實施例,且亦可包含可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的,且本身並不指示所論述各種實施例與/或組態之間的關係。
此外,為易於描述,可在本文中使用諸如「在…下面(beneath)」、「在…下方(below)」、「下部(lower)」、「在…上面(over)」、「在…上方(above)」、「上部(upper)」及類似者的空間相對術語來描述如諸圖中所示出的一個元件或特徵與另一元件或特徵的關係。除諸圖中所描繪的定向以外,空間相對術語意欲涵蓋元件於使用或操作中的不同定向。 裝置可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
另外,為易於說明,本文中可使用例如“第一”、“第二”、“第三”等用語來闡述圖中所示的相似或不同的元件或特徵,且這些用語可依據存在的次序或說明的上下文而互換地使用。
還可包括其他特徵及製程。舉例來說,可包括測試結構,以說明對三維(three-dimensional,3D)封裝或三維積體電路(three-dimensional integrated circuit,3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試墊,以使得能夠對3D封裝或3DIC進行測試、對探針和/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外,本文中所公開的結構及方法可結合包括對已知良好晶粒(known good die)進行中間驗證的測試方法來使用,以提高良率(yield)並降低成本。
圖1至圖14示出根據本公開一些實施例的封裝結構的製造方法中的各種階段的示意性剖視圖。圖15示出圖14中所繪示封裝結構的一部分的放大示意性剖視圖,其中所述封裝結構的所述一部分是由圖14中所示虛線框E1標明。在一些實施例中,所述製造方法是晶圓級封裝製程的一部分。應注意,本文中所述的製程步驟涵蓋用於製作封裝結構的製造製程的一部分。實施例旨在提供進一步的解釋,而不是用於限制本公開的範圍。在圖1至圖14中,示出多於一個(半導體)晶片或晶粒以代表晶圓的多個(半導體)晶片或晶粒,且示出一個(半導體)封裝結構以代表在(半導體)製造方法之後獲得的多個(半導體)封裝結構,然而本公開不限於此。在其他實施例中,示出一個或多於一個(半導體)晶片或晶粒以代表晶圓的多個(半導體)晶片或晶粒,且示出一個或多於一個(半導體)封裝以代表在(半導體)製造方法之後獲得的多個(半導體)封裝結構,本公開不限於此。
參照圖1,在一些實施例中,提供載體112。在一些實施例中,載體112可為玻璃載體或任何適合於為半導體封裝的製造方法承載半導體晶圓或重構晶圓(reconstituted wafer)的載體。在一些實施例中,載體112塗布有剝離層114(如圖1中所示)。剝離層114的材料可為任何適合於對載體112進行接合及將載體112從安置在載體112上的上方層或任何晶圓剝離的材料。
在一些實施例中,剝離層114可包括由介電材料製成的介電材料層,所述介電材料包括任何適合的聚合物系介電材料(例如,苯並環丁烯(benzocyclobutene,BCB)、聚苯並噁唑(polybenzoxazole,PBO))。在替代實施例中,剝離層114可包括由例如光熱轉換(light-to-heat-conversion,LTHC)釋放塗布膜等環氧樹脂系熱釋放材料製成的介電材料層,環氧樹脂系熱釋放材料會在受熱時失去其粘著性質。在又一替代實施例中,剝離層114可包括由紫外(ultra-violet,UV)膠製成的介電材料層,UV膠會在被暴露至UV光時失去其粘著性質。在某些實施例中,剝離層114可作為液體進行分配(dispense)並進行固化,或者可為被疊層到載體112上的疊層體膜(laminate film),或者可為類似形式。與接觸載體112的底表面相對的剝離層114的頂表面可被整平(levelled)且可具有高共面度(high degree of coplanarity)。在某些實施例中,剝離層114為例如具有良好耐化學性的光熱轉換層,且這種層能夠透過施加雷射輻照(laser irradiation)實現從載體112進行室溫剝離,然而本公開不限於此。
在替代實施例中,可在剝離層114上塗布緩衝層(圖中未示出),其中剝離層114夾置在緩衝層與載體112之間,且緩衝層的頂表面可進一步提供高共面度。在一些實施例中,緩衝層可為介電材料層。在一些實施例中,緩衝層可為聚合物層,所述聚合物層是由聚醯亞胺(polyimide,PI)、PBO、BCB或任何其他適合的聚合物系介電材料製成。在一些實施例中,緩衝層可為味之素構成膜(Ajinomoto Buildup Film,ABF)、阻焊膜(Solder Resist film,SR)等。換句話說,緩衝層是可選的且可基於需要及設計佈局而被省略;本公開不限於此。
繼續參照圖1,在一些實施例中,在剝離層114上及載體112之上形成晶種層材料122a。舉例來說,晶種層材料122a以由金屬或金屬合金材料製成的毯覆層(blanket layer)的方式共形地安置在剝離層114上,本公開不限於此。在一些實施例中,晶種層材料122a可為單個層或包括由不同材料形成的多個子層(sub-layers)的複合層。在一些實施例中,晶種層材料122a可包含鈦、銅、鉬、鎢、氮化鈦、鎢化鈦、其組合等。舉例來說,晶種層材料122a可包括鈦層以及位於鈦層之上的銅層。在一些實施例中,晶種層材料122a是透過化學氣相沉積(chemical vapor deposition,CVD)、物理氣相沉積(physical vapor deposition,PVD)、原子層沉積(atomic layer deposition,ALD)、高密度等離子體化學氣相沉積(high density plasma CVD,HDPCVD)或其組合形成。在本說明通篇中,用語“銅”旨在包括實質上純的元素銅、含有不可避免的雜質的銅以及含有少量例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等元素的銅合金等。
在一些實施例中,如圖1中所示,在晶種層材料122a上及載體112之上形成多個導電墊124。在一些實施例中,導電墊124可為透過電鍍(electroplating)或沉積(deposition)形成的圖案化鋁層(例如,鋁墊)。舉例來說,如圖1中所示,導電墊124沿堆疊方向(例如,方向Z)直接安置在晶種層材料122a上且沿X-Y平面分佈在晶種層材料122a的表面之上。舉例來說,方向X及方向Y垂直於方向Z,且方向X與方向Y不同。導電墊124的數目不限於此,且可基於需要來指定及選擇。舉例來說,導電墊124的數目可為一個或多於一個。如圖1中所示,導電墊124彼此分離且彼此間隔開。
參照圖2,在一些實施例中,接著透過移除未被導電墊124覆蓋的晶種層材料122a的部分而分別形成直接位於導電墊124之下的多個阻障晶種圖案122。在一些實施例中,使用導電墊124作為罩幕,透過蝕刻製程(etching process)移除未被導電墊124覆蓋的晶種層材料122a的部分來形成阻障晶種圖案122。舉例來說,蝕刻製程可包括幹法蝕刻(dry etching)、濕法蝕刻(wet etching)或其組合。換句話說,例如使用導電墊124(用作蝕刻罩幕)蝕刻晶種層材料122a以形成阻障晶種圖案122。由此,沿堆疊方向(例如,方向Z)在載體112上的垂直投影中,一個導電墊124的投影面積與直接位於所述一個導電墊124之下的相應一個阻障晶種圖案122的投影面積實質上相同。也就是說,在方向Z上,導電墊124各自與相應一個阻障晶種圖案122完全交疊。在一些實施例中,導電墊124中的每一者的側壁與阻障晶種圖案122中相應一者的側壁對準。在本文中,阻障晶種圖案122的數目不受限制,且可基於需要來指定及選擇,其中阻障晶種圖案122的數目可透過控制導電墊124的數目來調節。舉例來說,如圖2中所示,阻障晶種圖案122各自電連接到導電墊124中相應的一者。在本公開中,阻障晶種圖案122中的每一者及與其物理地連接的相應一個導電墊124被一起稱作連接墊120。
參照圖3至圖8,在一些實施例中,在連接墊120上及載體112之上形成重佈線路結構130。在一些實施例中,重佈線路結構130包括交替排列的一個或多於一個介電層132(例如,介電層132-1、介電層132-2及介電層132-3)以及一個或多於一個圖案化導電層134(例如,圖案化導電層134-1、圖案化導電層134-2及圖案化導電層134-3)。然而,在本公開中,介電層132的數目及圖案化導電層134的數目不限於圖3至圖8。舉例來說,介電層132的數目及圖案化導電層134的數目可基於需要及設計佈局獨立地為一個或多於一個。
如圖3中所示,在一些實施例中,在連接墊120上及載體112之上形成介電層132-1。在一些實施例中,介電層132-1覆蓋並包覆連接墊120。如圖3中所示,對於每一個連接墊120,導電圖案124被介電層132-1及阻障晶種圖案122環繞,且與剝離層114接觸的阻障晶種圖案122的表面S122b上不存在有介電層132-1,而阻障晶種圖案122的側壁S122s被介電層132-1包覆,其中導電圖案124的表面S124b物理地接觸阻障晶種圖案122的表面S122t。詳細來說,連接墊120的頂表面(例如,導電圖案124的表面S124t)及側壁(例如,導電圖案124的側壁S124s及阻障晶種圖案122的側壁S122s)物理地接觸介電層132-1,而連接墊120的底表面(例如,阻障晶種圖案122的表面S122b)上不存在有介電層132-1。換句話說,如圖3中所示,在一些實施例中,每一個連接墊120嵌入在介電層132-1中,連接墊120的一個表面(例如,表面S122b)被介電層132-1暴露出,其中阻障晶種圖案122的表面S122b與介電層132-1的表面S132-1b實質上齊平且共面(coplanar)(圖12)。
在一些實施例中,介電層132-1包括依序堆疊的介電材料132a及介電材料132b。在一些實施例中,介電材料132a及介電材料132b可包括氧化矽、氮化矽、聚合物或其組合,且是透過例如旋轉塗布(spin coating)、CVD等適合的製程沉積介電材料並接著對介電材料執行平坦化製程(planarization process)而形成。在一些實施例中,介電材料132a與介電材料132b的形成及材料可彼此相同或彼此不同,本公開不限於此。
在替代實施例中,在介電材料132a與介電材料132b之間、介電材料132a與連接墊120之間或者其組合之間可存在附加介電材料(圖中未示出)。舉例來說,附加介電材料的材料及形成可與介電材料132a及介電材料132b相同或相似,且因此本文中不再予以贅述。在一些實施例中,介電材料132a、介電材料132b與附加介電材料的功能及材料可彼此相同或彼此不同,本公開不限於此。舉例來說,附加介電材料可為氮化矽且用於蝕刻終止層,而介電材料132a及132b可為氧化矽且用於接合。
參照圖3及圖4,在介電層132-1中形成多個開口O1及多個開口O2。在一些實施例中,開口O1貫穿介電層132-1以暴露出連接墊120,而開口O2形成在介電層132-1中而不暴露出連接墊120。開口O1各自可為(但不限於)雙鑲嵌開口(dual damascene opening)。也就是說,開口O1各自包括較窄的通孔孔洞O1v及位於較窄的通孔孔洞O1v之上的較寬的溝渠孔洞O1t。在一些實施例中,按照以下步驟(稱作溝渠優先製程(trench first process))形成開口O1。透過微影製程及蝕刻製程將介電材料132b圖案化以在介電材料132b中形成溝渠孔洞O1t。溝渠孔洞O1t的定位位置對應於連接墊120的定位位置。接下來,透過微影製程及蝕刻製程將介電材料132a圖案化以在介電材料132a中形成通孔孔洞O1v。通孔孔洞O1v的定位位置對應于溝渠孔洞O1t的定位位置及連接墊120的定位位置。如圖4中所示,通孔孔洞O1v沿方向Z分別在空間上與溝渠孔洞O1t連通以形成開口O1。在一些實施例中,較窄的通孔孔洞O1v的底部寬度(或面積)小於導電圖案124的表面S124t的寬度(或面積)。在一些替代實施例中,較窄的通孔孔洞O1v的底部寬度(或面積)等於導電圖案124的表面S124t的寬度(或面積)。舉例來說,如圖4中所示,每一個開口O1對應於相應一個連接墊120,且暴露出所述相應一個連接墊120的導電圖案124的表面S124t的至少部分。
另一方面,在一些實施例中,開口O2可為(但不限於)單鑲嵌開口(single damascene opening)。舉例來說,開口O2各自可被稱作透過將介電材料132b圖案化以暴露出介電材料132a而形成的溝渠。在一些實施例中,開口O2的定位位置對應於連接墊120的定位位置,然而本公開不限於此。在其他實施例中,開口O2的定位位置不對應於連接墊120的定位位置。在又一些其他實施例中,一些開口O2的定位位置對應於連接墊120的定位位置,且一些開口O2的定位位置則不對應於連接墊120的定位位置。舉例來說,如圖4中所示,開口O2貫穿介電材料132b以暴露出介電材料132a的表面S132a。
在一些實施例中,可在相同的步驟處形成開口O2以及開口O1的溝渠孔洞O1t。在一些實施例中,可在不同的步驟處形成開口O2以及開口O1的溝渠孔洞O1t。開口O1及開口O2的數目在本文中不受限制,且可基於需要及設計佈局來指定及選擇。舉例來說,開口O1及開口O2的數目可為一個或多於一個,然而本公開不限於此。在另一個實例中,開口O1的數目可為一個或多於一個,且開口O2的數目可為零。
在介電材料132a與介電材料132b之間以及介電材料132a與連接墊120之間存在附加介電材料(用作蝕刻停止層)的替代實施例中,還可透過蝕刻製程蝕刻介電材料132a與介電材料132b之間的附加介電材料以形成暴露出介電材料132a的溝渠孔洞O1t,且還可透過蝕刻製程蝕刻介電材料132a與連接墊120之間的附加介電材料以形成暴露出連接墊120的通孔孔洞O1v。在附加介電材料的蝕刻製程期間,附加介電材料對介電材料132a和/或132b的蝕刻選擇性(etching selectivity)是顯著高的,因此在不移除介電材料132a及介電材料132b(例如,介電材料132a及介電材料132b的移除程度是顯著小的且因此為可忽略的)的情況下執行附加介電材料的蝕刻製程。
如圖5中所示,在一些實施例中,在介電層132-1上及載體112之上形成晶種層材料SL。在一些實施例中,晶種層材料SL直接形成在介電層132-1上且進一步延伸到形成在介電層132-1中的開口O1及開口O2中。在一些實施例中,晶種層材料SL被形成為與具有開口O1及開口O2的介電層132-1的輪廓共形,且均勻地覆蓋開口O1及開口O2的側壁及底表面以及介電層132-1的表面S132-1t。換句話說,開口O1的側壁及底表面以及開口O2的側壁及底表面完全被晶種層材料SL覆蓋。舉例來說,如圖5中所示,位於開口O1內的部分晶種層材料SL物理地接觸透過開口O1而暴露出的連接墊120。晶種層材料SL的材料及形成與圖1中所述晶種層材料122a的材料及形成實質上相同或相似,且因此為簡明起見,本文中不再予以贅述。在一個實施例中,晶種層材料SL的材料與晶種層材料122a的材料相同,然而本公開不限於此。在替代實施例中,晶種層材料SL的材料可與晶種層材料122a的材料不同。此外,共形的晶種層材料SL可說明降低重佈線路結構130的電阻並改善重佈線路結構130的電性質。
如圖6中所示,在一些實施例中,在晶種層材料SL上及在介電層132-1之上形成金屬材料ML以填充形成在介電層132-1中的開口O1及開口O2。在一些實施例中,金屬材料ML可為銅、鎳、鋁、金、銀、鎢、其合金或其組合,且可透過電化學鍍覆製程(electro-chemical plating process)、CVD、PVD等形成。然而,應理解,本公開的範圍不限於以上所公開的材料及說明。
在一些實施例中,參照圖6及圖7,執行平坦化製程以移除位於介電層132-1的表面S132-1t上方的部分金屬材料ML及位於介電層132-1的表面S132-1t上方的部分晶種層材料SL。在一些實施例中,移除位於介電層132-1的表面S132-1t上方的金屬材料ML及晶種層材料SL,直到暴露出介電層132-1的表面S132-1t為止。在移除位於介電層132-1的表面S132-1t上方的金屬材料ML及晶種層材料SL之後,形成多個金屬圖案134a及多個金屬圖案134b,金屬圖案134a各自具有填充在開口O1內的晶種層圖案134s、通孔134v及導電溝渠134t,金屬圖案134b各自具有填充在開口O2內的晶種層圖案134s及導電溝渠134t。在一些實施例中,對於每一個金屬圖案134a,晶種層圖案134s、通孔134v及導電溝渠134t彼此電耦合。在一些實施例中,對於每一個金屬圖案134b,晶種層圖案134s與導電溝渠134t彼此電耦合。在一些實施例中,平坦化製程包括化學機械拋光(chemical-mechanical polishing,CMP)製程、機械研磨製程(mechanical grinding process)、飛切製程(fly cutting process)或回蝕製程(etching back process)或其組合。
在連接墊120嵌入在介電材料132a中的一些實施例中,介電材料132a的厚度H132介於約0.5微米(μm)至約10μm範圍內。在一些實施例中,導電圖案124的厚度H124介於約5千埃(kÅ)至約40kÅ範圍內。舉例來說,介電材料132a的厚度H132介於約0.5μm至約1.5μm範圍內,而導電圖案124的厚度H124小於或實質上等於約14kÅ。另舉一例,介電材料132a的厚度H132介於約1.5μm至約2.5μm範圍內,而導電圖案124的厚度H124大於或實質上等於約14kÅ。本公開不特別限於此。另外,阻障晶種圖案122的厚度H122介於約200埃(Å)至約2000Å範圍內;本公開不限於此。
如圖7中所示,在一些實施例中,在對金屬材料ML及晶種層材料SL執行平坦化製程之後形成圖案化導電層134-1。舉例來說,圖案化導電層134-1包括形成在開口O1中的多個金屬圖案134a及形成在開口O2中的多個金屬圖案134b(如圖7中所示),然而本公開不限於此。在一個實施例中,圖案化導電層134-1可包括一個或多於一個形成在開口O1中的金屬圖案134a和/或一個或多於一個形成在開口O2中的金屬圖案134b。在替代實施例中,圖案化導電層134-1可包括一個或多於一個形成在開口O1中的金屬圖案134a且不包括形成在開口O2中的金屬圖案134b。
在一些實施例中,金屬圖案134a可為雙鑲嵌結構且與位於金屬圖案134a之下的連接墊120物理地連接,且金屬圖案134b可為單鑲嵌結構且形成在介電材料132a之上。換句話說,金屬圖案134a可包括凸塊通孔(bump via)及位於凸塊通孔之上的凸塊金屬線(bump metal line)(例如,凸塊導電溝渠),且金屬圖案134b可包括凸塊金屬線。在本公開中,在圖案化導電層134-1內,金屬圖案134a與金屬圖案134b可不彼此電連接或者可至少部分地彼此電連接。在本公開中,介電層132-1及圖案化導電層134-1被一起稱作重佈線路結構130的第一構成層(first build-up layer),其中第一構成層具有高共面度以便於形成隨後形成的特徵(例如膜層(例如,附加構成層)或裝置(例如,半導體晶粒或晶片))。舉例來說,如圖7中所示,圖案化導電層134-1的金屬圖案134a電連接到連接墊120。
如圖8中所示,在一些實施例中,在第一構成層(包括介電層132-1及圖案化導電層134-1)上依序形成介電層132-2、圖案化導電層134-2、介電層132-3及圖案化導電層134-3,以形成重佈線路結構130。介電層132-2及132-3的形成及材料與介電層132-1的形成及材料相同或相似,且圖案化導電層134-2及134-3的形成及材料與圖案化導電層134-1的形成及材料相同或相似,且因此為簡明起見,本文中不再予以贅述。
在一些實施例中,圖案化導電層134-2物理地連接到圖案化導電層134-1,且圖案化導電層134-3物理地連接到圖案化導電層134-2。換句話說,重佈線路結構130內的圖案化導電層134-1、134-2及134-3彼此電連接。舉例來說,各自形成在圖案化導電層134-1、圖案化導電層134-2及圖案化導電層134-3中的金屬圖案134a和/或金屬圖案134b的數目可為相同的或不同的,本公開不限於此。
在本公開中,圖8中所繪示介電層132-2及圖案化導電層134-2被一起稱作重佈線路結構130的第二構成層(second build-up layer),且圖8中所繪示介電層132-3及圖案化導電層134-3被一起稱作重佈線路結構130的第三構成層(third build-up layer)。在一些實施例中,如圖8中所示,第二構成層及第三構成層可與圖3至圖7中所述第一構成層(包括介電層132-1及圖案化導電層134-1)實質上相同或相似。然而,本公開不限於此;在替代實施例中,第二構成層及第三構成層可與第一構成層不同。在本公開中,重佈線路結構130中所包括的構成層的數目不受限制。在一個實施例中,重佈線路結構130中所包括的構成層(build-up layer)的數目可為一個或多於一個。舉例來說,如圖8中所示,重佈線路結構130物理地連接到且電連接到連接墊120。
參照圖9,在一些實施例中,提供至少一個半導體晶粒140。此後,出於例示目的,在圖9中示出兩個半導體晶粒140;本公開不限於此。在其他實施例中,半導體晶粒140的數目可基於需要及設計佈局而為一個或多於一個。舉例來說,如圖9中所示,將半導體晶粒140拾取並放置在重佈線路結構130(例如,重佈線路結構130的表面S132-3t)上。
在一些實施例中,半導體晶粒140各自包括:半導體基底141,具有主動表面S141a及與主動表面S141a相對的背側表面S141b;多個導電墊142,形成在主動表面S141a上;鈍化層143,安置在導電墊142上且局部地暴露出導電墊142;後鈍化層144,安置在鈍化層143上且局部地暴露出導電墊142;多個連接通孔145,安置在導電墊142上;以及保護層146,覆蓋後鈍化層144並包覆連接通孔145的側壁。換句話說,分佈在半導體基底141的主動表面S141a上的導電墊142被鈍化層143的接觸開口及後鈍化層144的接觸開口局部地暴露出,以物理地連接到連接通孔145。
在一些實施例中,半導體基底141的材料可包括矽基底,矽基底包括形成在其中的主動元件(例如,電晶體和/或記憶體(例如n通道金屬氧化物半導體(n-channel metal oxide semiconductor,NMOS)和/或p通道金屬氧化物半導體(p-channel metal oxide semiconductor,PMOS)裝置等))和/或被動元件(例如,電阻器、電容器、電感器等)。在替代實施例中,半導體基底141可為塊狀矽基底(bulk silicon substrate),例如由單晶矽構成的塊狀基底、經摻雜矽基底、未經摻雜矽基底或絕緣體上有矽(silicon on insulator,SOI)基底,其中經摻雜矽基底的摻雜劑可為N型摻雜劑、P型摻雜劑或其組合。本公開不限於此。
在一些實施例中,導電墊142可為鋁墊或其他適合的金屬墊。舉例來說,連接通孔145可為銅柱、銅合金柱或其它適合的金屬柱。在一些實施例中,鈍化層143、後鈍化層144和/或保護層146可為PBO層、聚醯亞胺(PI)層或其它適合的聚合物。在某些實施例中,鈍化層143、後鈍化層144和/或保護層146可由例如氧化矽、氮化矽、氮氧化矽或任何適合的介電材料等無機材料製成。在一個實施例中,鈍化層143、後鈍化層144和/或保護層146的材料可相同。在替代實施例中,鈍化層143、後鈍化層144和/或保護層146的材料可彼此不同,本公開不限於此。
繼續參照圖9,在一些實施例中,透過混合接合(hybrid bonding)(透過混合接合介面IF)將半導體晶粒140接合到重佈線路結構130。舉例來說,混合接合製程可包括親水熔融接合製程(hydrophilic fusion bonding process)或疏水熔融接合製程(hydrophobic fusion bonding process)。在一些實施例中,半導體晶粒140中的每一者的連接通孔145物理地接合到重佈線路結構130的圖案化導電層134的最頂層(例如,圖案化導電層134-3),圖案化導電層134的所述最頂層被介電層132的最頂層(例如,介電層132-3)暴露出來,且重佈線路結構130的介電層132-3的部分不被半導體晶粒140覆蓋。舉例來說,如圖9中所示,半導體晶粒140物理地連接到且電連接到重佈線路結構130。在一些實施例中,半導體晶粒140各自透過重佈線路結構130而電連接到連接墊120中的一些連接墊120。在本公開中,半導體晶粒140透過重佈線路結構130而彼此電連通。
在一些實施例中,本文中所述半導體晶粒140中的每一者可被稱作晶片或積體電路(integrated circuit,IC)。在一些實施例中,半導體晶粒140可包括為相同類型的晶片或為不同類型的晶片。舉例來說,半導體晶粒140包括無線及射頻(radio frequency,RF)晶片。舉例來說,在替代實施例中,半導體晶粒140包括數位晶片、類比晶片或混合信號晶片,例如應用專用積體電路(“application-specific integrated circuit,ASIC”)晶片、感測器晶片、無線及射頻(RF)晶片、記憶體晶片、邏輯晶片、電壓調節器晶片或其組合。在替代實施例中,半導體晶粒140中的一個或全部可被稱作組合型晶片或組合型積體電路。舉例來說,半導體晶粒140中的至少一者可為同時包括RF晶片與數位晶片二者的無線保真(wireless fidelity,WiFi)晶片。本公開不限於此。
參照圖10,在一些實施例中,在半導體晶粒140之上共形地形成絕緣材料150a,其中半導體晶粒140被包封在絕緣材料150a中,且被半導體晶粒140暴露出來的重佈線路結構130被絕緣材料150a覆蓋。在一些實施例中,如圖10中所示,半導體晶粒140中的每一者的背側表面S141b及側壁被絕緣材料150a環繞及覆蓋。在一些實施例中,絕緣材料150a可為氧化物(例如氧化矽等)。在一些實施例中,可透過沉積形成絕緣材料150a。如圖10中所示,半導體晶粒140及重佈線路結構130不被絕緣材料150a以可觸及方式露出。
參照圖11,在一些實施例中,對絕緣材料150a執行平坦化步驟以形成暴露出半導體晶粒140的背側表面S141b的絕緣包封體150。在某些實施例中,如圖11中所示,在平坦化之後,半導體晶粒140的背側表面S141b被絕緣包封體150的表面S150暴露出來。也就是說,半導體晶粒140的背側表面S141b例如變得與絕緣包封體150的表面S150實質上齊平。換句話說,半導體晶粒140的背側表面S141b與絕緣包封體150的表面S150彼此實質上共面。在一些實施例中,如圖11中所示,半導體晶粒140被絕緣包封體150以可觸及方式露出。
舉例來說,可透過機械研磨或CMP製程對絕緣材料150a進行平坦化。在平坦化步驟之後,可哥選地執行清潔步驟,例如以清潔來移除從平坦化步驟產生的殘留物。然而,本公開不限於此,且可透過任何其他適合的方法執行平坦化步驟。在一些替代實施例中,在對絕緣材料150a進行平坦化期間,半導體晶粒140的半導體基底141也可被平坦化。在某些實施例中,可例如對包覆模制(over-mold)絕緣材料150a執行平坦化步驟以齊平半導體晶粒140的背側表面S141b及絕緣包封體150的表面S150。由此,半導體晶粒140的背側表面S141b與絕緣包封體150的表面S150具有高共面度,以便於進行後續製程步驟。
參照圖12,在一些實施例中,將圖11中所繪示的整個結構翻轉(上下翻倒)並放置在塗布有剝離層214的載體212上,並將載體112從連接墊120及重佈線路結構130剝離。在一些實施例中,連接墊120(例如,阻障晶種圖案122)及重佈線路結構130(例如,介電層132-1的介電材料132a)因剝離層114而輕易地與載體112分離,且連接墊120(例如,阻障晶種圖案122的表面S122b)及重佈線路結構130(例如,介電層132-1的表面S132-1b)被暴露出。在一些實施例中,透過剝離製程將載體112從連接墊120及重佈線路結構130拆離,並移除載體112及剝離層114。
在一些實施例中,載體212的材料與載體112的材料可相同,然而本公開不限於此。在替代實施例中,載體212的材料可與載體112的材料不同。在一些實施例中,剝離層214的材料及形成可與剝離層114的材料及形成相同或不同,本公開不限於此。
參照圖13,在一些實施例中,在重佈線路結構130上形成鈍化層160,且鈍化層160至少局部地暴露出連接墊120。在一些實施例中,鈍化層160形成在重佈線路結構130上以完全覆蓋介電層132-1的表面S132-1b且形成在連接墊120上,其中形成在鈍化層160中的多個開口O3局部地暴露出被重佈線路結構130以可觸及方式露出的連接墊120的阻障晶種圖案122的表面S122b。如圖13中所示,連接墊120的尺寸W122大於開口O3的尺寸WO3。換句話說,連接墊120的阻障晶種圖案122中的每一者的部分物理地接觸鈍化層160(例如,在圖15中所繪示的區域R1內)。在一些實施例中,鈍化層160沿堆疊方向(例如,方向Z)與阻障晶種圖案122及導電墊124交疊(例如,在圖15中所繪示的區域R1內)。在一些實施例中,鈍化層160可為透過旋轉塗布或沉積所形成的PBO層、PI層或其它適合的聚合物層,而開口O3可透過蝕刻在鈍化層160中形成。然而,應理解,本公開的範圍不限於以上所公開的材料及說明。
繼續參照圖13,在一些實施例中,在鈍化層160上形成介電層170,且介電層170至少局部地暴露出被鈍化層160暴露出來的連接墊120。在一些實施例中,介電層170形成在鈍化層160上且完全覆蓋鈍化層160,並延伸到開口O3中,而透過開口O3以可觸及方式暴露出的連接墊120的部分透過形成在介電層170中的多個開口O4進一步暴露出。也就是說,開口O4的定位位置分別對應於開口O3的定位位置。在一些實施例中,連接墊120的尺寸W122大於開口O4的尺寸WO4,且開口O3的尺寸WO3大於開口O4的尺寸WO4。在一些實施例中,連接墊120的阻障晶種圖案122中的每一者的部分物理地接觸介電層170(例如,在圖15中所繪示的區域R2內)。在一些實施例中,介電層170沿堆疊方向(例如,方向Z)與阻障晶種圖案122及導電墊124交疊(例如,在圖15中所繪示的區域R1及區域R2內)。在一些實施例中,介電層170可包含例如透過旋轉塗布或沉積所形成的氧化矽、氮化矽、氮氧化矽或任何適合的介電材料等無機材料,而開口O4可透過蝕刻形成在介電層170中。然而,應理解,本公開的範圍不限於以上所公開的材料及說明。
開口O3及開口O4的數目及形狀可例如對應于隨後形成的導電結構(例如導電球或導電柱)的數目及形狀,本公開不限於此。
參照圖14,在一些實施例中,在介電層170上依序形成多個阻障晶種圖案180及多個導電端子190,其中阻障晶種圖案180夾置在介電層170與導電端子190之間。在一些實施例中,阻障晶種圖案180各自位於導電端子190中相應的一者與介電層170之間。由於阻障晶種圖案180,導電端子190與介電層170之間的粘著力增強。在一些實施例中,阻障晶種圖案180直接位於介電層170上並進一步延伸到形成在介電層170中的開口O4中,以物理地接觸且電接觸被形成在介電層170中的開口O4暴露出來的連接墊120的部分阻障晶種圖案122。在一些實施例中,連接墊120的阻障晶種圖案122中的每一者的一部分是物理地接觸阻障晶種圖案180中上覆在所述一部分上的相應一者(例如,在圖15中所繪示的區域R3內)。在一些實施例中,阻障晶種圖案180各自沿堆疊方向(例如,方向Z)與連接墊120中相應一者的阻障晶種圖案122及導電墊124分別交疊(例如,在圖15中所繪示的區域R1、區域R2及區域R3內)。
如圖14中所示,在一些實施例中,阻障晶種圖案180透過連接墊120電連接到重佈線路結構130。在一些實施例中,導電端子190透過阻障晶種圖案180及連接墊120電連接到重佈線路結構130。在一些實施例中,導電端子190中的一些導電端子190透過阻障晶種圖案180、連接墊120及重佈線路結構130電連接到半導體晶粒140中的至少一者。
在一些實施例中,可透過以下步驟形成阻障晶種圖案180及導電端子190,然而本公開不限於此。舉例來說,在圖13中所繪示的結構上共形地形成晶種層材料(圖中未示出),且所述晶種層材料延伸到開口O4中。在晶種層材料上形成其中形成有多個開口的抗蝕劑層(圖中未示出),以暴露出與開口O4的定位位置對應的晶種層材料的部分。透過鍍覆製程在晶種層材料上、形成在介電層170中的開口O4中及形成在抗蝕劑層中的開口中,形成多個導電元件192。透過分配(dispensing),在導電元件192上分別安置多個導電元件194,以形成多個導電端子190。透過可接受的灰化製程(ashing process)和/或光阻剝除製程(photoresist stripping process)移除抗蝕劑層。接著,透過一個或多於一個蝕刻製程,使用導電端子190作為蝕刻罩幕將晶種層材料圖案化,以形成多個阻障晶種圖案180。在一些實施例中,導電元件192的材料可包括銅、銅合金等;且導電元件194的材料可包括焊料等。然而,本公開不限於此,以上方法及製程可根據需要被任何其它適合的方法及製程代替。
如圖14中所示,舉例來說,沿著重佈線路結構130與半導體晶粒140的堆疊方向(例如,方向Z)在載體212上的垂直投影中,一個導電端子190的投影面積與位於所述一個導電端子190之下的相應一個阻障晶種圖案180的投影面積分別實質上相同。也就是說,在方向Z上,於X-Y平面上的垂直投影中,導電端子190各自與位於導電端子190之下的阻障晶種圖案180完全交疊。在一些實施例中,一個阻障晶種圖案180的側壁與相應一個導電端子190的側壁對準。
在一些替代實施例中,導電端子190為例如微凸塊(micro bump,μ-bump)、晶片連接件(例如,受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊)、球柵陣列(ball grid array,BGA)球、焊球或其它連接件。導電端子190的數目不限於本公開,且可基於開口O3及開口O4的數目來指定及選擇。當使用焊料時,所述焊料可包括共晶焊料(eutectic solder)或非共晶焊料(non-eutectic solder)。焊料可包含鉛或者為無鉛的,且可包含Sn-Ag、Sn-Cu、Sn-Ag-Cu等。在本公開中,對於一個實施例,導電端子190可被稱作用於與另一個封裝連接的導電連接件;或者對於另一個實施例,導電端子190可被稱作用於輸入/輸出電信號和/或功率信號的導電端子。
在一些實施例中,在形成導電端子190及阻障晶種圖案180之後,接著執行切割(單體化)製程,以將具有多個封裝結構P1的晶圓切割成各自分開且分離的多個封裝結構P1。在一個實施例中,所述切割製程是包括機械刀片鋸切(mechanical blade sawing)或雷射切割(laser cutting)的晶圓切割製程。至此,封裝結構P1的製造便告完成。藉由連接墊120的配置,使得阻障晶種圖案180/導電端子190與透過重佈線路結構130電連接到半導體晶粒140的連接墊120之間的未對準(misalignment)情況得到大幅抑制,從而提高了封裝結構P1的可靠性及良率。換句話說,透過連接墊120的形成方式,而輕易地實現分別在鈍化層160及介電層170中形成開口O3及開口O4以精確地暴露出連接墊120來電連接到導電端子190(或其它外部半導體裝置),從而提高了封裝結構P1的可靠性及良率。
在一些實施例中,如圖14中所示,載體212保留在封裝結構P1中以用作封裝結構P1的散熱元件,其中載體212為例如矽(Si)基底。在這種實施例中,載體212可進一步用於翹曲控制(warpage control)。然而,本公開不限於此,在替代實施例中,可將載體212進一步從封裝結構P1移除。
在又一些替代實施例中,除導電端子190之外,在圖14中,也可在阻障晶種圖案180上安置附加半導體裝置(圖中未示出),以電耦合半導體晶粒140中的至少一者。在一些實施例中,附加半導體裝置可包括被動元件或主動元件。在本公開中,附加半導體裝置的數目不受限制,且可基於需要及設計佈局來指定。
在替代實施例中,可省略圖14中所繪示的封裝結構P1中的導電元件194以形成導電端子190(參見如圖16中所示的封裝結構P1’)。在這種實施例中,封裝結構P1’的導電端子190可包括金屬杆/柱,例如銅杆/柱或其它金屬杆/柱。
圖17示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。圖18示出圖17中所繪示封裝結構的一部分的放大示意性剖視圖,其中所述封裝結構的所述一部分是由圖17中所繪示的虛線框E2標明。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號,且本文中將不再對相同元件的某些細節或說明(例如,材料、形成製程、定位配置等)予以贅述。參照圖14及圖17至圖18,圖17及圖18中所繪示的封裝結構P2相似於圖14中所繪示的封裝結構P1;不同之處在于,在封裝結構P2中,連接墊120被連接墊120’(參見圖18)代替。
如圖17中所示,在一些實施例中,在形成在介電層170中的開口O4的形成期間,連接墊120的部分阻障晶種圖案122也被移除以形成具有開口O5的連接墊120’。在一些實施例中,連接墊120’各自具有阻障晶種圖案122’及堆疊在阻障晶種圖案122’上的導電墊124,其中導電墊124透過形成在阻障晶種圖案122’中的開口O5局部地暴露出。換句話說,形成在介電層170中的開口O4各自在空間上與形成在阻障晶種圖案122’中的相應一個開口O5連通,使得連接墊120’的導電墊124透過形成在連接墊120’的阻障晶種圖案122’中的開口O5暴露出,以分別連接隨後形成的阻障晶種墊180。也就是說,對於每一個連接墊120’,導電墊124的表面S124b透過形成在相應一個阻障晶種圖案122’中的一個開口O5及形成在介電層170中的相應一個開口O4暴露出。舉例來說,阻障晶種圖案180分別連接到連接墊120’。如圖17及圖18中所示,阻障晶種圖案180中的每一者物理地連接到且電連接到連接墊120’中相應的一者(例如,位於開口O5內的阻障晶種圖案122’的側壁及被形成在阻障晶種圖案122’中的開口O5所暴露出來的導電墊124的表面S124b)。
如圖18中所示,在一些實施例中,在區域R1內,連接墊120’的阻障晶種圖案122’中的每一者的部分物理地接觸鈍化層160。在一些實施例中,鈍化層160沿堆疊方向(例如,方向Z)與阻障晶種圖案122’及導電墊124交疊(例如,在區域R1內)。如圖18中所示,在一些實施例中,在區域R2內,連接墊120’的阻障晶種圖案122’中的每一者的部分物理地接觸介電層170。在一些實施例中,介電層170沿堆疊方向(例如,方向Z)與阻障晶種圖案122’及導電墊124交疊(例如,在圖18中所繪示的區域R1及區域R2內)。在一些實施例中,在區域R3內,導電墊124中的每一者的部分(例如,透過開口O5暴露出的表面S124b)物理地接觸上覆在所述部分上的阻障晶種圖案180中相應的一者。在一些實施例中,阻障晶種圖案180沿堆疊方向(例如,方向Z)分別與阻障晶種圖案122’ (例如,在圖18中所繪示的區域R1及區域R2內)及導電墊124交疊(例如,在圖18中所繪示的區域R1、區域R2及區域R3內)。
圖19示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。圖20示出圖19中所繪示封裝結構的一部分的放大示意性剖視圖,其中所述封裝結構的所述一部分是由圖19中所繪示的虛線框E3標明。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號,且本文中將不再對相同元件的某些細節或說明(例如,材料、形成製程、定位配置等)予以贅述。參照圖14及圖19至圖20,圖19及圖20中所繪示的封裝結構P3相似於圖14中所繪示的封裝結構P1;不同之處在于,在封裝結構P3中,連接墊120被連接墊120’’(參見圖20)代替。
如圖19中所示,在一些實施例中,在形成在鈍化層160中的開口O3的形成期間,連接墊120的部分阻障晶種圖案122也被移除以形成具有開口O6的連接墊120’’。在一些實施例中,連接墊120’’各自具有阻障晶種圖案122’’及堆疊在阻障晶種圖案122’’上的導電墊124,其中導電墊124透過形成在阻障晶種圖案122’’中的開口O6局部地暴露出。換句話說,形成在鈍化層160中的開口O3各自在空間上與形成在阻障晶種圖案122’’中的相應一個開口O6連通,使得連接墊120’’的導電墊124透過形成在連接墊120’’的阻障晶種圖案122’’中的開口O6暴露出,以分別連接隨後形成的阻障晶種圖案180。
利用這種配置,形成在介電層170中的開口O4進一步延伸到形成在阻障晶種圖案122’’中的開口O6中,以暴露出連接墊120’’的導電墊124。舉例來說,阻障晶種圖案180分別連接到連接墊120’’。如圖19及圖20中所示,阻障晶種圖案180中的每一者物理地連接到且電連接到連接墊120’’中相應的一者(例如,被形成在介電層170中的開口O4暴露出來的導電墊124的表面S124b)。
如圖20中所示,在一些實施例中,在區域R1內,連接墊120’’的阻障晶種圖案122’’中的每一者的部分物理地接觸鈍化層160。在一些實施例中,鈍化層160沿堆疊方向(例如,方向Z)與阻障晶種圖案122’’及導電墊124交疊(例如,在區域R1內)。如圖20中所示,在一些實施例中,在區域R2內,導電墊124中的每一者的部分(例如,透過開口O6暴露出的表面S124b)物理地接觸介電層170。在一些實施例中,介電層170沿堆疊方向(例如,方向Z)與阻障晶種圖案122’’交疊(例如,在圖20中所繪示的區域R1內)且與導電墊124交疊(例如,在圖20中所繪示的區域R1及區域R2內)。如圖20中所示,在一些實施例中,在區域R3內,導電墊124中的每一者的部分(例如,透過開口O4暴露出的表面S124b)物理地接觸上覆在所述部分上的阻障晶種圖案180中相應的一者。在一些實施例中,阻障晶種圖案180沿堆疊方向(例如,方向Z)分別與阻障晶種圖案122’’交疊(例如,在圖20中所繪示的區域R1內)且與導電墊124交疊(例如,在圖20中所繪示的區域R1、區域R2及區域R3內)。
本公開不限於此;在替代實施例中,圖17中所繪示的封裝結構P2中的導電元件194和/或圖19中所繪示的封裝結構P3的導電元件194也可被省略(相似於圖16所示封裝結構P1’中所示的導電端子190)。
在一些替代實施例中,基於設計佈局及需要,封裝結構P1、P1’、P2及P3可進一步透過導電端子190和/或其他附加連接件而安裝有電路基底(circuit substrate)、中介體(interposer)、附加封裝(additional package)、晶片/晶粒或其他電子裝置,以形成堆疊封裝結構(stacked package structure)。作為例示,提供以下多個實例(例如,圖21所示封裝結構P4及圖22所示封裝結構P5(封裝結構P1的應用)以及圖23至圖29所示封裝結構P6(封裝結構P1’的應用)),但本公開不限於此。
圖21示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號,且本文中將不再對相同元件的某些細節或說明(例如,材料、形成製程、定位配置等)予以贅述。
參照圖21,在一些實施例中,提供基底500。在一些實施例中,基底500包括多個接觸墊510、多個接觸墊520、多個金屬化層530及多個通孔(圖中未示出)。在一些實施例中,接觸墊510與接觸墊520分別分佈在基底500的兩個相對側上,且被暴露出以與隨後形成的元件/特徵電連接。在一些實施例中,金屬化層530及通孔嵌入在基底500中且一起提供基底500的佈線功能,其中金屬化層530及通孔電連接到接觸墊510及接觸墊520。也就是說,接觸墊510中的至少一些接觸墊510透過金屬化層530及通孔電連接到接觸墊520中的一些接觸墊520。在一些實施例中,接觸墊510及接觸墊520可包括金屬墊或金屬合金墊。在一些實施例中,金屬化層530及通孔的材料可與金屬材料ML的材料實質上相同或相似,且因此為簡明起見,本文中不再予以贅述。
在一些實施例中,如圖21中所示,圖14中所繪示的封裝結構P1透過導電端子190物理地連接接觸墊510,而接合到基底500,以形成具有堆疊結構的封裝結構P4,其中封裝結構P1物理地連接到且電連接到基底500。圖1至圖15中闡述了封裝結構P1的細節,且因此本文中不再予以贅述。在一些實施例中,基底500被稱作電路基底,例如有機柔性基底(organic flexible substrate)或印刷電路板(printed circuit board)。在這種實施例中,導電端子190為例如晶片連接件或BGA球。
在一些實施例中,在基底500上分別形成多個導電端子600。舉例來說,如圖21中所示,導電端子600連接到基底500的接觸墊520。換句話說,導電端子600透過接觸墊520電連接到基底500。透過接觸墊510及接觸墊520,導電端子600中的一些導電端子600電連接到封裝結構P1(例如,封裝結構P1中所包括的半導體晶粒140)。在一些實施例中,導電端子600為例如焊球或BGA球。在一些實施例中,封裝結構P1透過利用倒裝晶片接合(flip chip bonding)將導電端子190與基底500的接觸墊510物理地連接而接合到基底500。
圖22示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號,且本文中將不再對相同元件的某些細節或說明(例如,材料、形成製程、定位配置等)予以贅述。
參照圖22,在一些實施例中,提供電路元件200。在一些實施例中,電路元件200包括芯體部210、多個通孔220、重佈線路結構230、重佈線路結構240、多個接合墊254a、多個接合墊254b、焊料罩幕層252a及焊料罩幕層252b。
在一些實施例中,芯體部210可包括塊狀矽基底,例如由單晶矽構成的塊狀基底、經摻雜矽基底、未經摻雜矽基底或SOI基底,其中經摻雜矽基底的摻雜劑可為N型摻雜劑、P型摻雜劑或其組合。在一些實施例中,通孔220是貫穿芯體部210的矽穿孔(through silicon via)。在本公開中,電路元件200被稱作中介體(參見圖22)。
如圖22中所示,在一些實施例中,重佈線路結構230與重佈線路結構240分別安置在芯體部210的兩個相對側上。在一些實施例中,重佈線路結構230和/或重佈線路結構240電連接到貫穿芯體部210的通孔220。如圖22中所示,在一些實施例中,嵌有通孔220的芯體部210位於重佈線路結構230與重佈線路結構240之間。透過通孔220,重佈線路結構230與重佈線路結構240彼此電連接。
在一些實施例中,重佈線路結構230包括依序交替形成的一個或多個介電層232及一個或多個金屬化層234,其中一個金屬化層234夾置在兩個介電層232之間。如圖22中所示,金屬化層234的最頂層的頂表面的部分分別透過形成在介電層232的最頂層中的開口暴露出以與其它導電特徵連接,且金屬化層234的最底層的底表面的部分分別透過形成在介電層232的最底層中的開口暴露出以與通孔220連接。重佈線路結構230中所包括的金屬化層及介電層的數目不限於此,且可基於需要來指定及選擇。
在一些實施例中,重佈線路結構240包括依序交替形成的一個或多個介電層242及一個或多個金屬化層244,其中一個金屬化層244夾置在兩個介電層242之間。如圖22中所示,金屬化層244的最頂層的頂表面的部分分別透過形成在介電層242的最頂層中的開口暴露出以與通孔220連接,且金屬化層244的最底層的底表面的部分分別透過形成在介電層242的最底層中的開口暴露出以與其他導電特徵連接。重佈線路結構240中所包括的金屬化層及介電層的數目不限於此,且可基於需要來指定及選擇。
在某些實施例中,介電層232及介電層242的材料可為可使用微影和/或蝕刻製程來圖案化的PI、PBO、BCB、例如氮化矽等氮化物、例如氧化矽等氧化物、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、硼磷矽酸鹽玻璃(boro-phospho-silicate glass,BPSG)、其組合等。在一些實施例中,介電層232及介電層242是透過例如旋轉塗布、CVD、等離子體增強型化學氣相沉積(plasma-enhanced CVD,PECVD)等適合的製作技術形成。本公開不限於此。在一個實施例中,介電層232的材料與介電層242的材料可相同。在替代實施例中,介電層232的材料與介電層242的材料可不同。
在某些實施例中,金屬化層234及金屬化層244的材料可由透過電鍍或沉積形成的導電材料(例如鋁、鈦、銅、鎳、鎢和/或其合金)製成,所述導電材料可使用微影及蝕刻製程來圖案化。在一些實施例中,金屬化層234及金屬化層244可為圖案化銅層或其他適合的圖案化金屬層。在一個實施例中,金屬化層234的材料與金屬化層244的材料可相同。在替代實施例中,金屬化層234的材料與金屬化層244的材料可不同。
在一些實施例中,接合墊254a安置在重佈線路結構230的表面上,且物理地連接到透過形成在介電層232的最頂層中的開口暴露出的金屬化層234的最頂層的頂表面的部分,其中透過形成在重佈線路結構230的(安置有接合墊254a的)表面上的焊料罩幕層252a,接合墊254a彼此物理地分離。透過重佈線路結構230,接合墊254a電連接到嵌入在芯體部210中的通孔220。
在一些實施例中,接合墊254b安置在重佈線路結構240的表面上,且物理地連接到透過形成在介電層242的最底層中的開口暴露出的金屬化層244的最底層的底表面的部分,其中透過形成在重佈線路結構240的(安置有接合墊254b的)表面上的焊料罩幕層252b,接合墊254b彼此物理地分離。透過重佈線路結構240,接合墊254b電連接到嵌入在芯體部210中的通孔220。
舉例來說,如圖22中所示,接合墊254a電連接到重佈線路結構230,且接合墊254b電連接到重佈線路結構240。在一些實施例中,接合墊254a及接合墊254b可包括凸塊下金屬(under bump metallurgy,UBM),然而本公開不限於此。舉例來說,如圖22中所示,接合墊254a與接合墊254b透過通孔220、重佈線路結構230及重佈線路結構240彼此電連接。
在替代實施例中,可從電路元件200省略重佈線路結構230及重佈線路結構240中的一者或兩者,本公開不限於此。也就是說,電路元件200可例如包括芯體部210、多個通孔220、多個接合墊254a、多個接合墊254b、焊料罩幕層252a及焊料罩幕層252b,其中接合墊254a與接合墊254b透過通孔220彼此電連接。
在一些實施例中,在接合墊254b上分別形成多個導電端子400。舉例來說,如圖22中所示,導電端子400物理地連接到接合墊254b。換句話說,導電端子400透過接合墊254b電連接到電路元件200。透過接合墊254b,導電端子400中的一些導電端子400電連接到接合墊254a中的一些接合墊254a。在一些實施例中,導電端子400為例如晶片連接件或BGA球。
繼續參照圖22,在一些實施例中,提供圖14中所繪示的封裝結構P1並將封裝結構P1接合到電路元件200,且電路元件200接合到基底500以形成具有堆疊結構的封裝結構P5。圖1至圖15中闡述了封裝結構P1的細節,且圖21中闡述了基底500的細節,且因此本文中不再予以贅述。在一些實施例中,封裝結構P1透過將導電端子190與電路元件200的接合墊254a連接而物理地連接到電路元件200,且電路元件200透過將導電端子400與基底500的接觸墊510連接而物理地連接到基底500。換句話說,封裝結構P1透過導電端子190及接合墊254a電連接到電路元件200,電路元件200透過導電端子400及接觸墊510電連接到基底500,使得封裝結構P1透過導電端子190、接合墊254a、導電端子400及接觸墊510電連接到基底500。在這種實施例中,導電端子190為例如微凸塊,而導電端子400為晶片連接件,且導電端子600為焊球或BGA球。在某些實施例中,圖22中所繪示的封裝結構P5可透過基底上晶圓上晶片(chip on wafer on substrate,CoWoS)封裝製程形成。
在一些實施例中,在電路元件200上最佳地形成有底部填充膠(underfill)300。舉例來說,如圖22中所示,底部填充膠300至少填充封裝結構P1與電路元件200之間的間隙,且包覆導電端子190的側壁。在一些替代實施例中,封裝結構P1的側壁可被底部填充膠300進一步覆蓋,本公開不限於此。舉例來說,底部填充膠300可為任何可接受的材料,例如聚合物、環氧樹脂、模制底部填充膠等。在一個實施例中,底部填充膠300可透過底部填充膠分配(underfill dispensing)或任何其他適合的方法來形成。底部填充膠300使得封裝結構P1與電路元件200之間的接合強度增強,從而提高了封裝結構P5的可靠性。
圖23至圖29示出根據本公開一些實施例的封裝結構的製造方法中的各種階段的示意性剖視圖。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號,且本文中將不再對相同元件的某些細節或說明(例如,材料、形成製程、定位配置等)予以贅述。
參照圖23,在一些實施例中,提供上面形成有剝離層DB及絕緣層IN的載體C。在一些實施例中,剝離層DB位於載體C與絕緣層IN之間。在一些實施例中,舉例來說,載體C為玻璃基底,剝離層DB為形成在玻璃基底上的LTHC釋放層,且絕緣層IN為形成在剝離層DB上的PBO層。應注意,在一些替代實施例中,所述形成絕緣層IN是可選的。還應注意,根據本公開,載體C、剝離層DB及絕緣層IN的材料不限於本文中所公開的材料。
在一些實施例中,在提供上面形成有剝離層DB及絕緣層IN的載體C之後,在絕緣層IN上形成多個導電柱CP。在一些實施例中,透過微影、鍍覆及光阻剝除製程在載體C之上(例如,直接在絕緣層IN上)形成導電柱CP。在一些替代實施例中,透過其他製程預先製作導電柱CP並將導電柱CP安裝在載體C之上。舉例來說,導電柱CP包括銅杆或其他金屬杆。
繼續參照圖23,在一些實施例中,可將圖16中所繪示的封裝結構P1’拾取並放置在由載體C所承載的絕緣層IN上。在一些實施例中,封裝結構P1’透過晶粒貼合膜(die attach film)、粘著膏(adhesion paste)等貼合或粘著在絕緣層IN上。在一些實施例中,如圖23中所示,封裝結構P1’可具有比導電柱CP的高度小的厚度。然而,本公開不限於此。在替代實施例中,封裝結構P1’的厚度可大於或實質上等於導電柱CP的高度。如圖23中所示,可在形成導電柱CP之後將封裝結構P1’拾取並放置在絕緣層IN上。然而,本公開不限於此。在替代實施例中,可在形成導電柱CP之前將封裝結構P1’拾取並放置在絕緣層IN上。
參照圖24,在載體C之上(例如,在絕緣層IN上)形成絕緣包封體710,以包封封裝結構P1’及導電柱CP。換句話說,封裝結構P1’及導電柱CP被絕緣包封體710覆蓋且嵌入在絕緣包封體710中。在一些實施例中,絕緣包封體710為透過模制製程形成的模制化合物(molding compound),且絕緣包封體710的材料可包括環氧樹脂或其他適合的樹脂。舉例來說,絕緣包封體710可為含有化學填料的環氧樹脂。如圖24中所示,封裝結構P1’及導電柱CP不被絕緣包封體710以可觸及方式露出。
參照圖24及圖25,在一些實施例中,將絕緣包封體710、導電柱CP及封裝結構P1’平坦化,直到封裝結構P1’的頂表面S1(例如,導電端子190的頂表面)及導電柱CP的頂表面S3暴露出為止。在將絕緣包封體710平坦化之後,在載體C之上(例如,在絕緣層IN上)形成平坦化絕緣包封體710’。在絕緣包封體710的平坦化製程期間,封裝結構P1’的導電端子190也被平坦化。在一些實施例中,在絕緣包封體710及封裝結構P1’的導電端子190的平坦化製程期間,導電柱CP的一部分也被平坦化。舉例來說,可透過機械研磨或CMP來形成平坦化絕緣包封體710’。在平坦化製程之後,可哥選地執行清潔步驟,例如以清潔來移除從平坦化步驟產生的殘留物。然而,本公開不限於此,且可透過任何其他適合的方法執行平坦化步驟。
在一些實施例中,如圖25中所示,平坦化絕緣包封體710’物理地接觸封裝結構P1’的側壁S2及導電柱CP的側壁S4。換句話說,封裝結構P1’及導電柱CP大部分嵌入在平坦化絕緣包封體710’中,僅封裝結構P1’的頂表面S1及導電柱CP的頂表面S3被以可觸及方式暴露出。在某些實施例中,封裝結構P1’的頂表面S1及導電柱CP的頂表面S3與平坦化絕緣包封體710’的頂表面S710實質上齊平。換句話說,封裝結構P1’的頂表面S1及導電柱CP的頂表面S3與平坦化絕緣包封體710’的頂表面S710實質上共面。
參照圖26,在一些實施例中,在形成平坦化絕緣包封體710’之後,在平坦化絕緣包封體710’上形成重佈線路結構720。在一些實施例中,重佈線路結構720形成在封裝結構P1’的頂表面S1、導電柱CP的頂表面S3及平坦化絕緣包封體710’的頂表面S710上。在某些實施例中,重佈線路結構720被製作成與位於之下的一個或多個連接件電連接。此處,前述一個或多個連接件可為封裝結構P1’的導電端子190及嵌入在平坦化絕緣包封體710’中的導電柱CP。換句話說,重佈線路結構720電連接到封裝結構P1’的導電端子190以及導電柱CP。
繼續參照圖26,在一些實施例中,重佈線路結構720包括交替堆疊的多個層間介電層722與多個重佈線導電層724,且重佈線導電層724電連接到封裝結構P1’的導電端子190及嵌入在平坦化絕緣包封體710’中的導電柱CP。如圖26中所示,在一些實施例中,封裝結構P1’的頂表面S1及導電柱CP的頂表面S3接觸重佈線路結構720。在此種實施例中,封裝結構P1’的頂表面S1及導電柱CP的頂表面S3物理地接觸重佈線導電層724中位於最底層的一者。在一些實施例,封裝結構P1’的頂表面S1及導電柱CP的頂表面S3被最底層的層間介電層222局部地覆蓋。在某些實施例中,最頂層的重佈線導電層224可包括多個接墊。在這種實施例中,上述接墊可包括用於球安裝的多個球下金屬(under-ball metallurgy,UBM)圖案U1和/或用於安裝附加半導體裝置(例如被動元件或主動元件)的多個連接墊(圖中未示出)。根據本公開,球下金屬圖案U1的數目不受限制。根據本公開,層間介電層722及重佈線導電層724的數目不受限制。
如圖26中所示,在一些實施例中,在形成重佈線路結構720之後,在球下金屬圖案U1上分別放置多個導電端子730。在一些實施例中,導電端子730可透過植球製程(ball placement process)放置在球下金屬圖案U1上。在一些實施例中,透過重佈線路結構720及球下金屬圖案U1,導電端子730中的一些導電端子730分別電連接到封裝結構P1’及導電柱CP。在某些實施例中,導電端子730中的一些導電端子730可為電浮置(electrically floated)或為電接地(electrically grounded),本公開不限於此。
在一些替代實施例中,附加半導體裝置可透過焊接製程(soldering process)設置並安裝在球下金屬圖案U1上。在一些實施例中,透過重佈線路結構720及球下金屬圖案U1,導電端子730中的一些導電端子730電連接到附加半導體裝置。
參照圖26及圖27,在一些實施例中,在形成重佈線路結構720及導電端子730之後,將絕緣層IN、平坦化絕緣包封體710’及封裝結構P1’從由載體C所承載的剝離層DB剝離,從而使得絕緣層IN與載體C分離。在剝離層DB為LTHC釋放層的實施例中,可使用UV雷射輻照,以方便從載體C脫除絕緣層IN。
如圖27中所示,在一些實施例中,可進一步將絕緣層IN圖案化,從而使得在絕緣層IN中形成多個接觸開口O,以暴露出導電柱CP的底表面S5。接觸開口O的數目可對應於導電柱CP的數目,本公開不限於此。在一些實施例中,絕緣層IN中的接觸開口O是透過雷射鑽孔製程(laser drilling process)或其他適合的製程形成。
參照圖28,在一些實施例中,在絕緣層IN中形成接觸開口O之後,在被接觸開口O而暴露出的導電柱CP的底表面S5上分別形成多個導電球740。並且,可例如對導電球740進行回焊(reflow)以與導電柱CP的底表面S5接合。如圖28中所示,在形成導電端子730及導電球740之後,具有雙側端子(dual-terminals)的積體扇出型(integrated fan-out,InFO)封裝的封裝結構P1’的形成便告完成。在一些實施例中,透過重佈線路結構720及導電柱CP,導電球740中的一些導電球740電連接到封裝結構P1’。在一些實施例中,透過重佈線路結構720及導電柱CP,導電球740中的一些導電球740電連接到導電端子730。在一些實施例中,透過重佈線路結構720及導電柱CP,導電球740中的一些導電球740電連接到附加半導體裝置。在某些實施例中,導電球740中的一些導電球740可為電浮置或為電接地,本公開不限於此。
參照圖29,在一些實施例中,提供封裝體800並將封裝體800接合到圖28中所繪示的結構以形成具有堆疊結構的封裝結構P6。在一些實施例中,封裝體800具有基底810、多個半導體晶粒820a及820b、多個接合線830a及830b、多個導電墊840、多個導電墊850、絕緣包封體860及多個接合焊球(圖中未示出)。舉例來說,如圖29中所示,提供具有連接膜DA1的半導體晶粒820a及具有連接膜DA2的半導體晶粒820b並將半導體晶粒820a及半導體晶粒820b安置在基底810上。在一些實施例中,連接膜DA1位於半導體晶粒220a與基底810之間,且連接膜DA2位於半導體晶粒220a與半導體晶粒220b之間。在一些實施例中,由於連接膜DA1及連接膜DA2分別設置在半導體晶粒820與基底810之間以及半導體晶粒820a與半導體晶粒820b之間,因此半導體晶粒820a、820b穩定地粘著到基底810。在一些實施例中,連接膜DA1、DA2可為例如晶粒貼合膜、由粘著劑或環氧樹脂製成的層等。
舉例來說,半導體晶粒820a及半導體晶粒820b安裝在基底810的一個表面(例如,表面S6)上。在一些實施例中,半導體晶粒820a及半導體晶粒820b可為邏輯晶片(例如,中央處理單元(central processing unit)、微控制器等)、記憶體晶片(例如,動態隨機存取記憶體(dynamic random access memory,DRAM)晶片、靜態隨機存取記憶體(static random access memory,SRAM)晶片等)、電力管理晶片(例如,電力管理積體電路(power management integrated circuit,PMIC)晶片)、射頻(RF)晶片、感測器晶片、信號處理晶片(例如,數位信號處理(digital signal processing,DSP)晶片)、前端晶片(例如,類比前端(analog front-end,AFE)晶片)、類似的晶片或其組合。舉例來說,如圖29中所示,半導體晶粒820a及半導體晶粒820b為DRAM晶片。在一個實施例中,半導體晶粒820a與半導體晶粒820b可相同。然而,本公開不限於此;在替代實施例中,半導體晶粒820a與半導體晶粒820b可彼此不同。
在一些實施例中,接合線830a及接合線830b分別用於在半導體晶粒820a、820b與位於基底810的表面S6上的導電墊840(例如接合墊)的一些導電墊840之間提供電連接。接合線830a及接合線830b使得半導體晶粒820a及半導體晶粒820b電連接到基底810。
在一些實施例中,絕緣包封體860形成在基底810的表面S6上以包封半導體晶粒820a、820b、接合線830a、830b以及導電墊840,從而保護這些元件。在一些實施例中,絕緣包封體860的材料與絕緣包封體710/平坦化絕緣包封體710’相同,且因此本文中不再予以贅述。在一個實施例中,絕緣包封體860的材料與絕緣包封體710/平坦化絕緣包封體710’不同,本公開不限於此。
在一些實施例中,可使用嵌入在基底810中的內連線(圖中未示出)或絕緣體穿孔(圖中未示出)在導電墊840與位於基底810的另一個表面(例如,與表面S6相對的表面S7)上的導電墊850(例如接合墊)之間提供電連接。在某些實施例中,除導電墊840中的一些導電墊840及接合線830a、830b之外,導電墊850中的一些導電墊850也透過這些絕緣體穿孔或內連線(圖中未示出)電連接到半導體晶粒820a及半導體晶粒820b。
在一些實施例中,封裝體800的導電墊850與導電柱CP透過夾置其間的多個接頭(joint)900電連接,其中接頭900是透過將形成在封裝體800的導電墊850上的焊料球(圖中未示出)與圖28中所繪示結構的導電球740相接合而形成。舉例來說,如圖29中所示,接頭900物理地連接到圖28中所繪示結構的導電柱CP及封裝體800的導電墊850。在一些實施例中,透過導電柱CP、接頭900及導電墊850,重佈線路結構720電連接到封裝體800的基底810。在一些實施例中,透過重佈線路結構720、導電柱CP、接頭900及導電墊850,導電端子730中的一些導電端子730電連接到封裝體800的基底810。在一些實施例中,透過重佈線路結構720、導電柱CP、接頭900及導電墊850,封裝結構P1’電連接到封裝體800的基底810。也就是說,封裝結構P1’與封裝體800透過夾置其間的接頭900而電連接且物理地連接,其中半導體晶粒820a、820b電相通(electrically communicate)到封裝結構P1’。換句話說,半導體晶粒820a、820b與封裝結構P1’的半導體晶粒140電連通。在本公開中,接頭900可被稱作用於連接到兩個封裝體(例如,圖28中所繪示其中包裝有封裝結構P1’的結構以及圖29中所繪示的封裝體800)的焊料接頭。
另外,舉例來說,如圖29中所示,底部填充膠UF填充在多個接頭900之間的間隙且包封接頭900。在一個實施例中,可透過底部填充膠分配或任何其他適合的方法來形成底部填充膠UF。在一些實施例中,底部填充膠UF的材料可與絕緣包封體710/平坦化絕緣包封體710’的材料、絕緣包封體860的材料和/或圖22中所述底部填充膠300的材料相同或不同,本公開不限於此。底部填充膠UF使得封裝結構P6的接合強度增強。
另外,圖14中所繪示封裝結構P1、圖17中所繪示封裝結構P2或圖19中所繪示封裝結構P3可以用以替換封裝結構P1’,本公開不限於此。在替代實施例中,在圖23中,可將一個或多於一個封裝結構P1’(和/或一個或多於一個封裝結構P1至P3)拾取並放置在絕緣層IN上,且可將以可移除方式接合到絕緣層IN的多個封裝結構P1’(和/或多個封裝結構P1至P3)排列成陣列。當放置在絕緣層IN上的多個封裝結構P1’(和/或多個封裝結構P1至P3)排列成陣列時,可將導電柱CP劃分成與多個封裝結構P1’(和/或多個封裝結構P1至P3)的數目對應的多個群組。
根據一些實施例,一種封裝結構包括半導體晶粒、重佈線路結構及連接墊。重佈線路結構位於半導體晶粒上且電連接到半導體晶粒。連接墊嵌入在重佈線路結構中且電連接到重佈線路結構,且連接墊包括阻障膜及位於阻障膜之下的導電圖案,其中阻障膜的表面與重佈線路結構的外表面實質上齊平。
根據一些實施例,一種封裝結構包括重佈線路結構、半導體晶粒、連接墊、鈍化層、介電層及導電端子。半導體晶粒位於重佈線路結構的第一外表面上且電連接到重佈線路結構。連接墊嵌入在重佈線路結構中且電連接到重佈線路結構,且連接墊包括阻障膜及位於阻障膜之下的導電圖案。阻障膜的表面與重佈線路結構的第二外表面實質上齊平,且第二外表面與第一外表面相對。鈍化層及介電層依序位於第二外表面上且各自局部地覆蓋連接墊。導電端子位於連接墊上且電連接到連接墊。
根據一些實施例,一種製造封裝結構的方法包括以下步驟:提供載體;在載體上安置連接墊,連接墊包括阻障膜及堆疊在阻障膜上的導電圖案;在載體上形成重佈線路結構,並將連接墊嵌入在重佈線路結構中,其中阻障膜的表面與重佈線路結構的外表面共面;在重佈線路結構上安裝半導體晶粒;將半導體晶粒包封在絕緣材料中;剝離載體以暴露出連接墊;在連接墊上依序形成鈍化層及介電層,以覆蓋被所述重佈線路結構暴露出的連接墊的部分;以及在被鈍化層及介電層暴露出的連接墊上安置導電端子。
前文概述若干實施例的特徵以使得所屬領域中具通常知識者可較佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解,其可易於使用本揭露內容作為設計或修改用於實現本文中所引入實施例的相同目的及/或達成相同優點的其他方法及結構的基礎。所屬領域中具通常知識者亦應認識到,此類等效構造並不脫離本揭露的精神及範疇,且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下於本文中作出各種改變、替代以及更改。
112、212、C:載體
114、214、DB:剝離層
120、120’、120’’:連接墊
122、122’、122’’:阻障晶種圖案
122a、SL:晶種層材料
124:導電墊
130、230、240、720:重佈線路結構
132、132-1、132-2、132-3、170、232、242:介電層
132a、132b:介電材料
134、134-1、134-2、134-3:圖案化導電層
134a、134b:金屬圖案
134s:晶種層圖案
134t:導電溝渠
134v、220:通孔
140、820a、820b:半導體晶粒
141:半導體基底
142、840、850:導電墊
143、160:鈍化層
144:後鈍化層
145:連接通孔
146:保護層
150、710、860:絕緣包封體
150a:絕緣材料
180:阻障晶種圖案
190、400、600、730:導電端子
192、194:導電元件
200:電路元件
210:芯體部
234、244、530:金屬化層
252a、252b:焊料罩幕層
254a、254b:接合墊
300、UF:底部填充膠
500、810:基底
510、520:接觸墊
710’:平坦化絕緣包封體
722:層間介電層
724:重佈線導電層
740:導電球
800:封裝體
830a、830b:接合線
900:接頭
CP:導電柱
DA1、DA2:連接膜
E1、E2、E3:虛線框
H122、H124、H132:厚度
IF:混合接合介面
IN:絕緣層
ML:金屬材料
O:接觸開口
O1、O2、O3、O4、O5、O6:開口
O1t:溝渠孔洞
O1v:通孔孔洞
P1、P1’、P2、P3、P4、P5、P6:封裝結構
R1、R2、R3:區域
S1、S3、S710:頂表面
S2、S4、S122s、S124s:側壁
S5:底表面
S6、S7、S122b、S122t、S124b、S124t、S132-1b、S132-1t、S132-3t、S132a、S150:表面
S141a:主動表面
S141b:背側表面
U1:球下金屬圖案
W122、WO3、WO4:尺寸
X、Y、Z:方向
結合附圖閱讀以下詳細描述會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,各種特徵未按比例繪製。事實上,出於論述清楚起見,可任意地增大或減小各種特徵的尺寸。
圖1至圖14示出根據本公開一些實施例的封裝結構的製造方法中的各種階段的示意性剖視圖。
圖15示出圖14中所繪示封裝結構的一部分的放大示意性剖視圖。
圖16示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。
圖17示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。
圖18示出圖17中所繪示封裝結構的一部分的放大示意性剖視圖。
圖19示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。
圖20示出圖19中所繪示封裝結構的一部分的放大示意性剖視圖。
圖21示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。
圖22示出根據本公開一些其他實施例的封裝結構的示意性剖視圖。
圖23至圖29示出根據本公開一些實施例的封裝結構的製造方法中的各種階段的示意性剖視圖。
212:載體
214:剝離層
120:連接墊
122:阻障晶種圖案
124:導電墊
130:重佈線路結構
132、132-1、132-2、132-3:介電層
132a、132b:介電材料
134、134-1、134-2、134-3:圖案化導電層
134a、134b:金屬圖案
134s:晶種層圖案
134t:導電溝渠
134v:通孔
140:半導體晶粒
141:半導體基底
142:導電墊
143、160:鈍化層
150:絕緣包封體
170:保護層
180:阻障晶種圖案
190:導電端子
192、194:導電元件
E1:虛線框
O3、O4:開口
P1:封裝結構
S150:表面
S141a:主動表面
S141b:背側表面
X、Y、Z:方向
Claims (20)
- 一種封裝結構,包括: 半導體晶粒; 重佈線路結構,位於所述半導體晶粒上且電連接到所述半導體晶粒;以及 連接墊,嵌入在所述重佈線路結構中且電連接到所述重佈線路結構,所述連接墊包括阻障膜及位於所述阻障膜之下的導電圖案,其中所述阻障膜的表面與所述重佈線路結構的外表面實質上齊平。
- 如申請專利範圍第1項所述的封裝結構,其中所述連接墊包括第一區、第二區及第三區,所述第二區位於所述第一區與所述第三區之間,且所述第三區被所述第二區及所述第一區環繞, 其中所述封裝結構更包括: 鈍化層,位於所述重佈線路結構上且至少局部地覆蓋所述連接墊; 介電層,位於所述鈍化層上且局部地覆蓋所述連接墊;以及 導電端子,位於所述連接墊上且電連接到所述連接墊。
- 如申請專利範圍第2項所述的封裝結構,其中所述阻障膜在所述連接墊的所述第一區、所述第二區及所述第三區內物理地接觸所述導電圖案, 其中所述鈍化層物理地接觸位於所述連接墊的所述第一區內的所述阻障膜的部分,所述介電層物理地接觸位於所述連接墊的所述第二區內的所述阻障膜的部分,且所述導電端子物理地接觸位於所述連接墊的所述第三區內的所述阻障膜的部分。
- 如申請專利範圍第2項所述的封裝結構,其中所述阻障膜在所述連接墊的所述第一區及所述第二區內物理地接觸所述導電圖案, 其中所述鈍化層物理地接觸位於所述連接墊的所述第一區內的所述阻障膜的部分,所述介電層物理地接觸位於所述連接墊的所述第二區內的所述阻障膜的部分,且所述導電端子物理地接觸位於所述連接墊的所述第三區內的所述導電圖案的部分。
- 如申請專利範圍第4項所述的封裝結構,其中在所述連接墊的所述第三區內、所述阻障膜與所述導電圖案的堆疊方向上,所述阻障膜不與所述導電圖案交疊。
- 如申請專利範圍第2項所述的封裝結構,其中所述阻障膜物理地接觸位於所述連接墊的所述第一區內的所述導電圖案, 其中所述鈍化層物理地接觸位於所述連接墊的所述第一區內的所述阻障膜的部分,所述介電層物理地接觸位於所述連接墊的所述第二區內的所述導電圖案的部分,且所述導電端子物理地接觸位於所述連接墊的所述第三區內的所述導電圖案的部分。
- 如申請專利範圍第6項所述的封裝結構,其中在所述連接墊的所述第二區及所述第三區內、所述阻障膜與所述導電圖案的堆疊方向上,所述阻障膜不與所述導電圖案交疊。
- 如申請專利範圍第2項所述的封裝結構,其中所述阻障膜的至少部分夾置在所述鈍化層與所述導電圖案之間。
- 如申請專利範圍第1項所述的封裝結構,更包括: 絕緣材料,包封所述半導體晶粒且位於所述重佈線路結構上。
- 如申請專利範圍第1項所述的封裝結構,更包括: 絕緣材料,包封所述半導體晶粒且位於所述重佈線路結構上; 電路基底,接合至所述重佈線路結構上且電連接到所述重佈線路結構,所述重佈線路結構夾置在所述電路基底與所述半導體晶粒之間。
- 如申請專利範圍第1項所述的封裝結構,更包括: 絕緣材料,包封所述半導體晶粒且位於所述重佈線路結構上; 電路基底,結合在所述重佈線路結構上且電連接到所述重佈線路結構,所述重佈線路結構夾置在所述電路基底與所述半導體晶粒之間;以及 中介體,具有貫穿所述中介體的多個穿孔,接合至所述重佈線路結構及所述電路基底上且電連接到所述重佈線路結構及所述電路基底。
- 一種封裝結構,包括: 重佈線路結構; 半導體晶粒,位於所述重佈線路結構的第一外表面上且電連接到所述重佈線路結構; 連接墊,嵌入在所述重佈線路結構中且電連接到所述重佈線路結構,所述連接墊包括阻障膜及位於所述阻障膜之下的導電圖案,其中所述阻障膜的表面與所述重佈線路結構的第二外表面實質上齊平,且所述第二外表面與所述第一外表面相對; 鈍化層及介電層,依序位於所述第二外表面上且各自局部地覆蓋所述連接墊;以及 導電端子,位於所述連接墊上且電連接到所述連接墊。
- 如申請專利範圍第12項所述的封裝結構,其中所述連接墊包括第一區、第二區及第三區,且所述第二區位於所述第一區與所述第三區之間並被所述第一區及所述第三區環繞, 其中所述阻障膜在所述連接墊的所述第一區、所述第二區及所述第三區內物理地接觸所述導電圖案, 其中所述鈍化層物理地接觸位於所述第一區內的所述阻障膜的部分,所述介電層物理地接觸位於所述第二區內的所述阻障膜的部分,且所述導電端子物理地接觸位於所述第三區內的所述阻障膜的部分。
- 如申請專利範圍第12項所述的封裝結構,其中所述連接墊包括第一區、第二區及第三區,且所述第二區位於所述第一區與所述第三區之間並被所述第一區及所述第三區環繞, 其中所述阻障膜在所述連接墊的所述第一區及所述第二區內物理地接觸所述導電圖案, 其中所述鈍化層物理地接觸位於所述第一區內的所述阻障膜的部分,所述介電層物理地接觸位於所述第二區內的所述阻障膜的部分,且所述導電端子物理地接觸位於所述第三區內的所述導電圖案的部分。
- 如申請專利範圍第12項所述的封裝結構,其中所述連接墊包括第一區、第二區及第三區,且所述第二區位於所述第一區與所述第三區之間並被所述第一區及所述第三區環繞, 其中所述阻障膜在所述連接墊的所述第一區內物理地接觸所述導電圖案, 其中所述鈍化層物理地接觸位於所述第一區內的所述阻障膜的部分,所述介電層物理地接觸位於所述第二區內的所述導電圖案的部分,且所述導電端子物理地接觸位於所述第三區內的所述導電圖案的部分。
- 如申請專利範圍第12項所述的封裝結構,其中所述導電端子包括導電部及夾置在所述導電部與所述阻障膜之間的阻障部,且所述阻障部物理地接觸所述阻障膜。
- 一種製造封裝結構的方法,包括: 提供載體; 在所述載體上安置連接墊,所述連接墊包括阻障膜及堆疊在所述阻障膜上的導電圖案; 在所述載體上形成重佈線路結構,並將所述連接墊嵌入在所述重佈線路結構中,其中所述阻障膜的表面與所述重佈線路結構的外表面共面; 在所述重佈線路結構上安裝半導體晶粒; 將所述半導體晶粒包封在絕緣材料中; 剝離所述載體以暴露出所述連接墊; 在所述連接墊上依序形成鈍化層及介電層,以覆蓋被所述重佈線路結構暴露出的所述連接墊的部分;以及 在被所述鈍化層及所述介電層暴露出的所述連接墊上安置導電端子。
- 如申請專利範圍第17項所述的製造封裝結構的方法,其中所述連接墊包括第一區、第二區及第三區,且所述第二區夾置在所述第一區與所述第三區之間, 在所述連接墊上依序形成所述鈍化層及所述介電層包括: 在所述連接墊上形成所述鈍化層,並將所述鈍化層圖案化以在所述第二區及所述第三區之上具有第一開口,所述鈍化層在所述第一區內物理地接觸所述阻障膜;以及 在所述連接墊上形成所述介電層,並將所述介電層圖案化以在所述第三區之上具有第二開口,所述介電層在所述第二區內物理地接觸所述阻障膜, 其中所述導電端子在所述第三區內物理地接觸所述阻障膜。
- 如申請專利範圍第17項所述的製造封裝結構的方法,其中所述連接墊包括第一區、第二區及第三區,且所述第二區夾置在所述第一區與所述第三區之間, 在所述連接墊上依序形成所述鈍化層及所述介電層包括: 在所述連接墊上形成所述鈍化層,並將所述鈍化層圖案化以在所述第二區及所述第三區之上具有第一開口,所述鈍化層在所述第一區內物理地接觸所述阻障膜;以及 在所述連接墊上形成所述介電層,並將所述介電層圖案化以在所述第三區之上具有第二開口,所述介電層在所述第二區內物理地接觸所述阻障膜,其中將所述介電層圖案化以具有所述第二開口更包括移除與所述連接墊的所述第三區對應的所述阻障膜的部分, 其中所述導電端子在所述第三區內物理地接觸所述導電圖案。
- 如申請專利範圍第17項所述的製造封裝結構的方法,其中所述連接墊包括第一區、第二區及第三區,且所述第二區夾置在所述第一區與所述第三區之間, 在所述連接墊上依序形成所述鈍化層及所述介電層包括: 在所述連接墊上形成所述鈍化層,並將所述鈍化層圖案化以在所述第二區及所述第三區之上具有第一開口,所述鈍化層在所述第一區內物理地接觸所述阻障膜,其中將所述鈍化層圖案化以具有所述第一開口更包括移除與所述連接墊的所述第二區及所述第三區對應的所述阻障膜的部分;以及 在所述連接墊上形成所述介電層,並將所述介電層圖案化以在所述第三區之上具有第二開口,所述介電層在所述第二區內物理地接觸所述導電圖案, 其中所述導電端子在所述連接墊的所述第三區內物理地接觸所述導電圖案。
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