TW202038885A - Storage box - Google Patents

Abstract

A storage box includes a box body, M*N infrared sensors and light emitting diodes(LEDs), a logic unit and a processing unit. The logic unit includes a plurality of three-state output latches, wherein M*N generates M*N driving signals based on M first control signals and N input and output signals to control the LEDs to emit light. The other M*N three-state output latches output N of M*N sensing signals of the infrared sensors to the N input and output signals based on M second control signals. The processing unit generates the first control signals and the second control signals, and obtains the M*N sensing signals by the N input and output signals at different time, and further, generated the M*N driving signals by the N input and output signals at different time based on the M*N sensing signals.

Description

Storage Box

The present invention relates to a storage box, in particular to a medicine storage box equipped with a light-emitting diode to display the storage state.

The conventional drug storage box includes a plurality of storage spaces for accommodating drugs, a plurality of infrared sensors that respectively sense whether the storage spaces contain drugs, and a plurality of corresponding storage spaces to display whether the drugs are accommodated. Light emitting diode and a processing unit. The processing unit is electrically connected to the infrared sensors to receive a plurality of sensing signals, and is also electrically connected to the light emitting diodes, and generates a plurality of driving signals according to the sensing signals to control the light emitting The diodes respectively emit light or no light in the storage spaces to correspondingly display whether each storage space contains medicines.

For example, the number of the storage spaces is 6*7 equal to 42, and the storage spaces are arranged in a matrix to correspond to a maximum of six medications per day, seven days a week. When all the 42 storage spaces contain medicines, the processing unit generates the 42 driving signals according to the 42 sensing signals, so that the 42 light-emitting diodes emit light. When the medicine in the first column and row 1 is taken, similarly, the processing unit controls the corresponding light-emitting diode to not emit light in the storage space of the first column and row 1, and controls the remaining 41 light-emitting diodes The body keeps emitting light in the other 41 storage spaces.

The first conventional processing unit uses M*N (ie 42) sensing signals and M*N (ie 42) drive signals. Therefore, the processing unit requires a total of 84 pins. When the processing unit has fewer than 84 pins, multiple processing units need to be installed, which is not economical. Alternatively, the second conventional processing unit uses a matrix control method to generate the driving signals, so the number of the driving signals can be reduced to M+N (that is, 13), so that the total required pins are reduced To M+N+M*N (ie 55). However, because the second processing unit adopts a matrix control method, the light emission of the light-emitting diodes is restricted.

Referring to FIG. 1, FIG. 1 uses eight control signals in four rows and four columns and the corresponding sixteen light-emitting diodes as examples to illustrate the problem of the second conventional control method. When it is desired to control the light-emitting diodes located in the R2 column and the C2 row to emit light, the two control signals in the R2 column and the C2 row are represented by solid lines as being changed by a logic value such as a logic 1 to complete. Similarly, when it is desired to control the light emitting diode located in the R3 column and the C3 row to emit light, the two control signals in the R3 column and the C3 row are represented by solid lines. However, when you want to control the two light-emitting diodes in the R2 column, the C2 row and the R3 column and C3 row to emit light at the same time, you need to control the four in the R2 column, C2 row, R3 column, and C3 row. The logic value of the control signal is, for example, logic 1 (represented by a solid line), but the other two light-emitting diodes in the R2 column and C3 row and R3 and C2 row also emit light, causing false display. That is to say, the use of the processing unit in the matrix form of control will cause the light emission of the light-emitting diodes to be limited by the circuit, and only a single or single row of light-emitting diodes can be displayed at a time, and the correctness cannot be simultaneously performed Control multiple coupling (Coupling) light-emitting diodes. Therefore, it has become a problem to be solved to provide a medicine storage box that uses a processing unit with a smaller number of feet to reduce the cost.

Therefore, the object of the present invention is to provide a storage box that uses a small number of input/output signals or pin processing units.

Therefore, the storage box of the present invention includes a box body, M*N infrared sensors, M*N light-emitting diodes, a logic unit, and a processing unit. Both M and N are positive integers.

The box body includes M*N storage spaces arranged in a matrix. The M*N infrared sensors are arranged in the box, and respectively detect whether the storage spaces contain an object, and generate M*N sensing signals. The M*N light-emitting diodes are arranged in the box body, and receive M*N drive signals respectively, so as to be controlled to determine correspondingly to emit light or not to emit light in the storage spaces.

The logic unit is electrically connected to the infrared sensors and the light emitting diodes, and includes M*N*2 three-state output latches. The M*N three-state output latches are defined as the first three-state output latch, and the other M*N three-state output latches are defined as the second three-state output latches. The first three-state output latches receive and generate the M*N drive signals in turn according to the M first control signals and the N input and output signals. The second three-state output latches receive and according to M second control signals, output N of the M*N sensing signals to the N input/output signals in turn.

The processing unit is electrically connected to the logic unit, and generates the M first control signals and the M second control signals, and obtains the M*N signals in turn according to the N input and output signals at different time points Sensing signals, and then generating the M*N driving signals in sequence through the N input and output signals at different time points according to the M*N sensing signals.

In some embodiments, the processing unit uses the M first control signals to make the M*N first three-state output latches keep outputting the logic value of the previous state, and uses the M The logic value of one of the second control signals is equal to a first logic value in turn, so as to obtain the output of the M*N second three-state output latch by the N input and output signals in turn N of the M*N sensing signals, and then obtaining the logic value of the M*N sensing signals.

In some implementations, the processing unit determines the logical values of the M*N driving signals according to the logical values of the M*N sensing signals, and uses the M second control signals to make the The output of the M*N second three-state output latches is in a high impedance state, and the logic value of one of the M first control signals is sequentially equal to a second logic value by turns The N input and output signals sequentially output N of the logic values determined by the M*N drive signals to N of the M*N first three-state output latches, thereby generating the M *N drive signals.

In some embodiments, each of the three-state output latches includes a consistent energy end, a latch end, a data end, and an output end, and the M*N first three-state output latches According to the matrix arrangement of the M*N storage spaces, they are defined and classified as belonging to the same row or the same column. The enable terminals of the M*N first three-state output latches receive the first logic value, and the latch terminals of the N first three-state output latches in the same column receive the M The same one of the first control signals, the data terminals of the N first three-state output latches in the same row receive the N input and output signals, and the M*N first three-state output latches The output terminals output the M*N driving signals.

In some embodiments, the M*N second three-state output latches are respectively defined and classified as belonging to the same row or the same column according to the matrix arrangement of the M*N storage spaces. The enabling ends of the N second three-state output latches in the same column receive the same one of the M second control signals, and the pins of the M*N second three-state output latches The lock terminal receives the second logic value, the data terminals of the M*N second three-state output latches receive the M*N sensing signals, and the N second three-state output latches in the same row are locked The output terminals of the converter output the N input and output signals.

In some embodiments, the enable terminal, the latch terminal, the data terminal, and the signal received or output by the output terminal of each of the three-state output latches have the following logical relationship .

When the logic value of the signal received by the enable terminal and the latch terminal is equal to the first logic value and the second logic value, respectively, the logic value of the signal output by the output terminal is equal to the signal received by the data terminal The logical value. When the logic values of the signals received by the enable terminal and the latch terminal are both equal to the first logic value, the logic value of the signal output by the output terminal is equal to the logic value maintained in the previous state. When the logic value of the signal received by the enable terminal is equal to the second logic value, the output of the output terminal is in the high impedance state.

In some embodiments, each of the three-state output latches further includes a first inverter, a first buffer, a D-type latch, and a second buffer. The first inverter includes an input terminal electrically connected to the enable terminal of the three-state output latch, and an output terminal. The first buffer includes an input terminal electrically connected to the latch terminal of the three-state output latch, and an output terminal. The D-type latch includes a latch terminal electrically connected to the output terminal of the first buffer, a data terminal electrically connected to the data terminal of the three-state output latch, and an output terminal.

The second buffer includes an input terminal electrically connected to the output terminal of the D-type latch, a control terminal electrically connected to the output terminal of the first inverter, and a control terminal electrically connected to the three-state output latch The output terminal of this output terminal. When the logic value of the signal received by the control terminal is equal to the first logic value, the output of the output terminal is in the high impedance state. When the logic value of the signal received by the control terminal is equal to the second logic value, the logic value of the signal output by the output terminal is equal to the logic value of the signal received by the input terminal.

In some implementation aspects, wherein the D-type latch of each of the three-state output latches further includes a reverse gate, a first and gate, a second and gate, a first reverse or gate, And a second reverse or gate. The reverse gate includes an input terminal electrically connected to the data terminal of the D-type latch, and an output terminal. The first and gate includes a first input terminal electrically connected to the output terminal of the reverse gate, a second input terminal electrically connected to the latch terminal of the D-type latch, and an output terminal. The second gate includes a first input terminal electrically connected to the latch end of the D-type latch, a second input terminal electrically connected to the data terminal of the D-type latch, and an output terminal.

The first reverse OR gate includes a first input terminal electrically connected to the output terminal of the first and gate, a second input terminal, and an output terminal electrically connected to the output terminal of the D-type latch. The second inverter or gate includes a first input terminal electrically connected to the output terminal of the first inverter or gate, a second input terminal electrically connected to the output terminal of the second inverter, and a second input terminal electrically connected to the first inverter Or the output end of the second input end of the gate.

In other embodiments, the processing unit uses the M first control signals to make the M*N first three-state output latches keep outputting the logic value of the previous state, and uses the The logic value of one of the M second control signals is equal to a first logic value, so as to obtain the M*N output by the M*N second three-state output latches by the N input/output signals N of the M*N sensing signals are then obtained to obtain the logic value of N of the M*N sensing signals.

The processing unit then uses the M second control signals to make the output of the M*N second three-state output latches a high impedance state, and uses one of the M first control signals The logic value of is equal to a second logic value, so that N of the logic values determined by the M*N driving signals are output to the M*N first three-state output latches through the N input/output signals N of the M*N drive signals generate logic values of N of the M*N driving signals.

The processing unit sequentially obtains the logic values of the other N of the M*N sensing signals by the other one of the M second control signals, and then uses the M first control signals The other one is to generate the logic values of the other N of the M*N driving signals, so as to obtain the M*N sensing signals and generate the M*N driving signals.

The effect of the present invention is that the M*N first three-state output latches store the logic values to be driven corresponding to the driving signals, and the M*N second three-state output latches store Corresponding to the logic values of the sensing signals, and through the N input and output signals, the M first control signals, and the M second control signals, the processing unit can obtain the M in turn in sequence. *The sensing signals detected by N infrared sensors, and the driving signals required by the M*N light-emitting diodes are output correctly and sequentially in turn. Compared with the conventional technology, it can greatly Reduce the number of signals or pins required by the processing unit.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are represented by the same numbers.

Referring to Figure 2, an embodiment of the storage box 100 of the present invention includes a box body 5, M*N infrared sensors 4, M*N light emitting diodes (LED) 3, a logic unit 2, and a processing unit Unit 1. The box body 5 includes M*N storage spaces 9 arranged in a matrix. Both M and N are positive integers, usually greater than 1. In this embodiment, the storage box 100 is a medicine storage box, M is equal to 6, N is equal to 7, to indicate a total of 6 columns and 7 rows, and correspondingly indicate that the drug is taken up to six times a day, seven days a week, but not This is limited. In addition, it should be supplemented that the configuration of each storage space 9 is similar. Therefore, for convenience of description, FIG. 2 simply shows a storage space 9, an infrared sensor 4, and a light-emitting diode The label of 3.

2 and 3, the M*N infrared sensors 4 are arranged on the box body 5, and respectively detect whether the storage spaces 9 contain an object (such as medicine), and generate M*N sensors Test signal IR_OUT[X,Y]. In this embodiment, the 6*7 infrared sensors 4 are respectively defined as infrared sensors 4 [X, Y], X is equal to 0, 1,..., M-1 (that is, 0~5), Y Equal to 0, 1,..., N-1 (ie 0~6) to represent the infrared sensor 4[X,Y] in the X+1th column and Y+1th row, and correspondingly generate the sensing signals IR_OUT[X,Y]. For example, when the infrared sensor 4[1,2] in the second column and the third row detects that the corresponding storage space 9 does not contain a medicine, the generated sensing signal IR_OUT[1 The logic value of ,2] is equal to a first logic value (such as logic 0), or, when a medicine is contained, the logic value of the sensing signal IR_OUT[1,2] is equal to a second logic value (such as logic 1 ).

The M*N light emitting diodes 3 are arranged in the box body 5, and respectively receive M*N drive signals LED_EN[X,Y], to be controlled to determine whether to emit light or not to emit light in the storage spaces 9 respectively . In this embodiment, the 6*7 light-emitting diodes 3 are respectively defined as light-emitting diodes 3 [X, Y] to represent the light-emitting diodes 3 in the X+1th column and Y+1th row. [X,Y], and correspondingly receive these drive signals LED_EN[X,Y]. For example, when the logic value of the driving signal LED_EN[2,3] received by the light emitting diode 3[2,3] in the third column and fourth row is equal to the first logic value (such as logic 0) When the light-emitting diode 3[2,3] does not emit light, or the logic value of the driving signal LED_EN[2,3] is equal to the second logic value (such as logic 1), it emits light.

Referring to Figure 3, Figure 4, and Figure 5, the logic unit 2 is electrically connected to the infrared sensors 4 [X, Y] and the light emitting diodes 3 [X, Y], and includes M*N*2 One (ie 84) three-state output latches. The M*N three-state output latches are defined as the first three-state output latches 20[X,Y] to indicate the corresponding storage space 9 in the X+1th column and Y+1th row. Three-state output latches, and the other M*N three-state output latches are defined as the second three-state output latches 21[X,Y] to indicate the corresponding X+1th column Y+1 The three-state output latch of the storage space 9 of the row. The first three-state output latches 20[X,Y] receive and generate the M*N drives in turn according to M first control signals LED_LE[X] and N input/output signals DATA[Y] Signal LED_EN[X,Y]. The second three-state output latches 21[X,Y] receive and according to the M second control signals IR_OE[X], N of the M*N sensing signals IR_OUT[X,Y] take turns Sequentially output to the N input/output signals DATA[Y].

6 and 7, for convenience of description, FIG. 6 only uses the seven first three-state output latches 20 corresponding to the storage spaces 9 in the sixth column (ie, X=5) [5, Y ] And the seven second three-state output latches 21 [5, Y] as an example for illustration, and the first three-state output latches 20 [0, Y], 20 corresponding to other columns are not shown. [1,Y], 20[2,Y], 20[3,Y], 20[4,Y] and the second three-state output latches 21[0,Y], 21[1,Y] , 21[2,Y], 21[3,Y], 21[4,Y].

Each of the three-state output latches (that is, the first three-state output latches 20 [X, Y] and the second three-state output latches 21 [X, Y]) includes unanimous energy ends 26, one The latching terminal 27, a data terminal 28, and an output terminal 29. The enabling terminals 26 of the M*N first three-state output latches 20 [X, Y] are electrically connected to a ground terminal to receive the first logic value (ie, logic 0). The latch terminals 27 of the N first three-state output latches 20 [X, Y] in the same column receive the same one of the M first control signals LED_LE [X], such as the first three The latching ends 27 of the state output latch 20[5,Y] respectively receive the first control signals LED_LE[5] and the first three-state output latches 20[4,Y] The latch terminals 27 respectively receive the first control signals LED_LE[4], and the latch terminals 27 of the first three-state output latches 20[3,Y] respectively receive the first control signals LED_LE[ 3]. The latch ends 27 of the first three-state output latches 20[2, Y] respectively receive the first control signals LED_LE[2], the first three-state output latches 20 The latching ends 27 of [1,Y] respectively receive the first control signal LED_LE[1] and the latching ends 27 of the first three-state output latches 20[0,Y], respectively Receive the first control signals LED_LE[0].

The data terminals 28 of the N first three-state output latches 20 [X, Y] in the same row receive the N input and output signals DATA[Y], such as the first three-state output latches 20 The data terminals 28 of [5,Y] respectively receive the N input/output signals DATA[Y], and the data terminals 28 of the first three-state output latches 20[4,Y] respectively receive the N Input/output signals DATA[Y], the data terminals 28 of the first three-state output latches 20[3,Y] respectively receive the N input/output signals DATA[Y], the first three-state The data terminals 28 of the output latch 20[2,Y] respectively receive the N input/output signals DATA[Y] and the data terminals of the first three-state output latch 20[1,Y] 28 respectively receive the N input/output signals DATA[Y] and the data terminals 28 of the first three-state output latches 20[0, Y] respectively receive the N input/output signals DATA[Y]. The output terminals 29 of the M*N first three-state output latches 20[X,Y] output the M*N driving signals LED_EN[X,Y] respectively.

The enabling terminals 26 of the N second three-state output latches 21[X,Y] in the same column receive the same one of the M second control signals IR_OE[X], such as the second and third The enabling terminals 26 of the state output latch 21[5,Y] respectively receive the second control signals IR_OE[5] and the second three-state output latch 21[4,Y]. The enabling terminals 26 respectively receive the second control signals IR_OE[4], and the enabling terminals 26 of the second three-state output latches 21[3,Y] respectively receive the second control signals IR_OE[ 3]. The enabling terminals 26 of the second three-state output latches 21 [2, Y] respectively receive the second control signals IR_OE[2] and the second three-state output latches 21 The enabling terminals 26 of [1,Y] respectively receive the second control signals IR_OE[1] and the enabling terminals 26 of the second three-state output latch 21[0,Y], respectively Receive the second control signals IR_OE[0].

The latch terminals 27 of the M*N second three-state output latches 21 [X, Y] are electrically connected to a power terminal to receive the second logic value (ie, logic 1). The data terminals 28 of the M*N second three-state output latches 21[X,Y] respectively receive the M*N sensing signals IR_OUT[X,Y]. The output terminals 29 of the N second three-state output latches 21 [X, Y] in the same column respectively output the N input and output signals DATA[Y], such as the second three-state output latches The output terminals 29 of 21[5,Y] respectively output the N input/output signals DATA[Y], and the output terminals 29 of the second three-state output latch 21[4,Y] respectively output the The N input/output signals DATA[Y], the output terminals 29 of the second three-state output latches 21[3,Y] output the N input/output signals DATA[Y], the second and third The output terminals 29 of the state output latch 21[2,Y] respectively output the N input/output signals DATA[Y] and the outputs of the second three-state output latch 21[1,Y] The terminal 29 respectively outputs the N input/output signals DATA[Y], and the output terminals 29 of the second three-state output latches 21[0,Y] output the N input/output signals DATA[Y] respectively .

Refer to the following table 1, each of the three-state output latches (ie, the first three-state output latch 20[X,Y] and the second three-state output latch 21[X,Y]) The enable terminal 26, the latch terminal 27, the data terminal 28, and the signals received or output by the output terminal 29 have the following logical relationship. input signal output signal Enable end 26 Latch end 27 Data port 28 Output 29 0 1 1 1 0 1 0 0 0 0 X Previous state 1 X X Z Form One

That is, when the logic values of the signals received by the enable terminal 26 and the latch terminal 27 are respectively equal to the first logic value (ie logic 0) and the second logic value (ie logic 1), the output The logic value of the signal output by the terminal 29 is equal to the logic value of the signal received by the data terminal 28.

When the logic value of the signal received by the enable terminal 26 and the latch terminal 27 is equal to the first logic value (ie, logic 0), the logic value of the signal output by the output terminal 29 is equal to the previous state The logical value. When the logic value of the signal received by the enable terminal 26 is equal to the second logic value (ie, logic 1), the output of the output terminal 29 is in a high impedance state. From Figure 6 and Table 1, it can be seen that the latching terminals 27 of the M*N second three-state output latch 21[X,Y] are kept at logic 1 (that is, electrically connected to the power terminal) to ensure that the When the logic value of one of the second control signals IR_OE[X] at the enable terminal 26 is equal to logic 0, the input/output signals DATA[Y] at the output terminals 29 and the data terminals The logic values of the corresponding ones of the sensing signals IR_OUT[X,Y] of 28 remain the same, and the logic values of the rest of the second control signals IR_OE[X] remain equal to logic 1, without interference These input and output signals DATA[Y].

Referring again to FIG. 7, in more detail, each of the three-state output latches (that is, the first three-state output latch 20[X, Y] and the second three-state output latch 21[X, Y]) also includes a first inverter 23, a first buffer 24, a D-type latch 22, and a second buffer 25, which means that each of the three-state output latches is a Transparent D-Type Latch with 3-State Outputs. The first inverter 23 includes an input terminal electrically connected to the enable terminal 26 of the three-state output latch, and an output terminal. The first buffer 24 includes an input terminal electrically connected to the latch terminal 27 of the three-state output latch, and an output terminal. The D-type latch 22 includes a latch terminal E electrically connected to the output terminal of the first buffer 24, a data terminal D electrically connected to the data terminal 28 of the three-state output latch, and an output terminal Q.

The second buffer 25 includes an input terminal electrically connected to the output terminal Q of the D-type latch 22, a control terminal electrically connected to the output terminal of the first inverter 23, and a control terminal electrically connected to the tri-state The output terminal of the output terminal 29 of the output latch. When the logic value of the signal received by the control terminal of the second buffer 25 is equal to the first logic value (ie, logic 0), the output of the output terminal of the second buffer 25 is in the high impedance state. When the logic value of the signal received by the control terminal of the second buffer 25 is equal to the second logic value (ie, logic 1), the logic value of the signal output by the output terminal of the second buffer 25 is equal to the The logical value of the signal received at the input.

The signals received or output by the latch terminal E, the data terminal D, and the output terminal Q of the D-type latch 22 have the following logical relationship. When the logic value of the signal received by the latch terminal E and the data terminal D is equal to the first logic value (ie, logic 0), the logic value of the signal output by the output terminal Q is equal to the one that remains in the previous state Logical value. When the logic values of the signals received by the latch terminal E and the data terminal D are equal to the first logic value (ie logic 0) and the second logic value (ie logic 1), the output terminal Q outputs The logical value of the signal is equal to the logical value maintained in the previous state.

When the logic values of the signals received by the latch terminal E and the data terminal D are both equal to the second logic value (ie logic 1) and the first logic value (ie logic 0), the output terminal Q outputs The logic value of the signal is equal to the first logic value (ie, logic 0). When the logic value of the signal received by the latch terminal E and the data terminal D is equal to the second logic value (ie, logic 1), the logic value of the signal output by the output terminal Q is equal to the second logic value ( That is logic 1).

Referring to FIG. 8, the internal circuit of a D-type latch 22 is illustrated, which also includes an INV gate 221, a first AND gate 222, a second AND gate 223, A first NOR gate 224 and a second NOR gate 225.

The reverse gate 221 includes an input terminal electrically connected to the data terminal D of the D-type latch 22, and an output terminal. The first and gate 222 includes a first input terminal electrically connected to the output terminal of the reverse gate 221, a second input terminal electrically connected to the latch terminal E of the D-type latch 22, and an output terminal. The second and gate 223 includes a first input terminal electrically connected to the latch end E of the D-type latch 22, a second input terminal electrically connected to the data terminal D of the D-type latch 22, And an output terminal.

The first inverter 224 includes a first input terminal electrically connected to the output terminal of the first and gate 222, a second input terminal, and an output terminal electrically connected to the output terminal Q of the D-type latch 22 end. The second inverter gate 225 includes a first input terminal electrically connected to the output terminal of the first inverter gate 224, a second input terminal electrically connected to the output terminal of the second inverter gate 223, and a second input terminal electrically connected to the The output terminal of the second input terminal of the first inverter 224.

2 and FIG. 9, FIG. 9 is a flowchart illustrating the control steps of the processing unit 1, including steps S1 to S3.

In step S1, the execution is started, and then step S2 is executed.

In step S2, sub-process 1 (ie S2) is executed, including steps S21 to S25, and then step S3 is executed.

In step S21, set the variable i=0, and then execute step S22.

In step S22, the processing unit 1 controls the generated second control signal IR_OE[i]=0 (that is, IR_OE[0] is logic 0, and other IR_OE[1:5] remains at logic 1), and then executes Step S23.

In step S23, the processing unit 1 stores the logic values of the input/output signals DATA[6:0], and then executes step S24.

In step S24, the processing unit 1 controls the generated second control signal IR_OE[i]=1, and calculates i=i+1 (that is, the updated i is equal to 1), and then executes step S25.

In step S25, the processing unit 1 determines whether i is less than 6, and when it is determined that i is less than 6, execute step S22. When it is determined that i is not less than 6, step S3 is executed.

In step S3, sub-process 2 (ie S3) is executed, including steps S31 to S35, and then step S2 is executed.

In step S31, set the variable j=0, and then execute step S32.

In step S32, the processing unit 1 controls the generated first control signal LED_LE[j]=1 (that is, LED_LE[0] is logic 1, and other LED_LE[1:5] remain at logic 0), that is In other words, the logic values of the drive signals LED_EN[j,Y] of the output terminals 29 of the first three-state output latches 20[j,Y] of the logic unit 2 will be synchronously equal to the data terminals The logical value of the input/output signal DATA[Y] of 28, that is, during each turn, the processing unit 1 controls the update of the on and off states of seven light-emitting diodes at the same time. Then, step S33 is executed.

In step S33, the processing unit 1 writes the logic values stored in step S23 into the input/output signals DATA[6:0] correspondingly, and then executes step S34.

In step S34, the processing unit 1 controls the generated first control signal LED_LE[j]=0, and calculates j=j+1 (that is, the updated j is equal to 1), and then executes step S35.

In step S35, the processing unit 1 determines whether j is less than 6, and when it is determined that j is less than 6, execute step S32. And when it is judged that j is not less than 6, step S2 is executed.

In summary, the processing unit 1 is electrically connected to the logic unit 2, and generates the M first control signals LED_LE[X] and the M second control signals IR_OE[X], and also uses the M first control signals LED_LE[X] at different time points. N input and output signals DATA[Y] obtain the M*N sensing signals IR_OUT[X,Y] in turn, and then according to the M*N sensing signals IR_OUT[X,Y] at different time points by The N input and output signals DATA[Y], in turn, sequentially generate the M*N drive signals LED_EN[X,Y].

In more detail, the processing unit 1 controls the generated logic values of the M first control signals LED_LE[X] to be equal to the first logic value (ie, logic 0), so that the M*N first three-state outputs The logic values of the signals received by the enable terminals 26 and the latch terminals 27 of the latch 20[X, Y] are all equal to the first logic value (ie logic 0), so that the M*N The logic values of the signals output from the output terminals 29 of the first three-state output latch 20[X,Y] (that is, output to the M*N drive signals LED_EN[X,Y]) remain in the previous state The logical value.

The processing unit also controls the logic value of one of the generated M second control signals IR_OE[X] (such as IR_OE[5]) to be equal to the first logic value (ie logic 0) in turn, and the rest The logic value of the M-1 second control signal (such as IR_OE[4]~[0]) is equal to the second logic value (ie logic 1), so that the M*N second three-state output latches 21 The logic values of the signals received by the N enable terminals 26 and the latch terminals 27 corresponding to that one of [X,Y] (such as 21[5,Y]) are respectively equal to the first logic Value (ie, logic 0) and the second logic value (ie, logic 1), so that the M*N second three-state output latch 21[X,Y] corresponds to the one (such as 21[5, The logic value of the signal (ie DATA[Y]) output by the output terminals 29 of Y]) is equal to the logic value of the signal received by the data terminals 28 (ie IR_OUT[5, Y]). In other words, at this time, the remaining (M-1)*N second three-state output latches (such as 21[4,Y], 21[3,Y], 21[2,Y], 21[ The logic values of the signals received by the enable terminals 26 of 1, Y] and 21 [0, Y]) are all equal to the second logic value (ie logic 1), so that the (M-1)*N The output of the output terminals 29 of the second three-state output latch is in the high impedance state without affecting the corresponding one of the M*N second three-state output latches 21[X,Y] ( For example, the logic values of the input and output signals DATA[Y] respectively output by the output terminals 29 of 21[5,Y]).

Therefore, the processing unit 1 can obtain the M*N second three-state output latches 21[X,Y] outputted by the M*N second three-state output latches 21[X,Y] in turn by the N input/output signals DATA[Y] N of the sensing signals IR_OUT[X,Y] (that is, corresponding to the same column) are detected, and the logical values of the M*N sensing signals IR_OUT[X,Y] are obtained. For example, the processing unit 1 obtains the M*N sensing signals through the M second control signals IR_OE[X] whose X is equal to 0, 1,..., M-1 (ie, 0~5) in sequence The logic value of the signal IR_OUT[X, Y] can be used to obtain whether the M*N storage spaces 9 of the box body contain medicines.

Furthermore, the processing unit 1 determines the logical values of the M*N driving signals LED_EN[X,Y] according to the logical values of the M*N sensing signals IR_OUT[X,Y], for example, the M*N driving signals LED_EN[X,Y] *N storage spaces 9 all contain medicines, and the logic value of the M*N sensing signals IR_OUT[X,Y] is equal to the second logic value (ie logic 1), then the processing unit 1 determines the M* The logic value of the N drive signals LED_EN[X,Y] is also equal to the second logic value (ie logic 1) to drive the M*N light-emitting diodes 3[X,Y] to emit light to indicate that The storage space 9 contains medicines.

In more detail, the logic value of the M second control signals IR_OE[X] generated by the processing unit 1 is equal to the second logic value (ie, logic 1), so that the M*N second three-state output The output of the output terminals 29 of the latch 21 [X, Y] is in the high impedance state without affecting the logic value of the input and output signals DATA[Y].

The processing unit 1 also controls the logic value of one of the M first control signals LED_LE[X] (such as LED_LE[5]) to be equal to the second logic value (logic 1) in turn, and the rest The logic value of the M-1 first control signals (such as LED_LE[4]~[0]) is equal to the first logic value (ie logic 0), so that the M*N first three-state output latches 20 The logic values of the signals received by the N enable terminals 26 and the latch terminals 27 corresponding to the one of [X, Y] (such as 20[5, Y]) are respectively equal to the first logic Value (ie logic 0) and the second logic value (ie logic 1), so that the M*N first three-state output latches 20[X,Y] correspond to one of them (such as 20[5, The logic value of the signal output by the output terminals 29 of Y]) (ie LED_EN[5, Y]) is equal to the logic value of the signal received by the data terminal 28 (ie DATA[Y]). In other words, at this time, the remaining (M-1)*N first three-state output latches (20[4,Y], 20[3,Y], 20[2,Y], 20[1 ,Y], 20[0,Y]), the logic values of the signals received by the enable terminals 26 and the latch terminals 27 are all equal to the first logic value (ie logic 0), so that the (M -1) The outputs of the output terminals 29 of the *N first three-state output latches maintain the logic value of the previous state, and are not affected by the input and output signals DATA[Y].

Therefore, the processing unit 1 can output N of the logic values determined by the M*N driving signals LED_EN[X,Y] to the M* by the N input/output signals DATA[Y] in turn. N of the N first three-state output latches 20[X, Y] generate the M*N drive signals LED_EN[X, Y]. For example, the processing unit 1 sequentially inputs the driving signals LED_EN[X,Y] corresponding to the first row to the sixth row by the generated logic values of the N input and output signals DATA[Y], and then Drive the M*N light-emitting diodes 3[X,Y] to emit light or not to emit light.

In addition, it should be noted that: in this embodiment, the processing unit 1 is, for example, a microcontroller, and according to the sequence of different columns, first read all the sensing signals IR_OUT[X,Y] and then The drive signals LED_EN[X,Y] are sequentially generated. In other embodiments, because the processing unit 1 generates the first control signals LED_LE[X] and the second control signals IR_OE[X] in a short period of time, the processing unit 1 also It is possible to read the sensing signal IR_OUT[X,Y] of the same column first and then generate the driving signal LED_EN[X,Y] of the same column according to the sequence of different columns, which is not limited.

In addition, in this embodiment, each storage space 9 corresponds to only one light-emitting diode 3, while in other embodiments, each storage space 9 may also correspond to two light-emitting diodes, one of which is The light emission indicates that the storage space 9 contains medicines, and the other light emission indicates that the storage space 9 does not contain medicines. Alternatively, each storage space 9 can also correspond to more than three light-emitting diodes, and use corresponding three-state output latches to receive corresponding multiple sensing signals and generate corresponding multiple driving signals .

In summary, the first three-state output latches store the logic values to be driven corresponding to the driving signals, and the second three-state output latches store the corresponding sensing signals The logic value of, and through the N input and output signals, the M first control signals, and the M second control signals, the processing unit can obtain the M*N infrared sensors in turn The detected sensing signals, and output the driving signals required by the M*N light-emitting diodes in turn and correctly and in turn, make the processing unit and the infrared sensors and the light-emitting Between the diodes, only 2*M*N three-state output latches and N+2*M signals (such as 19) are needed. Compared with the conventional technology, M*N*2 (such as 84) or M+N+M*N (such as 55), which greatly reduces the amount of signal books or pins required by the processing unit, so it can indeed achieve the purpose of the invention.

However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited by this, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the patent specification still belong to Within the scope of the patent for the present invention.

100: storage box 1: processing unit 2: logic unit 20[X,Y]: The first three-state output latch 21[X,Y]: The second three-state output latch 22: D-type latch 221: Reverse Gate 222: and gate 223: and gate 224: reverse or gate 225: reverse or gate 23: The first inverter 24: first buffer 25: second buffer 26: enabling end 27: Latch end 28: data side 29: output 3: Light-emitting diode 3[X,Y]: Light-emitting diode 4: infrared sensor 4[X,Y]: infrared sensor 5: Box body 9: Storage space DATA[Y]: Input and output signal LED_LE[X]: The first control signal IR_OE[X]: The second control signal LED_EN[X,Y]: drive signal IR_OUT[X,Y]: sense signal C1~C4: OK R1~R4: column E: Latch end D: Data terminal Q: output S1~S3: steps S21~S25: steps S31~S35: steps

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: Figure 1 is a schematic diagram illustrating the control method of the second conventional technology; Figure 2 is a schematic diagram illustrating an embodiment of the storage box of the present invention; Figure 3 is a block diagram to assist Figure 1 to illustrate the embodiment; Figure 4 is a schematic diagram, assisting Figure 1 to illustrate the electrical connection of the embodiment; Figure 5 is a schematic diagram assisting Figure 1 to illustrate the electrical connection relationship of this embodiment; Figure 6 is a circuit diagram illustrating a part of the circuit of a logic unit of this embodiment; Figure 7 is a circuit diagram illustrating a three-state output latch of this embodiment; Figure 8 is a circuit diagram illustrating a D-type latch of this embodiment; and Fig. 9 is a flowchart illustrating the operation process of this embodiment.

100: storage box

1: processing unit

2: logic unit

3: Light-emitting diode

4: infrared sensor

5: Box body

9: Storage space

Claims (9)

A storage box, including: A box, including M*N storage spaces arranged in a matrix, M and N are both positive integers; M*N infrared sensors are arranged in the box body and respectively detect whether the storage spaces contain an object, and generate M*N sensing signals; M*N light-emitting diodes are arranged in the box, and receive M*N drive signals respectively, so as to be controlled to determine correspondingly to emit light or not to emit light in the storage spaces; and A logic unit electrically connected to the infrared sensors and the light emitting diodes, and includes M*N*2 three-state output latches, where the M*N three-state output latches are defined as The first three-state output latch, and the other M*N three-state output latches are defined as the second three-state output latches. The first three-state output latches receive and according to the M th A control signal and N input and output signals, which in turn generate the M*N drive signals in sequence, and the second three-state output latches receive and sense the M*N drive signals according to the M second control signals. N of the signals are output to the N input and output signals in turn; and A processing unit, which is electrically connected to the logic unit, and generates the M first control signals and the M second control signals, and obtains the M*N sequentially by the N input and output signals at different time points According to the M*N sensing signals, the N input and output signals are used at different time points to generate the M*N driving signals in turn. The storage box according to claim 1, wherein the processing unit uses the M first control signals to make the M*N first three-state output latches keep outputting the logic value of the previous state, and borrow The logic value of one of the M second control signals is equal to a first logic value in turn, so that the M*N second three-state output latches are obtained in turn by the N input and output signals N of the M*N sensing signals output by the device, and then obtaining the logic value of the M*N sensing signals. The storage box according to claim 2, wherein the processing unit determines the logical values of the M*N driving signals according to the logical values of the M*N sensing signals, and uses the M second control signals , So that the output of the M*N second three-state output latch is in a high impedance state, and the logic value of one of the M first control signals is sequentially equal to a second logic value in turn, In order to output N of the logic values determined by the M*N drive signals to N of the M*N first three-state output latches in turn by the N input/output signals, and then Generate the M*N drive signals. The storage box according to claim 3, wherein each of the three-state output latches includes a consistent energy end, a latch end, a data end, and an output end, and the M*N first three-state outputs The latches are defined and classified as belonging to the same row or the same column according to the matrix arrangement of the M*N storage spaces, The enable terminals of the M*N first three-state output latches receive the first logic value, and the latch terminals of the N first three-state output latches in the same column receive the M The same one of the first control signals, the data terminals of the N first three-state output latches in the same row receive the N input and output signals, and the M*N first three-state output latches The output terminals output the M*N driving signals. The storage box according to claim 4, wherein the M*N second three-state output latches are respectively defined and classified as belonging to the same row or the same column according to the matrix arrangement of the M*N storage spaces, The enabling ends of the N second three-state output latches in the same column receive the same one of the M second control signals, and the pins of the M*N second three-state output latches The lock terminal receives the second logic value, the data terminals of the M*N second three-state output latches receive the M*N sensing signals, and the N second three-state output latches in the same row are locked The output terminals of the converter output the N input and output signals. The storage box according to claim 5, wherein the enable terminal, the latch terminal, the data terminal, and the signal received or output from the output terminal of each of the three-state output latches have the following Logical relationship, When the logic value of the signal received by the enable terminal and the latch terminal is equal to the first logic value and the second logic value, respectively, the logic value of the signal output by the output terminal is equal to the signal received by the data terminal Logical value, When the logic value of the signal received by the enable terminal and the latch terminal are both equal to the first logic value, the logic value of the signal output by the output terminal is equal to the logic value maintained in the previous state, When the logic value of the signal received by the enable terminal is equal to the second logic value, the output of the output terminal is in the high impedance state. The storage box according to claim 6, wherein each of the three-state output latches further includes: A first inverter includes an input terminal electrically connected to the enable terminal of the three-state output latch, and an output terminal; A first buffer, including an input terminal electrically connected to the latch end of the three-state output latch, and an output terminal; A D-type latch including a latch terminal electrically connected to the output terminal of the first buffer, a data terminal electrically connected to the data terminal of the three-state output latch, and an output terminal; and A second buffer includes an input terminal electrically connected to the output terminal of the D-type latch, a control terminal electrically connected to the output terminal of the first inverter, and a three-state output latch electrically connected The output terminal of the output terminal, when the logic value of the signal received by the control terminal is equal to the first logic value, the output of the output terminal is in the high impedance state, when the logic value of the signal received by the control terminal is equal to the first logic value In the case of two logic values, the logic value of the signal output by the output terminal is equal to the logic value of the signal received by the input terminal. The storage box according to claim 7, wherein the D-type latch of each three-state output latch further includes: A reverse gate, including an input terminal electrically connected to the data terminal of the D-type latch, and an output terminal; A first gate includes a first input terminal electrically connected to the output terminal of the reverse gate, a second input terminal electrically connected to the latch terminal of the D-type latch, and an output terminal; A second gate includes a first input terminal electrically connected to the latch end of the D-type latch, a second input terminal electrically connected to the data terminal of the D-type latch, and an output terminal; A first reverse OR gate, including a first input terminal electrically connected to the output terminal of the first and gate, a second input terminal, and an output terminal electrically connected to the output terminal of the D-type latch; and A second inverter gate includes a first input terminal electrically connected to the output terminal of the first inverter gate, a second input terminal electrically connected to the output terminal of the second inverter gate, and a second input terminal electrically connected to the first inverter gate. The output terminal of the second input terminal of the inverted OR gate. The storage box according to claim 1, wherein the processing unit uses the M first control signals to make the M*N first three-state output latches keep outputting the logic value of the previous state, and borrow The logic value of one of the M second control signals is equal to a first logic value to obtain the M*N output by the M*N second three-state output latches by the N input/output signals *N of the N sensing signals, and then obtaining the logic value of N of the M*N sensing signals, The processing unit then uses the M second control signals to make the output of the M*N second three-state output latches a high impedance state, and uses one of the M first control signals The logic value of is equal to a second logic value, so that N of the logic values determined by the M*N driving signals are output to the M*N first three-state output latches by the N input/output signals N of the M*N drive signals generate logic values of N of the M*N drive signals, The processing unit sequentially obtains the logic values of the other N of the M*N sensing signals by the other one of the M second control signals, and then uses the M first control signals The other one is to generate the logic values of the other N of the M*N driving signals, so as to obtain the M*N sensing signals and generate the M*N driving signals.

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