US6489937B1 - LED matrix control system with Field Programmable Gate Arrays - Google Patents
LED matrix control system with Field Programmable Gate Arrays Download PDFInfo
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- US6489937B1 US6489937B1 US09/439,399 US43939999A US6489937B1 US 6489937 B1 US6489937 B1 US 6489937B1 US 43939999 A US43939999 A US 43939999A US 6489937 B1 US6489937 B1 US 6489937B1
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- fpga
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
Definitions
- the present invention relates to the field of controlling the individual LED's in a matrix of LED's, and in particular to a system using two field programmable gate arrays (FPGA).
- FPGA field programmable gate arrays
- an LED matrix of 36 LED's can be arranged in two rows with 18 columns, three rows with 12 columns, four rows with nine columns, and six rows with six columns. Therefore the components between the CPU and the LED matrix changes for each LED matrix having a different number of LED's, or having a different arrangement of LED's.
- the present invention accomplishes this object by using two FPGA's, where one FPGA controls a first set of LED's and the second FPGA controls a second set of LED's.
- the first set and the second set of LED's are preferably mutually exclusive.
- the first FPGA controls all of the column lines of an LED matrix, and controls a sub set of the row lines of the LED matrix.
- the second FPGA also controls all of the column lines and controls another sub set of the row lines.
- Each FPGA receives the same information from the CPU.
- Each FPGA also has a config line.
- the config line of one FPGA is connected to a logical zero, such as ground, and the config line of the other FPGA is connected to a logical one, such as a power supply voltage.
- Each FPGA only enables or energizes one row at a time. The rows are energized on and off so quickly, that the human persistence of vision causes the appearance of the energized LED's to always appear lit.
- Each FPGA includes a row control means which controls which rows are energized.
- the row control means in each FPGA is based on the same clock signal, preferably the clock signal coming from the CPU. From this clock signal, row signals are generated. Each row signal separately indicates which row is to be energized.
- Each FPGA generates a separate row signal for each of the rows in the LED matrix, regardless of whether the respective FPGA will control that row.
- Each of the row signals in each FPGA also generates an indication of when the respective row is to be enabled, regardless of whether the respective FPGA controls that row.
- Each FPGA also includes a time logic block which receives the row signals and generates row subset signals. The time logic block also receives the config signal.
- the time logic block chooses which of the row signals to include in the row subset signals. As an example, if the config signal is at a logical one level, the time logic block includes only the row signals for the first set of rows in the row subset signals. If the config signal is at a logical zero level, the time logic block includes only the row signals for the second set of rows in the row subset signals.
- Each FPGA also includes an LED register array and generates individual LED signals for each of the LED's in the LED matrix based on the information received from the CPU.
- Each LED register array receives the same signals from the CPU.
- Each LED register array also receives the config signal. Based on the config signal, each LED register array generates the individual LED signals for either the first or second set of rows in the LED matrix.
- the row and column lines for that one LED must be enable.
- the FPGA enables the respective row.
- the FPGA enables the column line for that one individual LED.
- all of the LED's and in an LED matrix can be individually and separately controlled by two or more FPGA's which have identical programming, and can be programmed in parallel to reduce programming time.
- the size of the FPGAs can be smaller and it is often more cost-effective to use two smaller FPGA's then one large FPGA.
- the present invention is therefore able to provide an LED matrix control system which is simple in design, reliable during operation and economical to manufacture.
- FIG. 1 is a schematic diagram of the LED matrix control system
- FIG. 2 is a schematic diagram and of one FPGA
- FIG. 3 is a logic diagram for a nor gate
- FIG. 4 is a schematic representation of the preferred LED matrix.
- a matrix LED display, or LED matrix 1 is connected to first and second FPGAs 3 A and 3 B.
- a preferred type of FPGA is model EPF6016TC144-3, from ALTERA Corp. and a preferred type of LED matrix is model SEL-7588M, Selectronic Ltd., from LITEON ELECTRONIC CO., Ltd.
- the FPGAs 3 are connected to CPU 5 , preferably Motorola MPC 860.
- the FPGA's 3 have control outputs connected to the LED matrix 1 through a plurality of column lines 7 and row lines 9 A and 9 B.
- FPGA 3 A is connected to LED matrix 1 with row lines 9 A
- FPGA 3 B is connected to LED matrix 1 with row lines 9 B.
- the FPGAs 3 are both connected to all of the column lines 7 .
- the FPGAs 3 are connected to the CPU 5 by an address line 11 , data line 13 and clock line 15 . As can be seen from FIG. 1, the FPGAs 3 share the same address line 11 , data line 13 and clock line 15 .
- Programming of the FPGAs 3 can be done by the CPU 5 , or an optional memory device such as an EPROM, not shown.
- the programming of the FPGAs 3 can be through the address line 11 , data lines 13 and clock line 15 , or the programming can be performed through a separate lines not shown in the figures.
- Each FPGA 3 is programmed with the same programming code and both of the FPGAs 3 can be programmed simultaneously from the same source.
- Each FPGA 3 also includes a separate config input 17 A or 17 B.
- Config input 17 A is preferably tied by hardware to a logical one, usually a power supply voltage.
- Config input 17 B is preferably tied by hardware to a logical zero, usually ground.
- the program code in the FPGAs 3 read the signal on the config input 17 and use this signal to determine which rows 9 and respective LEDs, the FPGA 3 is to control.
- FIG. 4 individually shows the placement of the LEDs in the LED matrix 1 .
- the LED matrix 1 includes 36 bi-color LEDs, where each bi-color LED can display yellow or green light. Therefore the LED matrix one can be considered to have 72 different LEDs or lights.
- the terms starting with the letter A are controlled by FPGA 3 A, and the terms starting with the letter B are controlled by FPGA 3 B.
- the number following the letter indicates the number of the bi-color LED and the two letters after the number indicates if the term represents the green or yellow portion of the bi-color LED.
- Row 1 therefore includes the bi-color LEDs 13 — 18 of the first set and they are controlled by FPGA 3 A.
- row 2 includes bi-color LEDs 7 — 12 of the first set and they are also controlled by FPGA 3 A.
- Row 4 includes bi-color LEDs 13 - 18 of the second set and they are controlled by FPGA 3 B.
- each FPGA 3 includes an LED register array 19 which receives the address line 11 , data line 13 , clock line 15 and config line 17 .
- the LED register array 19 reads all of these lines and generates individual LED signals 21 .
- Each individual LED signal 21 indicates the state, on or off, of an individual LED.
- the individual LEDs themselves are divided into the two sets, preferably with one set corresponding to the first set of rows 9 , and the other set of LEDs corresponding to another set of rows 9 .
- the LED register array 19 generates the individual LED signals 21 for the specific set of LEDs based on the value of the signal on the config input 17 . In FIG. 2, the individual LED signals 21 are divided into LED signals for the green portion of the bi-colored LEDs and the yellow portion of the bi-colored LEDs.
- Each FPGA 3 controls one of the subset of row lines 9 by a row control means.
- FPGA 3 A controls row lines 9 A, which includes rows 1 - 3 .
- the other FPGA 3 B controls row lines 9 B with rows 4 - 6 .
- each FPGA 3 generates row signals 23 for all of the rows 9 .
- the row signals 23 are preferably enabled separately and sequentially. However the row signals 23 can be enabled in any order desired.
- the row signals 23 are preferably generated with the clock signal 15 and a self clearing shift register 25 .
- a 10 bit counter 27 can be placed between the clock signal 15 and the self clearing shift register 25 in order to reduce the speed of the clock.
- a carry signal from counter 27 is connected to the shift right input 29 .
- the output of the self clearing register 25 are the row signals 23 . All but one of the row signals 23 are separately combined in a nor gate 33 .
- the output of the nor gate 33 is connected to the data input 31 of the shift register 25 .
- FIG. 3 shows how the combination of the self clearing shift register 25 and the nor gate 33 combine to enable only one row signal 23 at a time. When the FPGA is started for the first time, all the bits in the register 23 are zero, and therefore the output of the nor gate 33 is one.
- This value of one is then entered into the data input 31 of the shift register 25 , and enables row signal T 1 .
- one of the inputs to the nor gate 33 is a logical one, and therefore the output of the nor gate 33 is zero.
- This zero is then placed into the shift register 25 and all the previous values in the shift register are moved one bit with the result as shown in line three of FIG. 3 .
- Each row line 23 is thus separately enabled in a sequential matter.
- each FPGA 3 does not enable or control all of the row lines 9 . Therefore the row signals 23 are delivered to a time logic block 35 .
- the time logic block 35 also receives the config signal 17 , and uses the config signal 17 with the row signals 23 to generate row subset signals 37 which only control the row lines 9 which the respective FPGA 3 is supposed to control.
- the logic for the row sub set signals is shown below:
- T 2 _ 5 (T 2 and Config) or (T 5 and NOT(Config))
- T 3 _ 6 ⁇ (T 3 and Config) or (T 6 and NOT(Config)).
- the row subset signals 37 are only enabled when the row to be enabled is a row controlled by the respective FPGA 3 .
- the row subset signals 37 are then fed to row enabling units 39 which enable or energize a row line 9 when the corresponding row subset signal 37 is energized.
- a row logic block 41 is placed between each corresponding row subset signal 37 and its corresponding row enabling unit 39 . The logic of each row logic block 41 is shown below.
- ROW 1 _ 4 T 1 _ 4 and (GR 13 or GR 14 or GR 15 or GR 16 or GR 17 or GR 18 or YL 13 or YL 14 or YL 15 or YL 16 or YL 17 or YL 18 )
- ROW 2 _ 5 T 2 _ 5 and (GR 7 or GR 8 or GR 9 or GR 10 or GR 11 or GR 12 or YL 7 or YL 8 or YL 9 or YL 10 or YL 11 or YL 12 )
- ROW 3 _ 6 T 3 _ 6 and (GR 1 or GR 2 or GR 3 or GR 4 or GR 5 or GR 6 or YL 1 or YL 2 or YL 3 or YL 4 or YL 5 or YL 6 ).
- row logic blocks 41 prevents a row from being energized or enabled when none of the LEDs in that row are to be enabled.
- the nor gate 33 , shift register 25 , time logic block 35 row logic blocks 41 and row enabling units 39 form the preferred embodiment of the row control means. However other embodiments are possible and within the scope of the invention.
- the enabling of the column lines 7 is performed by column control means which includes all the structure generating the row subset signals 37 , and column logic blocks 41 .
- Column logic blocks 41 receive both the individual LED signals 21 and the row subset signals 37 .
- each column logic block 41 receives all of the row subset signals 37 and the individual LED signals 21 for the LEDs in the respective column.
- the logic in each respective column logic block 41 determines if the corresponding column in the LED matrix I should be enabled.
- the logic for the column logic blocks in the preferred embodiment is as follows:
- COL 1 ((T 3 _ 6 and GR 1 ) or (T 2 _ 5 and GR 7 ) or (T 1 _ 4 and GR 13 ))
- COL 2 ((T 3 _ 6 and YL 1 ) or (T 2 _ 5 and YL 7 ) or (T 1 _ 4 and YL 13 ))
- COL 3 ((T 3 _ 6 and GR 2 ) or (T 2 _ 5 and GR 8 ) or (T 1 _ 4 and GR 14 ))
- COL 4 ((T 3 _ 6 and YL 2 ) or (T 2 _ 5 and YL 8 ) or (T 1 _ 4 and YL 14 ))
- COL 5 ((T 3 _ 6 and GR 3 ) or (T 2 _ 5 and GR 9 ) or (T 1 _ 4 and GR 15 ))
- COL 6 ((T 3 _ 6 and YL 3 ) or (T 2 _ 5 and YL 9 ) or (T 1 _ 4 and YL 15 ))
- COL 7 ((T 3 _ 6 and GR 4 ) or (T 2 _ 5 and GR 10 ) or (T 1 _ 4 and GR 16 ))
- COL 8 ((T 3 _ 6 and YL 4 ) or (T 2 _ 5 and YL 10 ) or (T 1 _ 4 and YL 16 ))
- COL 9 ((T 3 _ 6 and GR 5 ) or (T 2 _ 5 and GR 11 ) or (T 1 _ 4 and GR 17 ))
- COL 10 ((T 3 _ 6 and YL 5 ) or (T 2 _ 5 and YL 11 ) or (T 1 _ 4 and YL 17 ))
- COL 11 ((T 3 _ 6 and GR 6 ) or (T 2 _ 5 and GR 12 ) or (T 1 _ 4 and GR 18 ))
- COL 12 ((T 3 _ 6 and YL 6 ) or (T 2 _ 5 and YL 12 ) or (T 1 _ 4 and YL 18 )).
- Each column line 7 is therefore only enabled if an individual LED signal 21 is enabled for one of the LEDs in the respective column, and if the row line 9 A for that LED is enabled.
- a plurality of FPGA's 3 can be used to control a plurality of LEDs in an LED matrix, where the program code for the plurality of FPGA's 3 is identical for all of the FPGAs 3 . Also, all of the FPGAs 3 can be programmed simultaneously.
- the internal design of the FPGA 3 including alternate expressions of the logic can be changed, and still fall within the scope of the invention of having the program code for the FPGAs be identical and simultaneously programmable.
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US09/439,399 US6489937B1 (en) | 1999-11-15 | 1999-11-15 | LED matrix control system with Field Programmable Gate Arrays |
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US09/439,399 US6489937B1 (en) | 1999-11-15 | 1999-11-15 | LED matrix control system with Field Programmable Gate Arrays |
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Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
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US6762689B2 (en) * | 2001-11-16 | 2004-07-13 | Michel L. Dechape | Universal traffic signal display system and apparatus, and method of using the same |
US20050207152A1 (en) * | 2004-03-18 | 2005-09-22 | Lighting Sciences, Inc. | Lighting element using electronically activated light emitting elements and method of making same |
US20050207159A1 (en) * | 2004-03-18 | 2005-09-22 | Lighting Science Group Corporation | System and method for providing multi-functional lighting using high-efficiency lighting elements in an environment |
US20050237005A1 (en) * | 2004-04-23 | 2005-10-27 | Lighting Science Group Corporation | Electronic light generating element light bulb |
US20050242734A1 (en) * | 2004-04-30 | 2005-11-03 | Lighting Sciences, Inc. | Light bulb having wide angle light dispersion and method of making same |
US20050243552A1 (en) * | 2004-04-30 | 2005-11-03 | Lighting Science Group Corporation | Light bulb having surfaces for reflecting light produced by electronic light generating sources |
US20070044355A1 (en) * | 2005-09-01 | 2007-03-01 | Shofner Robert D | High-visibility airborne color LED display sign |
US20080114476A1 (en) * | 2006-11-09 | 2008-05-15 | Kay Jason E | Apparatus and method for allowing display modules to communicate information about themselves to other display modules in the same display panel |
CN101764981A (en) * | 2008-12-23 | 2010-06-30 | 康佳集团股份有限公司 | High-resolution video image controller for embedded LED display screen |
CN101770089B (en) * | 2008-12-26 | 2012-03-07 | 京东方科技集团股份有限公司 | Liquid crystal display module tester |
CN102446476A (en) * | 2011-11-02 | 2012-05-09 | 苏州华兴源创电子科技有限公司 | Small and medium-sized liquid crystal module checking machine |
US8901831B2 (en) | 2012-05-07 | 2014-12-02 | Lighting Science Group Corporation | Constant current pulse-width modulation lighting system and associated methods |
CN104299564A (en) * | 2014-09-11 | 2015-01-21 | 苏州合欣美电子科技有限公司 | LED display screen fault self-recovery control system |
US20150047186A1 (en) * | 2013-08-16 | 2015-02-19 | Lighting Science Group Corporation | Method of assembling a lighting device with flexible circuits having light-emitting diodes positioned thereon |
US9557015B2 (en) | 2013-08-16 | 2017-01-31 | Lighting Science Group Corporation | Lighting device with flexible circuits having light-emitting diodes positioned thereupon and associated methods |
US9894733B1 (en) | 2016-12-22 | 2018-02-13 | Nxp B.V. | Standalone light emitting diode (LED) controller |
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Cited By (29)
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US6762689B2 (en) * | 2001-11-16 | 2004-07-13 | Michel L. Dechape | Universal traffic signal display system and apparatus, and method of using the same |
US7086756B2 (en) | 2004-03-18 | 2006-08-08 | Lighting Science Group Corporation | Lighting element using electronically activated light emitting elements and method of making same |
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US20050207159A1 (en) * | 2004-03-18 | 2005-09-22 | Lighting Science Group Corporation | System and method for providing multi-functional lighting using high-efficiency lighting elements in an environment |
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US7367692B2 (en) | 2004-04-30 | 2008-05-06 | Lighting Science Group Corporation | Light bulb having surfaces for reflecting light produced by electronic light generating sources |
US20050242734A1 (en) * | 2004-04-30 | 2005-11-03 | Lighting Sciences, Inc. | Light bulb having wide angle light dispersion and method of making same |
US20070044355A1 (en) * | 2005-09-01 | 2007-03-01 | Shofner Robert D | High-visibility airborne color LED display sign |
US20080114476A1 (en) * | 2006-11-09 | 2008-05-15 | Kay Jason E | Apparatus and method for allowing display modules to communicate information about themselves to other display modules in the same display panel |
US7948450B2 (en) | 2006-11-09 | 2011-05-24 | D3 Led, Llc | Apparatus and method for allowing display modules to communicate information about themselves to other display modules in the same display panel |
CN101764981A (en) * | 2008-12-23 | 2010-06-30 | 康佳集团股份有限公司 | High-resolution video image controller for embedded LED display screen |
CN101764981B (en) * | 2008-12-23 | 2013-10-30 | 康佳集团股份有限公司 | High-resolution video image controller for embedded LED display screen |
CN101770089B (en) * | 2008-12-26 | 2012-03-07 | 京东方科技集团股份有限公司 | Liquid crystal display module tester |
CN102446476A (en) * | 2011-11-02 | 2012-05-09 | 苏州华兴源创电子科技有限公司 | Small and medium-sized liquid crystal module checking machine |
US8901831B2 (en) | 2012-05-07 | 2014-12-02 | Lighting Science Group Corporation | Constant current pulse-width modulation lighting system and associated methods |
US20150047186A1 (en) * | 2013-08-16 | 2015-02-19 | Lighting Science Group Corporation | Method of assembling a lighting device with flexible circuits having light-emitting diodes positioned thereon |
US9464788B2 (en) * | 2013-08-16 | 2016-10-11 | Lighting Science Group Corporation | Method of assembling a lighting device with flexible circuits having light-emitting diodes positioned thereon |
US9557015B2 (en) | 2013-08-16 | 2017-01-31 | Lighting Science Group Corporation | Lighting device with flexible circuits having light-emitting diodes positioned thereupon and associated methods |
CN104299564A (en) * | 2014-09-11 | 2015-01-21 | 苏州合欣美电子科技有限公司 | LED display screen fault self-recovery control system |
US9894733B1 (en) | 2016-12-22 | 2018-02-13 | Nxp B.V. | Standalone light emitting diode (LED) controller |
WO2021151112A1 (en) * | 2020-01-21 | 2021-07-29 | Brightlogic, Inc. | Light emitting diode package and electronic display |
US11438991B2 (en) | 2020-01-21 | 2022-09-06 | Brightlogic, Inc. | Light emitting diode package and electronic display |
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