TWI679975B - Storage Box - Google Patents

Abstract

A storage box includes a box body, M * N infrared sensors and light emitting diodes, a logic unit and a processing unit. The logic unit includes a plurality of three-state output latches, of which M * N are based on M first control signals and N input / output signals to generate M * N driving signals to control the light emitting diodes to emit light. In addition, M * N three-state output latches output N of the M * N sensing signals of the infrared sensors in turn to the N input / output signals according to the M second control signals. The processing unit generates the first control signals and the second control signals, and also obtains the M * N sensing signals from the N input / output signals at different points in time, and then according to the M * N sensing signals The measurement signals generate the M * N driving signals from the N input / output signals at different time points.

Description

Storage Box

The present invention relates to a storage box, and particularly to a medicine storage box provided with a light emitting diode to display a storage state.

The conventional medicine storage box includes a plurality of storage spaces for storing medicines, a plurality of infrared sensors that respectively sense whether the storage spaces contain medicines, and a plurality of corresponding corresponding storage spaces to display whether the medicines are contained. Light-emitting diode and a processing unit. The processing unit is electrically connected to the infrared sensors to receive a plurality of sensing signals, and is also electrically connected to the light emitting diodes, and generates a plurality of driving signals according to the sensing signals to control the light emission respectively. The diodes respectively emit or not emit light in the storage spaces, so as to correspondingly display whether each of the storage spaces contains a medicine.

For example, the number of such storage spaces is 6 * 7 equals 42 and the storage spaces are arranged in a matrix to correspond to medications taken up to six times a day, seven days a week. When medicines are contained in the 42 storage spaces, the processing unit generates the 42 driving signals according to the 42 sensing signals so that the 42 light-emitting diodes emit light. After the medicine in the first column and the first row is taken, similarly, the processing unit controls the corresponding light emitting diode in the storage space of the first column and the first row to not emit light, and controls the remaining 41 light emitting diodes. The body keeps emitting light in the other 41 storage spaces.

The first conventional processing unit uses M * N (ie, 42) sensing signals and M * N (ie, 42) driving signals. Therefore, the processing unit requires a total of 84 pins. When the number of pins of the processing unit is less than 84, it is necessary to set multiple processing units, which is not economical. Alternatively, the second conventional processing unit uses a matrix control method to generate the driving signals, so the number of the driving signals can be reduced to M + N (ie, 13), so that the total number of required pins is reduced. To M + N + M * N (ie 55). However, because the processing unit of the second type adopts a matrix control method, the light emission of the light-emitting diodes is also limited.

Referring to FIG. 1, FIG. 1 uses eight control signals in four rows and four columns and corresponding sixteen light-emitting diodes as examples to illustrate the problem of the control method of the second conventional technique. When the light-emitting diodes located in the R2 column and the C2 row are to be controlled to emit light, the two control signals in the R2 column and the C2 row are indicated by a solid line to be changed by a logic value such as logic 1. Similarly, when the light-emitting diodes located in the R3 column and the C3 row are to be controlled to emit light, the two control signals in the R3 column and the C3 row are indicated by solid lines. However, when two light emitting diodes in column R2, column C2, and column R3, column C3 are to be controlled to emit light at the same time, it is necessary to control four in column R2, row C2, column R3, and row C3. The logic value of the control signal is, for example, logic 1 (represented by a solid line), but the other two light-emitting diodes in column R2, column C3, and column R3 in column C2 also emit light, causing incorrect display. In other words, the use of a matrix-based control method using a processing unit will cause the light emission of these light-emitting diodes to be limited by the circuit, and only a single or a single row of light-emitting diodes can be displayed at a time, but not simultaneously and correctly. Controls multiple coupled light emitting diodes. Therefore, it is a problem to be solved to provide a medicine storage box using a processing unit with a smaller number of feet and reduce the cost.

Therefore, an object of the present invention is to provide a storage box using a processing unit with a smaller number of input / output signals or pins.

Therefore, the storage box of the present invention includes a box body, M * N infrared sensors, M * N light emitting diodes, a logic unit, and a processing unit. M and N are both positive integers.

The box body includes M * N storage spaces arranged in a matrix. The M * N infrared sensors are arranged on the box body, and respectively detect whether or not an object is accommodated in the storage spaces, thereby generating M * N sensing signals. The M * N light-emitting diodes are arranged in the box body, and receive M * N driving signals respectively, so as to be controlled and decided to respectively emit light or not emit light in the storage spaces.

The logic unit is electrically connected to the infrared sensors and the light emitting diodes, and includes M * N * 2 three-state output latches. The M * N three-state output latches are defined as a first three-state output latch, and the other M * N three-state output latches are defined as a second three-state output latch. The first three-state output latches receive and sequentially generate the M * N driving signals according to the M first control signals and the N input / output signals. The second three-state output latches receive and sequentially output N of the M * N sensing signals to the N input / output signals in turn according to the M second control signals.

The processing unit is electrically connected to the logic unit, and generates the M first control signals and the M second control signals, and obtains the M * N numbers in turn through the N input and output signals at different time points in turn. According to the sensing signals, the M * N driving signals are sequentially generated in turn based on the M * N sensing signals at different time points through the N input / output signals.

In some implementation forms, the processing unit uses the M first control signals to make the M * N first tri-state output latches output a logic value of a previous state, and uses the M The logical value of one of the second control signals is sequentially equal to a first logical value in order to obtain the output of the M * N second tri-state output latches in turn by the N input and output signals in turn. N of the M * N sensing signals are obtained, thereby obtaining a logic value of the M * N sensing signals.

In some embodiments, the processing unit determines the logic values of the M * N driving signals according to the logic values of the M * N sensing signals, and makes the The output of the M * N second tri-state output latches is in a high impedance state, and the logical value of one of the M first control signals is sequentially equal to a second logical value in turn, so that The N input and output signals take turns sequentially outputting N of the logical values determined by the M * N driving signals to N of the M * N first three-state output latches, and then generate the M * N drive signals.

In some implementation forms, each of the three-state output latches includes a uniform energy terminal, a latch terminal, a data terminal, and an output terminal, and the M * N first three-state output latches According to the matrix arrangement of the M * N storage spaces, it is defined and classified as belonging to the same row or the same column. The enabling terminals of the M * N first three-state output latches receive the first logic value, and the latch terminals of the N first three-state output latches in the same column receive the M The same one of the first control signals, the data terminals of the N first three-state output latches in the same column receive the N input and output signals, and the M * N first three-state output latches The output terminals output the M * N driving signals.

In some implementation forms, the M * N second tri-state output latches are respectively defined and classified as belonging to the same row or the same column according to the matrix arrangement of the M * N storage spaces. The enabling ends of the N second tri-state output latches in the same column receive the same one of the M second control signals, and the latches of the M * N second tri-state output latches The lock end receives the second logic value, the data ends of the M * N second tri-state output latches receive the M * N sensing signals, and the N second tri-state output latches of the same column The output terminals of the device output the N input / output signals.

In some implementation forms, the following logical relationship exists between the enable end, the latch end, the data end, and the signals received or output by each of the three-state output latches. .

When the logic values of the signals received by the enable terminal and the latch terminal are equal to the first logic value and the second logic value, respectively, the logic values of the signals output by the output terminal are equal to the signals received by the data terminal Logical value. When the logic value of the signal received by the enable terminal and the latch terminal is equal to the first logic value, the logic value of the signal output by the output terminal is equal to the logic value maintained in the previous state. When the logic value of the signal received by the enable terminal is equal to the second logic value, the output of the output terminal is in the high impedance state.

In some implementation forms, each of the three-state output latches further includes a first inverter, a first buffer, a D-shaped latch, and a second buffer. The first inverter includes an input terminal electrically connected to the enable terminal of the tri-state output latch, and an output terminal. The first buffer includes an input end electrically connected to the latching end of the three-state output latch, and an output end. The D-type latch includes a latch terminal electrically connected to the output terminal of the first buffer, a data terminal electrically connected to the data terminal of the tri-state output latch, and an output terminal.

The second buffer includes an input terminal electrically connected to the output terminal of the D-type latch, a control terminal electrically connected to the output terminal of the first inverter, and an electrical terminal electrically connected to the tri-state output latch. The output of this output. When the logic value of the signal received by the control terminal is equal to the first logic value, the output of the output terminal is in the high impedance state. When the logic value of the signal received by the control terminal is equal to the second logic value, the logic value of the signal output by the output terminal is equal to the logic value of the signal received by the input terminal.

In some implementation forms, the D-type latch of each of the three-state output latches further includes a reverse gate, a first and gate, a second and gate, a first reverse or gate, And a second anti OR gate. The reverse brake includes an input end electrically connected to the data end of the D-type latch and an output end. The first sum gate includes a first input end electrically connected to the output end of the reverse gate, a second input end electrically connected to the latched end of the D-type latch, and an output end. The second sum brake includes a first input end electrically connected to the latching end of the D-type latch, a second input end electrically connected to the data end of the D-type latch, and an output end.

The first OR gate includes a first input terminal electrically connected to the output terminal of the first AND gate, a second input terminal, and an output terminal electrically connected to the output terminal of the D-type latch. The second OR gate includes a first input terminal electrically connected to the output terminal of the first OR gate, a second input terminal electrically connected to the output terminal of the second AND gate, and an electrical connection to the first inverter. An output terminal of the second input terminal of the OR gate.

In other embodiments, the processing unit uses the M first control signals to cause the M * N first three-state output latches to output the logic value of the previous state, and uses the The logic value of one of the M second control signals is equal to a first logic value to obtain the M * N output by the M * N second three-state output latches through the N input / output signals. N of the plurality of sensing signals, thereby obtaining a logical value of N of the M * N sensing signals.

The processing unit further makes the output of the M * N second three-state output latches into a high impedance state by the M second control signals, and uses one of the M first control signals The logic value of is equal to a second logic value to output N of the logic values determined by the M * N driving signals to the M * N first three-state output latches by the N input / output signals. N of them are used to generate logic values of N of the M * N driving signals.

The processing unit sequentially obtains the logic values of the other N of the M * N sensing signals by sequentially using the other of the M second control signals, and then using the M first control signals. The other one generates logic values of the other N of the M * N driving signals, so that the M * N sensing signals can be obtained and the M * N driving signals can be generated.

The effect of the present invention is that the logic values to be driven corresponding to the driving signals are stored by the M * N first three-state output latches, and are stored by the M * N second three-state output latches. The logic values of the corresponding sensing signals and the N input and output signals, the M first control signals, and the M second control signals enable the processing unit to sequentially obtain the M in turn. The driving signals required by the * N infrared sensors and the sequential and correct output of the driving signals required by the M * N light-emitting diodes can be greatly compared with the conventional technology Reduce the number of signals or pins required by the processing unit.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are represented by the same numbers.

Referring to FIG. 2, an embodiment of the storage box 100 of the present invention includes a box body 5, M * N infrared sensors 4, M * N light-emitting diodes (LEDs) 3, a logic unit 2, and a process. Unit 1. The box body 5 includes M * N storage spaces 9 arranged in a matrix, and M and N are both positive integers, and generally greater than 1. In this embodiment, the storage box 100 is a medicine storage box, where M is equal to 6, and N is equal to 7, which indicates a total of 6 columns and 7 rows, and correspondingly indicates that the drug is taken up to six times a day, seven days a week, but not taking This is limited. In addition, it should be added that the configuration of each of the storage spaces 9 is similar. Therefore, for convenience of explanation, FIG. 2 simply indicates a storage space 9, an infrared sensor 4, and a light-emitting diode. Number of 3.

Referring to FIG. 2 and FIG. 3, the M * N infrared sensors 4 are disposed on the box body 5 and respectively detect whether the storage spaces 9 contain an object (such as a medicine), thereby generating M * N senses. Measure signal IR_OUT [X, Y]. In this embodiment, the 6 * 7 infrared sensors 4 are defined as infrared sensors 4 [X, Y], X is equal to 0, 1, ..., M-1 (that is, 0 ~ 5), Y Equal to 0, 1, ..., N-1 (that is, 0 ~ 6), to represent the infrared sensor 4 [X, Y] in the X + 1 column and the Y + 1 row, and correspondingly generate these sensing signals IR_OUT [X, Y]. For example, when the infrared sensor 4 [1,2] in the second column and the third row detects that the corresponding storage space 9 does not contain a medicine, the sensing signal IR_OUT [1 , 2] The logic value is equal to a first logic value (such as logic 0), or when a medicine is contained, the logic value of the sensing signal IR_OUT [1,2] is equal to a second logic value (such as logic 1) ).

The M * N light-emitting diodes 3 are arranged in the box body 5 and respectively receive M * N drive signals LED_EN [X, Y], and are controlled to decide whether to emit light or not to emit light in the storage spaces 9 respectively. . In this embodiment, the 6 * 7 light-emitting diodes 3 are respectively defined as light-emitting diodes 3 [X, Y] to represent the light-emitting diodes 3 in the X + 1 column and the Y + 1 row. [X, Y], and correspondingly receive such driving signals LED_EN [X, Y]. For example, when the logic value of the driving signal LED_EN [2,3] received by the light-emitting diode 3 [2,3] in the third column and the fourth row is equal to the first logic value (such as logic 0) When the light-emitting diode 3 [2,3] does not emit light, or when the logic value of the driving signal LED_EN [2,3] is equal to the second logic value (such as logic 1), it emits light.

Referring to FIG. 3, FIG. 4, and FIG. 5, the logic unit 2 is electrically connected to the infrared sensors 4 [X, Y] and the light emitting diodes 3 [X, Y], and includes M * N * 2 (Ie 84) three-state output latches. The M * N three-state output latches are defined as the first three-state output latches 20 [X, Y] to indicate that the storage space 9 corresponding to the X + 1th column and the Y + 1th row of the storage space 9 Three-state output latches, and the other M * N three-state output latches are defined as the second three-state output latches 21 [X, Y] to indicate that they correspond to the X + 1th column Y + 1 The three-state output latches of the storage space 9 of the row. The first three-state output latches 20 [X, Y] receive and according to M first control signals LED_LE [X] and N input / output signals DATA [Y], and sequentially generate the M * N drives Signal LED_EN [X, Y]. The second three-state output latches 21 [X, Y] receive and rotate N of the M * N sensing signals IR_OUT [X, Y] according to the M second control signals IR_OE [X]. The N input / output signals DATA [Y] are sequentially output.

Referring to FIG. 6 and FIG. 7, for the convenience of description, FIG. 6 only uses the seven first three-state output latches 20 [5, Y corresponding to the storage spaces 9 of the sixth column (ie, X = 5). ] And the seven second three-state output latches 21 [5, Y] as examples for illustration, and the first three-state output latches 20 [0, Y], 20 corresponding to other columns are not shown [1, Y], 20 [2, Y], 20 [3, Y], 20 [4, Y] and these second three-state output latches 21 [0, Y], 21 [1, Y] , 21 [2, Y], 21 [3, Y], 21 [4, Y].

Each of the three-state output latches (that is, the first three-state output latch 20 [X, Y] and the second three-state output latch 21 [X, Y]) includes a uniform energy terminal 26, a The latching terminal 27, a data terminal 28, and an output terminal 29. The enabling terminals 26 of the M * N first three-state output latches 20 [X, Y] are electrically connected to a ground terminal to receive the first logic value (ie, logic 0). The latch terminals 27 of the N first three-state output latches 20 [X, Y] in the same column receive the same one of the M first control signals LED_LE [X], such as the first three The latch terminals 27 of the state output latch 20 [5, Y] respectively receive the first control signals LED_LE [5], the first three-state output latch 20 [4, Y], and the like. The latching ends 27 respectively receive the first control signals LED_LE [4], and the latching ends 27 of the first three-state output latches 20 [3, Y] respectively receive the first control signals LED_LE [ 3]. The latching ends 27 of the first three-state output latches 20 [2, Y] respectively receive the first control signals LED_LE [2], the first three-state output latches 20 The latching ends 27 of [1, Y] respectively receive the first control signals LED_LE [1] and the latching ends 27 of the first three-state output latches 20 [0, Y], respectively. Receive the first control signals LED_LE [0].

The data terminals 28 of the N first three-state output latches 20 [X, Y] in the same column receive the N input / output signals DATA [Y], such as the first three-state output latches 20 The data terminals 28 of [5, Y] respectively receive the N input / output signals DATA [Y], and the data terminals 28 of the first three-state output latches 20 [4, Y] respectively receive the N I / O signals DATA [Y], the data terminals 28 of the first three-state output latches 20 [3, Y] receive the N I / O signals DATA [Y], the first three-states The data terminals 28 of the output latch 20 [2, Y] receive the N input / output signals DATA [Y], the data terminals of the first three-state output latch 20 [1, Y], respectively. 28 respectively receive the N input / output signals DATA [Y] and the data terminals 28 of the first three-state output latches 20 [0, Y] respectively receive the N input / output signals DATA [Y]. The output terminals 29 of the M * N first three-state output latches 20 [X, Y] respectively output the M * N driving signals LED_EN [X, Y].

The enabling terminals 26 of the N second three-state output latches 21 [X, Y] in the same column receive the same one of the M second control signals IR_OE [X], such as the second three The enabling terminals 26 of the state output latch 21 [5, Y] receive the second control signal IR_OE [5], the second three-state output latch 21 [4, Y], The enabling terminals 26 receive the second control signals IR_OE [4], and the enabling terminals 26 of the second three-state output latches 21 [3, Y] respectively receive the second control signals IR_OE [ 3]. The enabling terminals 26 of the second three-state output latches 21 [2, Y] receive the second control signals IR_OE [2], the second three-state output latches 21, respectively. The enabling terminals 26 of [1, Y] respectively receive the second control signals IR_OE [1] and the enabling terminals 26 of the second three-state output latches 21 [0, Y], respectively. Receive the second control signals IR_OE [0].

The latching terminals 27 of the M * N second tri-state output latches 21 [X, Y] are electrically connected to a power terminal to receive the second logic value (ie, logic 1). The data terminals 28 of the M * N second tri-state output latches 21 [X, Y] receive the M * N sensing signals IR_OUT [X, Y], respectively. The output terminals 29 of the N second three-state output latches 21 [X, Y] in the same column respectively output the N input / output signals DATA [Y], such as the second three-state output latches. The output terminals 29 of 21 [5, Y] respectively output the N input / output signals DATA [Y], and the output terminals 29 of the second three-state output latches 21 [4, Y] respectively output the The N input / output signals DATA [Y] and the output terminals 29 of the second three-state output latches 21 [3, Y] output the N input / output signals DATA [Y], the second and third signals, respectively. The output terminals 29 of the state output latch 21 [2, Y] respectively output the N input / output signals DATA [Y] and the outputs of the second three-state output latch 21 [1, Y]. The terminals 29 respectively output the N input / output signals DATA [Y] and the output terminals 29 of the second three-state output latches 21 [0, Y] respectively output the N input / output signals DATA [Y] .

Referring to the following Table 1, each of the three-state output latches (that is, the first three-state output latch 20 [X, Y] and the second three-state output latch 21 [X, Y]) The signals received or output by the enable terminal 26, the latch terminal 27, the data terminal 28, and the output terminal 29 have the following logical relationships.
input signal output signal Enabling end 26 Latching end 27 Data terminal 28 Output 29 0 1 1 1 0 1 0 0 0 0 X Previous state 1 X X Z Form one

That is, when the logic values of the signals received by the enable terminal 26 and the latch terminal 27 are equal to the first logic value (ie, logic 0) and the second logic value (ie, logic 1), the output The logic value of the signal output by the terminal 29 is equal to the logic value of the signal received by the data terminal 28.

When the logic values of the signals received by the enable terminal 26 and the latch terminal 27 are equal to the first logic value (ie, logic 0), the logic value of the signal output by the output terminal 29 is equal to maintaining the previous state Logical value. When the logic value of the signal received by the enable terminal 26 is equal to the second logic value (ie, logic 1), the output of the output terminal 29 is in a high impedance state. It can be known from FIG. 6 and Table 1 that the latch terminals 27 of the M * N second tri-state output latches 21 [X, Y] are maintained at logic 1 (that is, electrically connected to the power terminal). When the logical value of one of the second control signals IR_OE [X] of the enable terminal 26 is equal to logic 0, the input / output signals DATA [Y] of the output terminals 29 and the data terminals The logical values of the corresponding ones of the sensing signals IR_OUT [X, Y] of 28 remain the same, and the logical values of the remaining ones of the second control signals IR_OE [X] remain equal to logical 1 without disturbing These I / O signals DATA [Y].

Referring to FIG. 7 again, in more detail, each of the three-state output latches (ie, the first three-state output latch 20 [X, Y] and the second three-state output latch 21 [X, Y]) also includes a first inverter 23, a first buffer 24, a D-shaped latch 22, and a second buffer 25, that is, each of the three-state output latches is a Transparent D-Type Latch with 3-State Outputs. The first inverter 23 includes an input terminal electrically connected to the enable terminal 26 of the tri-state output latch, and an output terminal. The first buffer 24 includes an input terminal electrically connected to the latching terminal 27 of the tri-state output latch, and an output terminal. The D-type latch 22 includes a latch terminal E electrically connected to the output terminal of the first buffer 24, a data terminal D electrically connected to the data terminal 28 of the tri-state output latch, and an output terminal. Q.

The second buffer 25 includes an input terminal electrically connected to the output terminal Q of the D-type latch 22, a control terminal electrically connected to the output terminal of the first inverter 23, and an electrical connection to the tri-state. An output of the output terminal 29 of the output latch. When the logic value of the signal received by the control terminal of the second buffer 25 is equal to the first logic value (ie, logic 0), the output of the output terminal of the second buffer 25 is in the high impedance state. When the logic value of the signal received by the control terminal of the second buffer 25 is equal to the second logic value (ie, logic 1), the logic value of the signal output by the output terminal of the second buffer 25 is equal to the The logical value of the signal received at the input.

The latch terminal E, the data terminal D, and the signals received or output by the output terminal Q of the D-type latch 22 have the following logical relationships. When the logic values of the signals received by the latch terminal E and the data terminal D are equal to the first logic value (ie, logic 0), the logic value of the signal output by the output terminal Q is equal to that maintained in the previous state. Logical value. When the logic values of the signals received by the latch terminal E and the data terminal D are equal to the first logic value (ie, logic 0) and the second logic value (ie, logic 1), the output from the output terminal Q The logic value of the signal is equal to the logic value held in the previous state.

When the logic values of the signals received by the latch terminal E and the data terminal D are respectively equal to the second logic value (ie, logic 1) and the first logic value (ie, logic 0), the output from the output terminal Q is output. The logic value of the signal is equal to the first logic value (ie, logic 0). When the logic values of the signals received by the latch terminal E and the data terminal D are equal to the second logic value (ie, logic 1), the logic value of the signal output by the output terminal Q is equal to the second logic value ( Ie logic 1).

Referring to FIG. 8, the internal circuit of a D-type latch 22 is illustrated, which further includes an INV gate 221, a first AND gate 222, a second AND gate 223, A first NOR gate 224 and a second NOR gate 225.

The anti-gate 221 includes an input terminal electrically connected to the data terminal D of the D-type latch 22 and an output terminal. The first sum gate 222 includes a first input end electrically connected to the output end of the reverse gate 221, a second input end electrically connected to the latching end E of the D-type latch 22, and an output end. The second sum gate 223 includes a first input terminal electrically connected to the latching end E of the D-type latch 22, a second input terminal electrically connected to the data end D of the D-type latch 22, And an output.

The first OR gate 224 includes a first input terminal electrically connected to the output terminal of the first and gate 222, a second input terminal, and an output electrically connected to the output terminal Q of the D-type latch 22. end. The second OR gate 225 includes a first input terminal electrically connected to the output terminal of the first OR gate 224, a second input terminal electrically connected to the output terminal of the second AND gate 223, and an electrical connection to the The output terminal of the second input terminal of the first OR gate 224.

Referring to FIG. 2 and FIG. 9, FIG. 9 is a flowchart illustrating the control steps of the processing unit 1 by way of example, including steps S1 to S3.

In step S1, execution is started, and then step S2 is performed.

In step S2, sub-process 1 (ie, S2) is performed, including steps S21 to S25, and then step S3 is performed.

In step S21, the variable i = 0 is set, and then step S22 is performed.

In step S22, the processing unit 1 controls the generated second control signal IR_OE [i] = 0 (that is, IR_OE [0] is logic 0, and other IR_OE [1: 5] remain at logic 1), and then executes Step S23.

In step S23, the processing unit 1 stores the logical values of the input / output signals DATA [6: 0], and then executes step S24.

In step S24, the processing unit 1 controls the generated second control signal IR_OE [i] = 1, calculates i = i + 1 (that is, the updated i is equal to 1), and then executes step S25.

In step S25, the processing unit 1 determines whether i is less than 6, and when it is determined that i is less than 6, executes step S22. When it is determined that i is not less than 6, step S3 is performed.

In step S3, sub-process 2 (ie, S3) is performed, including steps S31 to S35, and then step S2 is performed.

In step S31, the variable j = 0 is set, and then step S32 is performed.

In step S32, the processing unit 1 controls the generated first control signal LED_LE [j] = 1 (that is, LED_LE [0] is logic 1 and the other LED_LE [1: 5] remains at logic 0), that is, Say, the logic values of the driving signals LED_EN [j, Y] of the first three-state output latches 20 [j, Y] of the logic unit 2 will be equal to the data terminals The logical value of the input / output signal DATA [Y] of 28, that is, the processing unit 1 simultaneously controls the update of the on / off states of the seven light emitting diodes at a time during each rotation. Then, step S33 is executed.

In step S33, the processing unit 1 writes the logic values stored in step S23 into the input / output signals DATA [6: 0] correspondingly, and then executes step S34.

In step S34, the processing unit 1 controls the generated first control signal LED_LE [j] = 0, calculates j = j + 1 (that is, updated j is equal to 1), and then executes step S35.

In step S35, the processing unit 1 determines whether j is less than 6, and when it is determined that j is less than 6, executes step S32. When it is determined that j is not less than 6, step S2 is performed.

In summary, the processing unit 1 is electrically connected to the logic unit 2 and generates the M first control signals LED_LE [X] and the M second control signals IR_OE [X], and at different points in time, The N input and output signals DATA [Y] sequentially obtain the M * N sensing signals IR_OUT [X, Y] in turn, and then according to the M * N sensing signals IR_OUT [X, Y] at different time points, The N input / output signals DATA [Y] sequentially generate the M * N driving signals LED_EN [X, Y] in turn.

In more detail, the processing unit 1 controls the logic values of the M first control signals LED_LE [X] generated to be equal to the first logic value (ie, logic 0), so that the M * N first tri-state outputs The logic values of the signals received by the enable terminals 26 and the latch terminals 27 of the latch 20 [X, Y] are equal to the first logic value (ie, logic 0), so that the M * N The logic value of the signals output from the output terminals 29 of the first three-state output latch 20 [X, Y] (that is, output to the M * N driving signals LED_EN [X, Y]) remains in the previous state Logical value.

The processing unit also controls the logic value of one of the M second control signals IR_OE [X] (such as IR_OE [5]) to be sequentially equal to the first logic value (ie, logic 0) in turn, and the rest The logic value of the M-1 second control signals (such as IR_OE [4] ~ [0]) is equal to the second logic value (ie, logic 1), so that the M * N second tri-state output latches 21 [X, Y] The logical values of the signals received by the enable terminals 26 and the latch terminals 27 corresponding to the N (such as 21 [5, Y]) are respectively equal to the first logic Value (that is, logic 0) and the second logic value (that is, logic 1), so that the M * N second three-state output latches 21 [X, Y] correspond to one of them (such as 21 [5, The logic value of the signal (ie DATA [Y]) output by the output terminals 29 of Y]) is equal to the logic value of the signal (ie IR_OUT [5, Y]) received by the data terminals 28. That is, at this time, the remaining (M-1) * N second tri-state output latches (such as 21 [4, Y], 21 [3, Y], 21 [2, Y], 21 [ 1, Y], 21 [0, Y]) The logic values of the signals received by the enabling terminals 26 are equal to the second logic value (ie, logic 1), so that (M-1) * N The outputs of the output terminals 29 of the second three-state output latches are in the high-impedance state without affecting the corresponding ones of the M * N second three-state output latches 21 [X, Y] ( Logic values of the input and output signals DATA [Y] respectively output by the output terminals 29 such as 21 [5, Y]).

Therefore, the processing unit 1 can sequentially obtain the M * N outputs of the M * N second three-state output latches 21 [X, Y] by the N input / output signals DATA [Y] in turn. N of the sensing signals IR_OUT [X, Y] (that is, those corresponding to the same column), and then the logical values of the M * N sensing signals IR_OUT [X, Y] are obtained. For example, the processing unit 1 obtains the M * N senses by the M second control signals IR_OE [X] in which X is sequentially equal to 0, 1, ..., M-1 (that is, 0 to 5). The logic value of the signal IR_OUT [X, Y] can obtain whether the M * N storage spaces 9 of the box body contain medicines.

Furthermore, the processing unit 1 determines the logical values of the M * N driving signals LED_EN [X, Y] according to the logical values of the M * N sensing signals IR_OUT [X, Y]. For example, the M * N storage spaces 9 each contain medicines. The logical value of the M * N sensing signals IR_OUT [X, Y] is equal to the second logical value (ie, logic 1), then the processing unit 1 determines the M * The logic values of the N driving signals LED_EN [X, Y] are also equal to the second logic value (ie, logic 1) to drive the M * N light-emitting diodes 3 [X, Y] to emit light to indicate such The storage space 9 contains medicines.

In more detail, the processing unit 1 controls the logic values of the M second control signals IR_OE [X] generated to be equal to the second logic value (ie, logic 1), so that the M * N second tri-state outputs The outputs of the output terminals 29 of the latch 21 [X, Y] are in the high-impedance state without affecting the logic values of the input / output signals DATA [Y].

The processing unit 1 also controls the logic value of one of the M first control signals LED_LE [X] (such as LED_LE [5]) to be sequentially equal to the second logic value (logic 1) in turn, and the rest The logic values of the M-1 first control signals (such as LED_LE [4] ~ [0]) are equal to the first logic value (ie, logic 0), so that the M * N first three-state output latches 20 [X, Y] corresponds to the logic value of the signals received by the N enabled terminals 26 and the latched terminals 27 of the N (eg, 20 [5, Y]) respectively. Value (that is, logic 0) and the second logic value (that is, logic 1), so that the corresponding M * N first three-state output latches 20 [X, Y] correspond to that one (such as 20 [5, The logic value of the signal (ie LED_EN [5, Y]) output by the output terminals 29 of Y]) is equal to the logic value of the signal (ie DATA [Y]) received by the data terminals 28. That is, at this time, the remaining (M-1) * N first three-state output latches (20 [4, Y], 20 [3, Y], 20 [2, Y], 20 [1 , Y], 20 [0, Y]) The logic values of the signals received by the enabling terminals 26 and the latching terminals 27 are equal to the first logic value (ie, logic 0), so that (M -1) The outputs of the output terminals 29 of the * N first three-state output latches are maintained at the logic values of the previous state without being affected by the input and output signals DATA [Y].

Therefore, the processing unit 1 can sequentially output N of the logical values determined by the M * N driving signals LED_EN [X, Y] to the M * by the N input / output signals DATA [Y] in turn. N of the N first three-state output latches 20 [X, Y] generate the M * N driving signals LED_EN [X, Y]. For example, the processing unit 1 sequentially inputs the driving signals LED_EN [X, Y] corresponding to the first to sixth columns through the generated logical values of the N input / output signals DATA [Y], and then The M * N light-emitting diodes 3 [X, Y] are driven to emit light or not to emit light.

In addition, it should be added that, in this embodiment, the processing unit 1 is, for example, a microcontroller, and according to the order of different columns, all the sensing signals IR_OUT [X, Y] are read first. The driving signals LED_EN [X, Y] are sequentially generated. In other embodiments, because the processing time of the first control signal LED_LE [X] and the second control signal IR_OE [X] generated by the processing unit 1 is very short, the processing unit 1 also has According to the order of different columns, the sensing signal IR_OUT [X, Y] in the same column is first read, and then the driving signal LED_EN [X, Y] in the same column is generated, which is not limited to this.

In addition, in this embodiment, there is only one light-emitting diode 3 corresponding to each of the storage spaces 9, and in other embodiments, each of the storage spaces 9 may also correspond to two light-emitting diodes, one of which Light emission indicates that the storage space 9 contains medicine, and another light emission indicates that the storage space 9 does not contain medicine. Alternatively, each of the storage spaces 9 may correspond to three or more light-emitting diodes, and use corresponding three-state output latches to receive corresponding multiple sensing signals and generate corresponding multiple driving signals. .

In summary, the logic values to be driven corresponding to the driving signals are stored by the first three-state output latches, and the corresponding sensing signals are stored by the second three-state output latches. And the N input and output signals, the M first control signals, and the M second control signals can enable the processing unit to sequentially obtain the M * N infrared sensors in turn. The detected sensing signals and the driving signals required for the M * N light-emitting diodes are output correctly and sequentially in turn, which indeed makes the processing unit, the infrared sensors, and the light-emitting diodes Between the diodes, only 2 * M * N three-state output latches and N + 2 * M signals (such as 19) are required, compared with the conventional technology using M * N * 2 (such as 84) or M + N + M * N (for example, 55) can greatly reduce the number of signal books or pin numbers required by the processing unit, so it can indeed achieve the purpose of cost invention.

However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited by this, any simple equivalent changes and modifications made according to the scope of the patent application and the contents of the patent specification of the present invention are still Within the scope of the invention patent.

100‧‧‧Storage Box

1‧‧‧ processing unit

2‧‧‧Logic Unit

20 [X, Y] ‧‧‧The first three-state output latch

21 [X, Y] ‧‧‧Second tri-state output latch

22‧‧‧D type latch

221‧‧‧Reverse

222‧‧‧ and gate

223‧‧‧ and gate

224‧‧‧Anti-OR gate

225‧‧‧Anti-OR gate

23‧‧‧first inverter

24‧‧‧First buffer

25‧‧‧Second buffer

26‧‧‧Enable

27‧‧‧ bolt end

28‧‧‧data terminal

29‧‧‧output

3‧‧‧light-emitting diode

3 [X, Y] ‧‧‧light-emitting diode

4‧‧‧ Infrared sensor

4 [X, Y] ‧‧‧Infrared sensor

5‧‧‧Box

9‧‧‧Storage space

DATA [Y] ‧‧‧I / O signal

LED_LE [X] ‧‧‧First control signal

IR_OE [X] ‧‧‧Second control signal

LED_EN [X, Y] ‧‧‧Drive signal

IR_OUT [X, Y] ‧‧‧Sensed signal

Lines C1 ~ C4‧‧‧‧

R1 ~ R4‧‧‧Column

E‧‧‧ bolt end

D‧‧‧data terminal

Q‧‧‧ output

S1 ~ S‧‧‧ steps

Steps S21 ~ S25‧‧‧‧

S31 ~ S35‧‧‧‧step

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein:
FIG. 1 is a schematic diagram illustrating a control method of a second conventional technique; FIG.
2 is a schematic diagram illustrating an embodiment of the storage box of the present invention;
FIG. 3 is a block diagram illustrating the embodiment with reference to FIG. 1; FIG.
FIG. 4 is a schematic diagram assisting FIG. 1 to explain the electrical connection relationship of the embodiment; FIG.
FIG. 5 is a schematic diagram assisting FIG. 1 to explain the electrical connection relationship of the embodiment; FIG.
6 is a circuit diagram illustrating a part of a circuit of a logic unit of the embodiment;
7 is a circuit diagram illustrating a three-state output latch according to the embodiment;
FIG. 8 is a circuit diagram illustrating an example of a D-shaped latch of the embodiment; and FIG. 9 is a flowchart illustrating an operation flow of the embodiment.

Claims (9)

A storage box containing:
A box body includes M * N storage spaces arranged in a matrix, and M and N are positive integers;
M * N infrared sensors are arranged on the box body, and respectively detect whether or not an object is accommodated in the storage spaces, thereby generating M * N sensing signals;
M * N light-emitting diodes are arranged in the box body and receive M * N driving signals respectively, so as to be controlled to decide whether to emit light or not to emit light in the storage spaces respectively; and a logic unit, which is electrically connected to And other infrared sensors and the light-emitting diodes, and includes M * N * 2 three-state output latches, wherein the M * N three-state output latches are defined as the first three-state output latches And the other M * N three-state output latches are defined as the second three-state output latches. The first three-state output latches receive and are based on M first control signals and N outputs. Input signals, and sequentially generate the M * N driving signals in turn, the second three-state output latches receive and according to the M second control signals, N of the M * N sensing signals in turn Sequence output to the N input and output signals; and a processing unit, electrically connected to the logic unit, and generating the M first control signals and the M second control signals, and using the N The input and output signals take turns sequentially to obtain the M * N sensing signals, and then according to the M * N sensing signals at different time points, the The N input and output signals generate the M * N driving signals in turn. The storage box according to claim 1, wherein the processing unit keeps the M * N first three-state output latches to output the logic value of the previous state by using the M first control signals, and borrows The logical value of one of the M second control signals is sequentially equal to a first logical value in order to sequentially obtain the M * N second tri-state output latches by the N input and output signals in turn. N of the M * N sensing signals outputted by the controller, and further obtaining a logic value of the M * N sensing signals. The storage box according to claim 2, wherein the processing unit determines the logical values of the M * N driving signals according to the logical values of the M * N sensing signals and uses the M second control signals , So that the outputs of the M * N second three-state output latches are in a high-impedance state, and the logical value of one of the M first control signals is sequentially equal to a second logical value in turn, In turn, N of the logical values determined by the M * N driving signals are sequentially output to N of the M * N first three-state output latches by the N I / O signals in turn. The M * N driving signals are generated. The storage box according to claim 3, wherein each of the three-state output latches includes a uniform energy terminal, a latching terminal, a data terminal, and an output terminal, and the M * N first three-state outputs The latches are defined and classified as belonging to the same row or column according to the matrix arrangement of the M * N storage spaces,
The enabling terminals of the M * N first three-state output latches receive the first logic value, and the latch terminals of the N first three-state output latches in the same column receive the M The same one of the first control signals, the data terminals of the N first three-state output latches in the same column receive the N input and output signals, and the M * N first three-state output latches The output terminals output the M * N driving signals. The storage box according to claim 4, wherein the M * N second tri-state output latches are respectively defined and classified as belonging to the same row or the same column according to the matrix arrangement of the M * N storage spaces,
The enabling ends of the N second tri-state output latches in the same column receive the same one of the M second control signals, and the latches of the M * N second tri-state output latches The lock end receives the second logic value, the data ends of the M * N second tri-state output latches receive the M * N sensing signals, and the N second tri-state output latches of the same column The output terminals of the device output the N input / output signals. The storage box according to claim 5, wherein between the enable end, the latch end, the data end, and the signal received or output by each of the three-state output latches, there is the following: Logical relationship,
When the logic values of the signals received by the enable terminal and the latch terminal are equal to the first logic value and the second logic value, respectively, the logic values of the signals output by the output terminal are equal to the signals received by the data terminal Logical value of
When the logic value of the signal received by the enable terminal and the latch terminal is equal to the first logic value, the logic value of the signal output by the output terminal is equal to the logic value maintained in the previous state,
When the logic value of the signal received by the enable terminal is equal to the second logic value, the output of the output terminal is in the high impedance state. The storage box according to claim 6, wherein each of the three-state output latches further comprises:
A first inverter including an input end electrically connected to the enable end of the tri-state output latch and an output end;
A first buffer including an input end electrically connected to the latching end of the tri-state output latch and an output end;
A D-shaped latch including a latch terminal electrically connected to the output terminal of the first buffer, a data terminal electrically connected to the data terminal of the tri-state output latch, and an output terminal; and a second The buffer includes an input terminal electrically connected to the output terminal of the D-type latch, a control terminal electrically connected to the output terminal of the first inverter, and an output electrically connected to the tri-state output latch. When the logic value of the signal received by the control terminal is equal to the first logic value, the output of the output terminal is in the high impedance state. When the logic value of the signal received by the control terminal is equal to the second logic value At this time, the logic value of the signal output by the output terminal is equal to the logic value of the signal received by the input terminal. The storage box according to claim 7, wherein the D-type latch of each of the three-state output latches further comprises:
A reverse brake including an input end electrically connected to the data end of the D-type latch and an output end;
A first sum brake including a first input end electrically connected to the output end of the reverse brake, a second input end electrically connected to the latch end of the D-type latch, and an output end;
A second sum brake including a first input end electrically connected to the latching end of the D-type latch, a second input end electrically connected to the data end of the D-type latch, and an output end;
A first OR gate including a first input terminal electrically connected to the output terminal of the first and gate, a second input terminal, and an output terminal electrically connected to the output terminal of the D-type latch; and The second OR gate includes a first input terminal electrically connected to the output terminal of the first OR gate, a second input terminal electrically connected to the output terminal of the second AND gate, and an electrical connection to the first inverter. An output terminal of the second input terminal of the OR gate. The storage box according to claim 1, wherein the processing unit keeps the M * N first three-state output latches to output the logic value of the previous state by using the M first control signals, and borrows The logic value of one of the M second control signals is equal to a first logic value to obtain the M output by the M * N second tri-state output latches through the N input / output signals. * N of the N sensing signals to obtain the logical value of N of the M * N sensing signals,
The processing unit further makes the output of the M * N second three-state output latches into a high impedance state by the M second control signals, and uses one of the M first control signals The logic value of is equal to a second logic value to output N of the logic values determined by the M * N driving signals to the M * N first three-state output latches by the N input / output signals. N of them, and then generate logic values of N of the M * N driving signals,
The processing unit sequentially obtains the logic values of the other N of the M * N sensing signals by sequentially using the other of the M second control signals, and then using the M first control signals. The other one generates logic values of the other N of the M * N driving signals, so that the M * N sensing signals can be obtained and the M * N driving signals can be generated.