TW202038380A - 用於隔離結構的伸縮襯裡層 - Google Patents
用於隔離結構的伸縮襯裡層 Download PDFInfo
- Publication number
- TW202038380A TW202038380A TW108140249A TW108140249A TW202038380A TW 202038380 A TW202038380 A TW 202038380A TW 108140249 A TW108140249 A TW 108140249A TW 108140249 A TW108140249 A TW 108140249A TW 202038380 A TW202038380 A TW 202038380A
- Authority
- TW
- Taiwan
- Prior art keywords
- processing chamber
- substrate
- processing
- liner layer
- layer
- Prior art date
Links
- 238000002955 isolation Methods 0.000 title abstract description 21
- 238000012545 processing Methods 0.000 claims abstract description 301
- 239000000758 substrate Substances 0.000 claims abstract description 197
- 238000000034 method Methods 0.000 claims abstract description 105
- 239000003989 dielectric material Substances 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000009832 plasma treatment Methods 0.000 claims abstract description 14
- 239000007789 gas Substances 0.000 claims description 85
- 230000008569 process Effects 0.000 claims description 83
- 238000012546 transfer Methods 0.000 claims description 81
- 239000004065 semiconductor Substances 0.000 claims description 30
- 238000005137 deposition process Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- 238000004140 cleaning Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000460 chlorine Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 11
- 229910052801 chlorine Inorganic materials 0.000 claims description 11
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 11
- 239000002243 precursor Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000009969 flowable effect Effects 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000000280 densification Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims 4
- 238000009826 distribution Methods 0.000 description 15
- 239000012212 insulator Substances 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 9
- 239000001307 helium Substances 0.000 description 9
- 229910052734 helium Inorganic materials 0.000 description 9
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 8
- 230000006698 induction Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 6
- 238000001816 cooling Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000012159 carrier gas Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000012530 fluid Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000010926 purge Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000001636 atomic emission spectroscopy Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ZQXCQTAELHSNAT-UHFFFAOYSA-N 1-chloro-3-nitro-5-(trifluoromethyl)benzene Chemical compound [O-][N+](=O)C1=CC(Cl)=CC(C(F)(F)F)=C1 ZQXCQTAELHSNAT-UHFFFAOYSA-N 0.000 description 1
- OTMSDBZUPAUEDD-UHFFFAOYSA-N Ethane Chemical compound CC OTMSDBZUPAUEDD-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005524 ceramic coating Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000012809 cooling fluid Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 231100001261 hazardous Toxicity 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hcl hcl Chemical compound Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/24—Deposition of silicon only
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/28—Deposition of only one other non-metal element
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
- C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/56—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32733—Means for moving the material to be treated
- H01J37/32743—Means for moving the material to be treated for introducing the material into processing chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32733—Means for moving the material to be treated
- H01J37/32788—Means for moving the material to be treated for extracting the material from the process chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32816—Pressure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3211—Nitridation of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
- H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67196—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the transfer chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67201—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the load-lock chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/332—Coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67103—Apparatus for thermal treatment mainly by conduction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Organic Chemistry (AREA)
- Mechanical Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Analytical Chemistry (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Crystallography & Structural Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Cylinder Crankcases Of Internal Combustion Engines (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
- Laminated Bodies (AREA)
- Chemical Vapour Deposition (AREA)
- Element Separation (AREA)
Abstract
通常,本文所述的實例涉及用於在基板上的鰭片之間形成隔離結構(例如,淺溝槽隔離(STI))的方法和處理系統。在一實例中,在基板上形成鰭片。在該等鰭片上和該等鰭片之間共形地形成襯裡層。形成該襯裡層包括在該等鰭片上和該等鰭片之間共形地沉積預襯裡層,以及使用電漿處理使該預襯裡層緻密化以形成該襯裡層。在該襯裡層上形成介電材料。
Description
本文所述的實例通常係關於半導體處理領域,並且更特定言之,係關於縮放用於半導體裝置的隔離結構的襯裡層。
可靠地產生奈米和更小的特徵是超大規模積體(VLSI)和特大規模積體(ULSI)的下一代半導體裝置的關鍵技術挑戰之一。隨著電路技術的極限到來,收縮尺寸的VLSI和ULSI技術對處理能力有附加需求。隨著積體電路元件的尺寸的減小(例如,以奈米尺寸),通常仔細地選擇用於製造元件的材料和製程,以便獲得令人滿意的電效能水準。
積體電路元件的尺寸的減小可能導致在元件之間的間隙越來越小。一些可能適合於以較大尺寸填充類似間隙的製程可能不適合於以較小尺寸填充間隙。因此,需要的是一種能夠在維持積體電路的裝置的令人滿意的效能的同時以較小尺寸形成複雜裝置的製程和處理系統。
更進一步,由於現今VLSI和ULSI結構的複雜性,必須在多個不同處理腔室中處理其上形成該等裝置的基板,該等處理腔室一般經配置為執行圖案化步驟、沉積步驟、蝕刻步驟或熱處理步驟中的至少一者。由於在製程化學物質之間的不相容性、腔室產量的差異、或處理技術,在半導體製造行業中,設備製造商通常只將某些類型的處理技術(例如,沉積腔室)放置在一個處理系統中而將另一種處理技術(例如,蝕刻腔室)放置在另一個處理系統中。出現在常規半導體設備中的處理技術的劃分要求將基板從一個處理系統傳送到另一個處理系統,使得可以在基板上執行各種不同半導體製造製程。在各個處理系統之間執行的傳送製程使基板暴露於各種形式的污染物和顆粒。因此,需要的是一種能夠形成複雜裝置並避免現今影響半導體處理的常見的污染物和顆粒源的製程和處理設備。
本揭示的實施例包括一種用於半導體處理的方法。在基板上形成鰭片。在該等鰭片上和該等鰭片之間共形地形成襯裡層。形成該襯裡層包括在該等鰭片上和該等鰭片之間共形地沉積預襯裡層,以及使用電漿處理使該預襯裡層緻密化以形成該襯裡層。在該襯裡層上形成介電材料。
本揭示內容的實施例還包括一種半導體處理系統。該半導體處理系統包括:傳送設備;第一處理腔室,該第一處理腔室耦接到該傳送設備;第二處理腔室,該第二處理腔室耦接到該傳送設備;及系統控制器。該系統控制器經配置為控制在該第一處理腔室中執行的沉積製程,控制該基板通過該傳送設備從該第一處理腔室向該第二處理腔室的傳送,以及控制在該第二處理腔室中執行的電漿處理製程。該沉積製程在基板上的鰭片上和鰭片之間共形地沉積預襯裡層。該電漿處理製程使該預襯裡層緻密化以形成襯裡層。
本揭示內容的實施例進一步包括一種半導體處理系統,該半導體處理系統包括非暫時性電腦可讀媒體,該非暫時性電腦可讀媒體儲存指令,該等指令在由處理器執行時致使電腦系統執行操作。該操作包括控制處理系統的第一處理腔室中的沉積製程,控制該基板通過該處理系統的傳送設備從該處理系統的該第一處理腔室向第二處理腔室的傳送,以及控制在該第二處理腔室中的電漿處理製程。該沉積製程在基板上的鰭片上和鰭片之間共形地沉積預襯裡層。該第一處理腔室和該第二處理腔室耦接到該傳送設備。該電漿處理製程使該預襯裡層緻密化以形成襯裡層。
一般地,本文所述的實例涉及用於在基板上的鰭片之間形成隔離結構(例如,淺溝槽隔離(STI))的方法和處理系統。經由這種處理形成的隔離結構可以在例如鰭式場效應電晶體(FinFET)中實現。該方法和處理系統可以提供具有高度共形的氣密襯裡層的隔離結構,該隔離結構可以減少鰭片的氧化,這可以進一步減少鰭片因處理而產生的寬度(例如,臨界尺寸(CD))損失。可以在鰭片之間的距離小的情況下在鰭片之間的溝槽中形成襯裡層。另外地,可以使用低溫(例如,等於或小於550℃)處理來形成襯裡層,這可以減小鰭片的應力和彎折。可以在不使用含氯氣體的情況下形成襯裡層,這可以減少安全性和環境問題,並且可以准許後續處理的靈活性。另外地,可以藉由使用整合處理解決方案來形成襯裡層。
由於半導體裝置不斷地伸縮,在鰭片之間的隔離結構的形成變得越來越有挑戰性。形成用於隔離結構的襯裡層的技術不能形成具有足夠的階梯覆蓋率的襯裡層,這防止了襯裡層氣密。若襯裡層不是氣密的,則其上形成襯裡層的鰭片可能就被氧化,這隨後可能導致在隔離結構的凹陷期間鰭片的寬度損失。另外地,用於形成這種襯裡層的熱預算可能太高,這可能導致在隔離結構中產生應力,如此又可能導致鰭片彎折。
本文所述的實例可以提供高度共形的氣密襯裡層,其能夠減少或防止鰭片的氧化,這可以減少鰭片寬度的損失。襯裡層可以使用低溫處理形成,這可以減小應力和鰭片彎折。本文所述的系統和方法可以提供用於形成襯裡層的整合解決方案,使得其上形成襯裡層的基板在實施用於形成襯裡層的各個製程之間不暴露於大氣周圍環境(例如,製造設施(「晶圓廠(fab)」)中的環境)。藉由避免暴露於大氣周圍環境,可以避免在形成襯裡層的各個製程之間的清潔步驟。本文描述了各種實例的其他益處;不過,本領域的技術人員將容易地理解本揭示內容的範圍內的實例的其他優點及益處。
以下描述各種不同實例。儘管不同實例的多個特徵可以在製程流程或系統中一起進行描述,但是多個特徵也可以各自分開地或單獨地及/或在不同製程流程或不同系統中實施。另外地,各種製程流程經描述為按循序執行;其他實例可以以不同順序及/或以更多或更少的操作實施製程流程。
圖1是根據本揭示內容的一些實例的多腔室處理系統100的示意性俯視圖。處理系統100一般包括裝載鎖定腔室104、106、具有傳送機器人110的傳送腔室108、以及處理腔室112、114、116、118、120、122。處理系統100可以進一步包括工廠介面(未示出)。如本文詳細地描述的,處理系統100中的基板可以在各個腔室中進行處理並在各個腔室之間進行傳送,而不將基板暴露於在處理系統100外部的周圍環境(例如,如可能存在於晶圓廠中的大氣周圍環境)。例如,可以在低壓(例如,小於或等於約300Torr)或真空環境中在各個腔室之間進行傳送基板,而不破壞在處理系統100中在基板上執行的各個製程之間的低壓或真空環境。因此,處理系統100可以提供用於基板的一些處理的整合解決方案。
可根據本文提供的教示適當地修改的處理系統的實例包括Producer®
或可從位於加利福尼亞州聖克拉拉的應用材料公司(Applied Materials, Inc., Santa Clara, California)商購的其他合適的處理系統。可以設想,其他處理系統(包括來自其他製造商的處理系統)可以適於從本文所述的態樣中受益。
如圖所示,處理腔室112、114經分組在串聯單元130中;處理腔室116、118經分組在串聯單元132中;並且處理腔室120、122經分組在串聯單元134中。串聯單元130、132、134可以各自具有相應單個製程氣體供應。串聯單元130、132、134圍繞傳送腔室108定位。處理腔室112、114、116、118、120、122例如經由在處理腔室與傳送腔室之間的相應埠來耦接到傳送腔室108。類似地,裝載鎖定腔室104、106例如經由在裝載鎖定腔室與傳送腔室之間的相應埠來耦接到傳送腔室108。傳送腔室108具有傳送機器人110,以用於在腔室之間處理和傳送基板。在一些實例中,工廠介面可以耦接到裝載鎖定腔室104、106(例如,裝載鎖定腔室104、106設置在工廠介面與傳送腔室108之間)。
裝載鎖定腔室104、106具有耦接到傳送腔室108的相應埠。傳送腔室108進一步具有耦接到處理腔室112、114、116、118、120、122的相應埠。埠可以是例如帶有狹縫閥的狹縫閥開口,以用於經由傳送機器人110使基板從中通過並用於在相應腔室之間提供密封以防止氣體從相應腔室之間通過。一般地,任何埠都是敞開的,以用於傳送基板從中通過;否則,埠是封閉的。
裝載鎖定腔室104、106、傳送腔室108、以及處理腔室112、114、116、118、120、122可以流體地耦接到氣體和壓力控制系統(未具體地示出)。氣體和壓力控制系統可以包括一或多個氣泵(例如,渦輪泵、低溫泵、粗抽泵等)、氣源、各種閥、和流體地耦接到各個腔室的導管。在操作中,基板經傳送到裝載鎖定腔室104或106(例如,從工廠介面)。然後,氣體和壓力控制系統將裝載鎖定腔室104或106抽空。氣體和壓力控制系統進一步將傳送腔室108維持處於內部低壓或真空環境(其可以包括惰性氣體)。因此,抽空裝載鎖定腔室104或106促進基板在例如工廠介面的大氣環境與傳送腔室108的低壓或真空環境之間傳遞。
在基板處於已經被抽空的裝載鎖定腔室104或106中的情況下,傳送機器人110通過將裝載鎖定腔室104或106耦接到傳送腔室108的相應埠將基板從裝載鎖定腔室104或106傳送到傳送腔室108中。然後,傳送機器人110能夠通過相應埠將基板傳送到處理腔室112、114、116、118、120、122中的任一者及/或在處理腔室112、114、116、118、120、122中的任一者之間進行傳送。基板在各個腔室內和各個腔室間的傳送可以在由氣體和壓力控制系統提供的低壓或真空環境中進行。
處理腔室112、114、116、118、120、122可以是用於靶材處理的任何合適的腔室。在一些實例中,處理腔室112能夠執行清潔製程;處理腔室116能夠執行沉積製程(例如,電漿增強CVD或熱CVD製程);並且處理腔室120能夠執行電漿製程及/或熱製程。該等處理腔室112、116、120經標識出以便於之後描述。其他處理腔室可以執行該等製程。處理腔室112可以是可從加利福尼亞州聖克拉拉的應用材料公司獲得的SiCoNi®
預清潔腔室。處理腔室116可以是可從加利福尼亞州聖克拉拉的應用材料公司獲得的Precision®
腔室。處理腔室120可以是可從加利福尼亞州聖克拉拉的應用材料公司獲得的DPXTM
腔室。可以實施可從其他製造商獲得的其他腔室。
系統控制器140耦接到處理系統100,以用於控制處理系統100或處理系統的元件。例如,系統控制器140可以使用對處理系統100的腔室104、106、108、112、114、116、118、120、122的直接控制或藉由控制與腔室104、106、108、112、114、116、118、120、122相關聯的控制器來控制處理系統100的操作。在操作中,系統控制器140使得資料能夠從相應腔室收集和回饋,以協調處理系統100的效能。
系統控制器140一般包括中央處理單元(CPU)142、記憶體144及支援電路146。CPU 142可以是可在工業環境中使用的任何形式的通用處理器中的一種。記憶體144或非暫時性電腦可讀媒體可由CPU 142存取,並且可以是諸如隨機存取記憶體(RAM)、唯讀記憶體(ROM)、軟碟、硬碟或任何其他形式的數位儲存裝置(無論本端還是遠端)的記憶體中的一或多者。支援電路146耦接到CPU 142,並且可以包括快取記憶體、時鐘電路、輸入/輸出子系統、電源等。本文揭示的各種方法一般可以藉由CPU 142執行儲存在記憶體144(或特定處理腔室的記憶體)中的例如作為軟體常式的電腦指令代碼來在CPU 142的控制下實現。當由CPU 142執行電腦指令代碼時,CPU 142控制腔室以根據各種方法來執行製程。
其他處理系統可以採用其他配置。例如,更多或更少的處理腔室可以耦接到傳送設備。在所示的實例中,傳送設備包括傳送腔室108。在其他實例中,更多傳送腔室(例如,兩個或更多個傳送腔室)及/或一或多個保持腔室可以經實施為處理系統中的傳送設備。
圖2是根據本揭示內容的一些實例的可用於執行清潔製程的處理腔室112的截面圖。處理腔室112可以是可從加利福尼亞州聖克拉拉的應用材料公司獲得的SiCoNi®
預清潔腔室。處理腔室112包括腔室主體212、蓋組件214及基板支撐組件216。蓋組件214設置在腔室主體212的上端處,並且基板支撐組件216至少部分地設置在腔室主體212內。腔室主體212、蓋組件214和基板支撐組件216一起限定可在其中處理基板的區域。
蓋組件214包括至少兩個堆疊元件,該至少兩個堆疊元件經配置為在兩個堆疊元件之間形成電漿區域。第一電極220豎直地佈置在第二電極222的上方,以限制在兩個電極之間的電漿體積。第一電極220連接到射頻(RF)電源224,並且第二電極222連接到接地,這在第一電極220與第二電極222之間形成電容。
蓋元件214還包括一或多個氣體埠226,以用於通過阻擋板228和氣體分配板230(諸如噴頭)向基板表面提供清潔氣體。清潔氣體可以是蝕刻劑、離子化氣體或活性自由基,諸如離子化氟、氯或氨。在其他實例中,可以利用不同清潔製程來清潔基板表面。例如,可以通過氣體分配板230將包含氦(He)和三氟化氮(NF3
)的遠端電漿引入處理腔室112中,而可以經由設置在腔室主體212的一側處的單獨進氣埠225將氨(NH3
)直接地佈植處理腔室112中。
基板支撐元件216可以包括基板支撐件232,以在處理期間在其上支撐基板210。基板支撐件232具有平坦基板支撐表面,以用於在其上支撐待處理的基板。基板支撐件232可以經由軸236耦接到致動器234,該軸延伸穿過形成在腔室主體212的底部中的居中地定位的開口。致動器234可以經由波紋管(未示出)柔性地密封以與腔室主體212隔開,從而防止真空從軸236周圍洩漏。致動器234允許基板支撐件232在腔室主體212內在製程位置與下部傳送位置之間豎直地移動。傳送位置在形成在腔室主體212的側壁中的狹縫閥開口的開口稍下方。在操作中,基板支撐件232可以升高到緊鄰蓋組件214的位置,以控制待處理的基板210的溫度。因此,可以經由來自氣體分配板230的發出輻射或對流來加熱基板210。
偏壓電源280可以經由阻抗匹配網路284耦接到基板支撐件232。偏壓電源280向基板210提供偏壓以將離子化清潔氣體引向基板210。
可作為處理系統100的氣體及壓力控制系統的一部分的真空系統可以用於從處理腔室112排出氣體。真空系統包括真空泵218,該真空泵經由閥217耦接到設置在腔室主體212中的真空埠221。處理腔室112還包括控制器(未示出),該控制器可以是系統控制器140或由系統控制器140控制的控制器,以用於控制在處理腔室112內的製程。
圖3是根據本揭示內容的一些實例的可用於執行沉積製程的處理腔室116的截面圖。處理腔室116是用於在基板上沉積薄膜或層的腔室。如本文所述的,處理腔室116經配置為實施電漿增強化學氣相沉積(PECVD),但是其他實例也設想了處理腔室116經配置為實施其他類型的沉積製程,諸如CVD(更廣泛地)、原子層沉積(ALD)或其他沉積製程。處理腔室112可以是可從加利福尼亞州聖克拉拉的應用材料公司獲得的Precision®
腔室。
處理腔室116包括腔室主體302、蓋組件306和基板支撐組件354。蓋組件306設置在腔室主體302的上端處並由該腔室主體支撐,並且基板支撐元件354至少部分地設置在腔室主體302內。腔室主體302、蓋組件306和基板支撐組件354一起限定在處理腔室116內的可在其中處理基板的內部處理區域308。內部處理區域308可以通過形成在腔室主體302中的埠(未示出)進入,該埠促進基板傳送進出處理腔室116。腔室主體302可以由整塊鋁或與處理相容的其他材料製成。
蓋組件306包括基底板310、阻擋板312、氣體分配板314、調製電極316及絕緣體318。例如,基底板310、阻擋板312及氣體分配板314可以由不銹鋼、鋁、陽極氧化鋁、鎳或任何其他RF導電材料製成。進氣埠320穿過基底板310,並且流體地耦接到氣源322。阻擋板312耦接到基底板310並相對於基底板310朝向內部處理區域308設置在內部。阻擋板312具有從中穿過的通路324。絕緣體318(例如,環形絕緣體)設置在阻擋板312與氣體分配板314之間。氣體分配板314(例如,噴頭)具有從中穿過的通路326並相對於阻擋板312朝向內部處理區域308設置在內部。一對絕緣體318(例如,環形絕緣體)設置在氣體分配板314與調製電極316之間。調製電極316是環形的,並且環繞內部處理區域308。絕緣體318(例如,環形絕緣體)設置在調製電極316與腔室主體302之間,諸如當蓋元件306設置在腔室主體302上以進行處理時。絕緣體318將在之間設置相應絕緣體318的相應元件電隔離並在一些情況下熱隔離。絕緣體318可以是介電材料,諸如陶瓷或金屬氧化物,例如氧化鋁及/或氮化鋁。
蓋元件306及/或腔室主體302可以包括加熱和冷卻元件。例如,基底板310可以具有用於使流體循環通過基底板310的導管。流體可以是熱控制流體,諸如冷卻流體(例如,水)。另外,加熱器可以包括在基底板310中,該加熱器與用於使流體循環的導管一起可以為蓋組件306提供熱控制以實現溫度均勻性。
可以由氣源322通過進氣埠320提供製程氣體(例如,一或多種前驅物和一或多種惰性載氣)以引入處理腔室116中。阻擋板312可以向氣體分配板314的背面提供均勻的氣體分配。來自進氣埠320的處理氣體進入部分地限制在基底板310與阻擋板312之間的第一空間328,並且然後流過穿過阻擋板312的通路324進入在阻擋板312與氣體分配板314之間的第二空間330。然後,處理氣體從第二空間330通過穿過氣體分配板314的通路326進入內部處理區域308。可以通過經由閥344流體地耦接到內部處理區域308的真空泵342將處理氣體從內部處理區域308排出。真空泵342可以是處理系統100的氣體和壓力控制系統的一部分。
RF電源340電連接到基底板310並經配置為將RF電位施加到基底板310,以促進在內部處理區域308中產生電漿。RF電源340可以包括能夠產生RF功率(例如,以約13.56 MHz的頻率)的高頻RF電源(「HFRF電源」),或包括能夠產生RF功率(例如,以約300 kHz的頻率)的低頻RF電源(「LFRF電源」)。LFRF電源可以提供低頻生成和固定匹配元素。HFRF電源可以經設計成與固定匹配一起使用,並且可以調節輸送到負載的功率,從而減弱了對前向和反射功率的擔憂。
調製電極316可以耦接到調諧電路346,該調諧電路控制從調製電極316到電接地的電路徑的阻抗。調諧電路346包括電子感測器348和可由電子感測器348控制的可變電容器350。調諧電路346可以是包括一或多個電感器352的LC電路。電子感測器348可以是電壓或電流感測器,並且可以耦接到可變電容器350以提供對內部處理區域308內的電漿條件的一定程度的閉環控制。
基板支撐組件354可以設置在處理腔室116內。基板支撐組件354包括可在處理期間支撐基板356的基板支撐件358。第一電極360和第二電極362設置在基板支撐件358內及/或上。另外,加熱器元件364嵌入在基板支撐件358中。加熱器元件364可操作來將基板支撐組件354和定位在其上的基板356可控地加熱到目標溫度,以便將基板356維持為處於在約150℃至約1,000℃的範圍內的溫度。基板支撐件358耦接到用於支撐的軸366。軸366可以提供來自氣源368的導管以及在基板支撐組件354與處理腔室116的其他元件之間的電和溫度監測引線(未示出)。在一些實例中,可以通過連接到氣源368的一或多個淨化氣體入口369將淨化氣體提供到基板356的背面。朝向基板356的背面流動的淨化氣體可以幫助防止因沉積在基板356的背面上而引起的顆粒污染。淨化氣體也可以用作冷卻基板356的背面的溫度控制形式。儘管未示出,但是軸366可以耦接到如以上關於圖2所述的那樣的致動器。致動器可以經由波紋管(未示出)柔性地密封以與腔室主體302隔開,從而防止真空從軸366周圍洩漏。致動器可以允許基板支撐件358在腔室主體302內在製程位置與下部傳送位置之間豎直地移動。傳送位置在形成在腔室主體302的側壁中的狹縫閥開口的開口稍下方。在操作中,基板支撐件358可以升高到緊鄰蓋組件306的位置,這可以進一步控制待處理的基板356的溫度。
第一電極360可以嵌入在基板支撐件358內或耦接到基板支撐件358的表面。第一電極360可以是板、穿孔板、網、金屬絲網或任何其他分配佈置。第一電極360可以是調諧電極,並且可以耦接到調諧電路370。調諧電路370可以具有電子感測器372和可變電容器374,該可變電容器374電連接在第一電極360與電接地之間。電子感測器372可以是電壓或電流感測器,並且可以耦接到可變電容器374,以提供對內部處理區域308中的電漿條件的進一步控制。
可作為偏壓電極的第二電極362可以耦接到基板支撐件358。第二電極362可以通過阻抗匹配電路378耦接到偏壓電源376。偏壓電源376可以是DC功率、脈衝DC功率、RF功率、脈衝RF功率或它們的組合。
處理腔室112還包括控制器(未示出),該控制器可以是系統控制器140或由系統控制器140控制的控制器,以用於控制在處理腔室112內的製程。
在操作中,基板設置在基板支撐件358上並根據任何期望的流動計畫使製程氣體流過蓋組件306。為處理腔室116中的各種熱元件建立溫度設定點。電功率耦接到基底板310,以在內部處理區域308中建立電漿。若需要,可以使用偏壓電源376對基板進行電偏壓。
當在內部處理區域308中激發電漿後,在電漿與調製電極316之間建立電位差。在電漿與第一電極360之間也建立了電位差。然後,可變電容器350和374可以用於調整到由調諧電路346和370表示的電接地的路徑的阻抗。可以將設定點輸送到調諧電路346和370,以提供對從中心到邊緣的電漿密度均勻性以及沉積速率的獨立控制。電子感測器可以獨立地調整可變電容器以最大化沉積速率並最小化厚度不均勻性。除其他外,經實施來控制電漿的溫度和均勻性的元件可以准許高度共形的層沉積在待處理的基板上,即使在很小間隙內。
圖4是根據本揭示內容的一些實例的可用於執行電漿處理的處理腔室120的截面圖。處理腔室120是用於使用電漿處理基板(諸如已經形成在基板表面上的薄膜)的腔室。如本文所述的,處理腔室120經配置為實現電感耦合電漿(ICP),但是其他實例也設想了處理腔室120經配置為實施其他類型的電漿,諸如電容耦合電漿(CCP)。處理腔室112可以是可從加利福尼亞州聖克拉拉的應用材料公司獲得的DPXTM
腔室。
如圖所示,處理腔室120包括腔室主體402、蓋組件404和基板支撐組件410。蓋組件404設置在腔室主體402的上端處並由該腔室主體支撐,並且基板支撐元件410至少部分地設置在腔室主體402內。腔室主體402、蓋組件404和基板支撐組件410一起限定在處理腔室120內的可在其中處理基板的內部處理區域406。內部處理區域406可以通過形成在腔室主體402中的埠(未示出)進入,該埠促進基板傳送進出處理腔室120。
腔室主體402可以耦接到電接地。腔室主體402可以包括嵌入其中的加熱和冷卻元件。例如,容納液體的導管(未示出)可以延行穿過腔室主體402,及/或加熱元件可以嵌入在腔室主體402中(例如,加熱盒或線圈)或可以包裹在內部處理區域406周圍(例如,加熱套或膠帶)。蓋元件404可以包括任何合適的介電質或由任何合適的介電質組成,諸如石英。對於一些實例,蓋組件404可以是各種形狀(例如,圓頂形的)。在一些實例中,蓋組件404可以塗覆陶瓷塗層,以用於進行保護以免受電漿物種。
基板支撐組件410包括基板支撐件412(例如,靜電吸盤(ESC))。基板支撐件412經配置為在基板414的處理期間將基板414固定在基板支撐組件410上,諸如包括將基板414暴露於在內部處理區域406中的電漿。在一些實例中,基板支撐件412及/或基板支撐組件410包括加熱及/或冷卻元件,該加熱及/或冷卻元件經配置為在處理期間控制基板414的溫度。在一些實例中,藉由使用加熱和冷卻元件,可以將基板支撐件412的溫度控制在約20℃至約500℃的範圍內。例如,經由嵌入在基板支撐組件410內的加熱和冷卻元件對基板支撐件412和基板414的溫度控制可以幫助降低因離子轟擊而引起的不想要的溫度。
在一些實例中,經由導管418耦接到基板支撐組件410的氣源416可以促進基板支撐元件410與基板之間的熱傳遞。來自氣源416的氣體可以經由導管418經提供到在基板414下方的基板支撐組件410的表面(例如,基板支撐件412的表面)中形成的通道(未示出)。氣體可以促進在基板支撐組件410與基板414之間的熱傳遞。在處理期間,可以將基板支撐組件410加熱到穩態溫度,並且然後氣體可以促進基板414的均勻加熱。可以經由加熱元件(未示出)來加熱基板支撐組件410,加熱元件諸如嵌入在基板支撐元件410內的電阻加熱器或一般對準基板支撐組件410或當在該基板支撐組件上時的基板414的燈。
處理腔室120包括氣源420、一或多個進氣埠422、閥424(例如,節流閥)和真空泵426。氣源420、閥424和真空泵426單獨地和及/或共同地可以是處理系統100的氣體和壓力控制系統的一部分。可以通過一或多個進氣埠422從氣源420供應一或多種製程氣體,以在內部處理區域406中供應氣體來產生電漿。閥424經配置成準許從內部處理區域406維持或排出氣體。真空泵426經配置為從內部處理區域406排出或排放氣體,例如當閥424打開時。氣源420、閥424和真空泵426可以經配置為共同地維持內部處理區域406內的目標壓力。
處理腔室120包括電漿發生器430。電漿發生器430包括感應線圈元件432、第一阻抗匹配網路434、RF電源436、遮罩電極438、開關440及檢測器442。如圖所示,包括至少一個感應線圈元件432的RF天線設置在蓋組件404上。在一些實例中,諸如如圖4所示,圍繞處理腔室120的內部處理區域406的中心軸線設置的兩個同軸線圈元件電連接在第一阻抗匹配網路434與電接地之間,並且第一阻抗匹配網路434電連接到RF電源436。感應線圈元件432可以以RF頻率被驅動,例如,經由RF電源436,以在處理腔室120的內部處理區域406中產生電漿。在一些實例中,可以圍繞腔室主體402的至少一部分設置一或多個感應線圈元件432。在一些實例中,RF電源436能夠以13.56MHz的頻率產生例如高達4kW的RF功率。例如,供應到感應線圈元件432的RF功率可以以高達100kHz的頻率經脈衝或進行功率循環。
如圖所示,遮罩電極438插置在RF天線的感應線圈元件432與蓋組件404之間,但是在一些實例中可以省略遮罩電極438。遮罩電極438可以選擇性地(例如,交替地)電浮動或經由諸如開關440的用於進行和斷開電連接的任何合適的機構耦接到電接地。
在一些實例中,檢測器442可以附接到腔室主體402,以促進確定內部處理區域406內的氣體何時已經經激發成電漿。檢測器442可以例如檢測由經激發的氣體發出的輻射或使用光學發射光譜(OES)來量測與所產生的電漿相關聯的一或多個波長的光的強度。
處理腔室120還包括第二阻抗匹配網路452和偏壓電源454。基板支撐元件410可以經由第二阻抗匹配網路452來耦接到偏壓電源454。偏壓電源454與RF電源436類似地能夠產生具有在1MHz至160MHz的範圍內的驅動頻率和在約0kW至約3kW的範圍內的功率的RF信號。偏壓電源454能夠在2MHz至160MHz範圍內的頻率(例如,以13.56MHz或2MHz的頻率)下產生在約1W至約1kW的範圍內的功率。在一些實例中,偏壓電源454可以是DC或脈衝DC源。在一些實例中,耦接到偏壓電源454的電極設置在基板支撐件412內。偏壓電源454可以在基板414上提供基板電壓偏壓以促進對基板414的處理。
處理腔室112還包括控制器(未示出),該控制器可以是系統控制器140或由系統控制器140控制的控制器,以用於控制在處理腔室112內的製程。
在操作中,基板414可以放置在基板支撐件412上,並且一或多種製程氣體可以從氣源420通過一或多個進氣埠422供應到處理腔室120的內部處理區域406中。供應到內部處理區域406中的一或多種氣體可以在內部處理區域406中由電漿發生器430(例如,通過供應來自RF電源436的功率)激發成電漿460。偏壓電源454可以在基板414上提供電壓偏壓(例如,藉由從偏壓電源454提供電壓),以促進電漿製程。在內部處理區域406內的壓力和基板414的溫度可以經控制為目標壓力和目標溫度。電漿460可以轟擊基板414,例如以更改基板414上的膜的性質。
可以藉由使用任何電漿診斷技術來量測電漿460的電漿密度,諸如藉由使用自激電子電漿共振光譜(SEERS)、朗繆爾探針(Langmuir probe)或其他合適的技術。感應線圈元件432配置,諸如如圖4所示,對比諸如電容耦合電漿的其他電漿源配置來說,可以提供高密度電漿的改進的控制和產生。
圖5是根據本揭示內容的一些實例的半導體處理的方法500的流程圖。圖6至圖10是圖示根據本揭示內容的一些實例的圖5的方法500的各態樣的中間半導體結構的截面圖。本文所述的實例是在基板上的鰭片之間形成隔離結構(例如,淺溝槽隔離(STI))的上下文中。本領域的技術人員將容易地理解本文所述的態樣在其他上下文中的各種應用,並且在其他實例的範圍內也設想了此類變型。
根據圖5的方塊502,在基板2上形成鰭片10。圖6圖示了在基板2上形成的鰭片10的截面圖。為了獲得圖6的結構,提供基板2。基板2可以是任何合適的半導體基板,諸如體基板、絕緣體上半導體(SOI)基板等。在一些實例中,基板2是體矽晶圓。基板尺寸的實例包括200mm直徑、350mm直徑、400mm直徑、和450mm直徑。在基板2上形成磊晶層6(例如,異質磊晶層)。在一些實例中,磊晶層6的材料是矽鍺。可以使用任何適當的磊晶生長製程來形成磊晶層6。
然後,在基板2上形成鰭片10。可以經由蝕刻特徵(諸如延伸到基板2中的溝槽12)來形成鰭片10,使得每個鰭片10經限定在一對相鄰特徵(例如,溝槽12)之間。如圖所示,掩模部分8形成在磊晶層6上並用於掩蔽形成溝槽12的蝕刻。例如,掩模部分8可以是或包括氮化物,諸如氮化矽、碳氮化矽、氮氧化矽等。掩模部分8的層可以沉積在磊晶層6上並使用適當的圖案化製程在蝕刻製程中經圖案化到掩模部分8中。圖案化製程可以包括多重圖案化製程,諸如自對準雙重圖案化(SADP)、微影-蝕刻-微影-蝕刻(LELE)雙重圖案化等,以在鰭片10之間實現目標間距。蝕刻溝槽12的示例蝕刻製程包括反應離子蝕刻(RIE)製程等。如圖6所示,每個鰭片10包括磊晶層6的一部分和基板2的一部分2A,在該兩者上有掩模部分8。
根據方塊504,然後,將其上形成鰭片10的基板2傳送到處理系統,諸如圖1的處理系統100。例如,基板2經由前開式晶元傳送盒(FOUP)傳送到工廠介面,並且在工廠介面處,基板2通過埠從FOUP傳送到裝載鎖定腔室104或106。然後如上所述將裝載鎖定腔室104或106抽空。後續傳送和處理是在處理系統100中執行,如方塊506所示,例如而不將基板2暴露於在處理系統100外部的大氣周圍環境且不破壞在處理系統100的傳送設備內維持的低壓或真空環境。方塊506中所示的處理僅是實例。方塊506中的一些製程可能不在處理系統100中執行,及/或附加製程可能在處理系統100中執行。
在方塊508中,任選地,將基板2傳送到處理系統100的第一處理腔室,例如處理腔室112。例如,傳送機器人110通過埠從裝載鎖定腔室104或106傳送基板2並通過埠到達處理腔室112。在方塊510中,任選地,在處理腔室112中的基板2上執行清潔製程。清潔製程可以是SiCoNi®
預清潔製程。清潔製程可以移除由於在將基板2運輸到處理系統100期間暴露於大氣周圍環境而在鰭片10上形成的任何原生氧化物。
在圖2所示的處理腔室112中執行的一些實例中,清潔製程包括使三氟化氮(NF3
)和氦(He)的混合物從進氣埠226流入並使氨(NH3
)從進氣埠225流入。三氟化氮(NF3
)和氦(He)的混合物的比例在1:350 (NF3
:He)至1:120 (NF3
:He)的範圍內,該混合物可以從進氣埠226以5000sccm至7000sccm的範圍內的流率流動,諸如其中三氟化物(NF3
)的流率為在10 sccm至25 sccm的範圍內,而氦(He)的流率為在約3000 sccm至3500 sccm的範圍內。在清潔製程期間腔室122中的壓力可以維持處於在0.25 Torr至約2 Torr的範圍內。由RF電源224施加的功率可以在約10 MHz至約20 MHz的範圍內(例如,13.56MHz)的頻率下在約10 W至約50 W的範圍內。
在處理腔室112中執行清潔製程之後,在方塊512中,將基板2傳送到處理系統100的第二處理腔室,例如處理腔室116。例如,藉由傳送機器人110將基板2從處理腔室112傳送通過埠並通過另一個埠到達處理腔室116。
在方塊514中,在處理腔室116中在基板2上執行沉積製程以形成預襯裡層14。圖7圖示預襯裡層14的形成。預襯裡層14共形地形成在溝槽12和鰭片10中。在一些實例中,預襯裡層14諸如通過PECVD、ALD等在該溝槽12中和鰭片10上共形地沉積。在一些實例中,預襯裡層14是或包括非晶矽,但是在其他實例中,預襯裡層14可以是或包括能夠經緻密化以形成氣密阻擋物的任何材料。在一些實例中,預襯裡層14的厚度在約1 nm至約4 nm的範圍內,諸如約1.5 nm至約2.5 nm,諸如約2 nm。預襯裡層14可以沿著鰭片10和溝槽12具有良好的階梯覆蓋率。處理腔室116可以是Precision®
腔室,其可以執行沉積製程,諸如在圖3中所示。
在圖3所示的處理腔室116中執行的一些實例中,沉積製程沉積非晶矽的預襯裡層14。在此類實例中,可以從氣源322供應含矽前驅物氣體,示例的前驅物氣體包括乙矽烷(Si2
H6
)、丙矽烷(Si3
H8
)及/或其他含矽前驅物。前驅物氣體的流率可以在約10 sccm至約2000 sccm的範圍內。前驅物氣體可以與惰性載氣(諸如氬(Ar)、氦(He)、氫(H2
)、氮(N2
)等)混合。在沉積製程中內部處理區域308內的壓力可以維持在較大壓力下,諸如達到或包括600 Torr。在沉積製程期間處理溫度可以在約100℃至約500℃的範圍內。處理腔室116可以准許在高壓和等於或小於550℃的低溫下(具有高溫均勻性)沉積預襯裡層14,這可以准許在小尺度的間隙(諸如溝槽12)中沉積高度共形的層。
在處理腔室116中執行沉積製程之後,在方塊516中,將基板2傳送到處理系統100的第三處理腔室,例如處理腔室120。例如,經由傳送機器人110將基板2從處理腔室116傳送通過埠並通過另一個埠到達處理腔室120。
在方塊518中,在處理腔室120中的基板2上執行電漿處理製程以將預襯裡層14緻密化以形成襯裡層16。圖8圖示了將預襯裡層14緻密化以形成襯裡層16。可以使用電漿製程使預襯裡層14緻密化以形成襯裡層16。在一些實例中,實施氦及/或含氮電漿。預襯裡層14可以暴露於含氦及/或氮電漿,它使襯裡層14緻密,並且在某些情況下使氮擴散到預襯裡層14中及/或與預襯裡層14反應以形成襯裡層16。因此,在一些實例中,電漿製程可以因此使預襯裡層14氮化以形成襯裡層16。在預襯裡層14為非晶矽且隨後使用含氮電漿緻密化的實例中,襯裡層16可以是含氮矽層(例如「類氮化物」層)及/或氮化矽層。襯裡層16可以在鰭片10上形成氣密阻擋物,以減少及/或防止氧在後續處理期間穿過襯裡層16擴散到鰭片10。處理腔室120可以是可執行電漿製程的DPXTM
腔室,如圖4所示。
在圖4所示的處理腔室120中執行的一些實例中,非晶矽的預襯裡層14經由電漿製程進行緻密化和氮化,以形成類氮化物層或氮化矽的襯裡層16。在此類實例中,電漿製程可以包括藉由使含氮製程氣體從氣源420流過進氣埠422來產生含氮電漿,該含氮製程氣體可以包括惰性載氣。在一些實例中,含氮製程氣體是或包括氮(N2
)和氬(Ar)或氦(He)的混合物。在電漿製程期間在內部處理區域406中的壓力可以在約1 mTorr至約100 mTorr的範圍內。在電漿製程期間RF電源436的功率可以在約2 MHz至約160 MHz的範圍內(例如13.56 MHz)的頻率下在約500 W至約5000 W的範圍內。在一些實例中,RF電源的功率可以是脈衝的。偏壓電源454可以關閉或可以不向基板支撐件施加任何功率。偏壓電源454的功率可以在約2 MHz至約160 MHz的範圍內(約13.56 MHz)的頻率下在約0 W至約2000 W的範圍內。在電漿製程期間基板支撐件412的溫度可以在約150℃至約500℃的範圍內,諸如約450℃。在電漿製程的一些實例中,將基板溫度保持在約350℃至500℃,向製程氣體提供約2000 W至2500 W的RF功率,施加約0W至1000 W(例如,1W至100W)的基板RF偏壓功率,將腔室保持在約5 mTorr至20 mTorr,並且使氮和氦流動達約4分鐘的時間段。
返回參考方塊514,在一些實例中,襯裡層16在不使用含氯氣體的情況下形成。藉由避免使用含氯氣體,就不形成危險和腐蝕性副產物氣體(諸如鹽酸(HCl)和氯(Cl2
))。因此,可以實現安全且環境友好的優點。因此,如以上的一些實例所述,預襯裡層14的沉積可以實現含矽前驅物和惰性載氣,該兩者都不包含氯,並且預襯裡層14緻密化以形成襯裡層16可以實現含氮電漿,該含氮電漿可以包括惰性載氣,該兩者都不包含氯。
在單個處理系統100內傳送基板2准許傳送基板2,而不將基板2暴露於在處理系統100外部的大氣周圍環境中(例如,製造設施環境)。藉由避免將基板2暴露於該大氣周圍環境,可以避免在處理腔室116中的處理與在處理腔室120中的處理之間進行清潔處理,例如,由於沒有發生因暴露於這種大氣周圍環境而引起的氧化或污染。
藉由如上所述形成襯裡層16,襯裡層16可以是高度氣密的層。藉由成為高度氣密的層,幾乎沒有氧可以擴散或穿透襯裡層16到達鰭片10。因此,相對於可形成為隔離結構的一部分的其他襯裡層,鰭片10的側面可以具有減少的氧化或沒有氧化。在鰭片10減少或沒有氧化的情況下,鰭片10的寬度(例如,臨界尺寸(CD))可以在後續處理期間更容易地維持。例如,若鰭片10的側面經顯著地氧化,則對隨後沉積的介電材料進行蝕刻以使該材料凹陷(如下所述)可能導致鰭片10的氧化面也經蝕刻,這使鰭片10的寬度發生損失。在完全沒有氧化或幾乎沒有氧化的情況下,將完全沒有或幾乎沒有氧化物經蝕刻,使得鰭片10的寬度完全沒有損失或幾乎沒有損失。高度氣密的層可以准許基板2隨後暴露於例如大氣周邊環境,而不發生顯著氧化,並且可以准許在本來可能導致顯著氧化的後續處理中有自由度。
在處理腔室120中的電漿處理製程之後,基板2可以由傳送機器人110通過埠從處理腔室120傳送通過埠到達另一個處理腔室(例如,用於後續材料的沉積)及/或然後通過埠將基板2傳送到裝載鎖定腔室104或106。然後,將基板2通過埠從裝載鎖定腔室104或106傳送出,經由工廠介面到達FOUP。然後,可以將基板2運輸到其他處理系統進行進一步處理。
在方塊520中,將介電材料18沉積在基板2上。圖9圖示了在襯裡層16上形成介電材料18。在一些實例中,介電材料18在襯裡層16上流動到溝槽12中並流動到鰭片10上作為一種材料並轉換成另一種材料。作為一個實例,使含氮材料流動並隨後轉換成氧化物材料以形成介電材料18。介電材料18的形成可以是通過可流動CVD(FCVD)進行的。FCVD的轉換製程可以包括例如在高壓環境中使流動材料暴露於蒸氣。高壓環境可以達到並包括80巴的壓力(例如,約60,000 Torr),諸如在1巴至80巴的範圍內。由於存在高度氣密的襯裡層16,因此在高壓環境下的轉化可以執行而幾乎沒有或完全沒有氧化鰭片10的風險,如上所述。
圖10圖示了介電材料18和襯裡層16凹陷以在鰭片10之間的溝槽12中形成隔離結構(例如,STI)。在方塊522中,執行平坦化製程,諸如化學機械平坦化(CMP),以將介電材料18和襯裡層16的頂表面與鰭片10的磊晶層6的頂表面(未示出)平坦化。因此,平坦化製程可以去除掩模部分8。在方塊524中,使介電材料18和襯裡層16凹陷,如圖10所示。可以執行一或多個蝕刻製程以使介電材料18和襯裡層16凹陷,使得鰭片10從相鄰隔離結構之間突出。隔離結構的頂表面(例如,介電材料18和襯裡層16的頂表面)可以從鰭片10的頂表面凹陷到變化深度,並且圖10的圖示僅是實例。如上所述,襯裡層16是氣密的,使得鰭片10不被顯著地氧化,這可以減小在介電材料18和襯裡層16凹陷期間鰭片10的寬度損失。
鰭片10和在其之間的隔離結構之後可以用於形成任何合適的裝置結構。例如,鰭片10可以用於形成FinFET。閘極結構可以形成在鰭片10上並縱向地垂直於鰭片10。閘極結構可以包括沿著鰭片的表面的閘極介電質(例如,高介電常數閘極介電質)、在閘極介電質上的一或多個功函數調諧層、以及在功函數調諧層上的金屬填充物。閘極結構可以在位於閘極結構下方的相應鰭片10中限定通道區域。可以在鰭片中在通道區域的相對側上形成源極/汲極區域(例如,磊晶源極/汲極區域)
。閘極結構、通道區域和源極/汲極區域一起可以形成FinFET。
在本文所述的實例中,可以形成在鰭片之間的隔離結構,其中在鰭片之間的尺寸減小。可以在鰭片之間形成厚度小的、高度共形的、氣密的襯裡層。襯裡層可以減少鰭片的氧化,這可以減少鰭片的寬度損失並提高在後續處理中的靈活性。可以經由低溫處理形成隔離結構,這可以減少鰭片的應力和彎折。另外,可以在不使用含氯氣體的情況下形成襯裡層,這可以減少安全性和環境問題。另外,襯裡層的形成可以在單個處理系統100中執行,這准許基板2在不同腔室之間傳送以進行不同處理,而無需將基板2暴露於在處理系統100(例如,晶圓廠環境)外部的大氣周圍環境。藉由避免將基板暴露於這種大氣周圍環境,可以避免在不同處理之間進行清潔處理,諸如由於沒有發生因暴露於這種大氣周圍環境而導致的氧化和污染。因此,本文所述的實例提供用於形成襯裡層的整合解決方案。
儘管前述內容涉及本揭示內容的各個實例,但是在不脫離本揭示內容的基本範圍的情況下,可以設想本揭示內容的其他和進一步實例,並且本揭示內容的範圍由所附申請專利範圍確定。
2:基板
2A:部分
6:磊晶層
8:掩模部分
10:鰭片
12:溝槽
14:預襯裡層
16:襯裡層
18:介電材料
100:處理系統
104,106:裝載鎖定腔室
108:傳送腔室
110:傳送機器人
112~122:處理腔室
130~134:串聯單元
140:系統控制器
142:中央處理單元
144:記憶體
146:支援電路
210:基板
212:腔室主體
214:蓋組件
216:基板支撐組件
217:閥
218:真空泵
220:第一電極
221:真空埠
222:第二電極
224:RF電源
225:進氣埠
226:進氣埠
228:阻擋板
230:氣體分配板
232:基板支撐件
234:致動器
236:軸
280:偏壓電源
284:阻抗匹配網路
302:腔室主體
306:蓋組件
308:內部處理區域
310:基底板
312:阻擋板
314:氣體分配板
316:調製電極
318:絕緣體
320:進氣埠
322:氣源
324,326:通路
328:第一空間
330:第二空間
340:RF電源
342:真空泵
344:閥
346:調諧電路
348:電子感測器
350:可變電容器
352:電感器
354:基板支撐組件
356:基板
358:基板支撐件
360:第一電極
362:第二電極
364:加熱器元件
366:軸
368:氣源
369:淨化氣體入口
370:調諧電路
372:電子感測器
374:可變電容器
376:偏壓電源
378:阻抗匹配電路
402:腔室主體
404:蓋組件
406:內部處理區域
410:基板支撐組件
412:基板支撐件
414:基板
416:氣源
418:導管
420:氣源
422:進氣埠
424:閥
426:真空泵
430:電漿發生器
432:感應線圈元件
434:第一阻抗匹配網路
436:RF電源
438:遮罩電極
440:開關
442:檢測器
452:第二阻抗匹配網路
454:偏壓電源
460:電漿
500:方法
502~524:步驟
為了能夠詳細地理解本揭示內容的上述特徵的方式,可以參考實例得到上文簡要地概述的更特定的描述,其中一些實施例在附圖中示出。然而,應當注意,附圖僅圖示了一些實例,並且因此不應視為對本揭示內容的範圍的限制,因為本揭示內容可以允許其他等效實例。
圖1是根據本揭示內容的一些實例的示例多腔室處理系統的示意性俯視圖。
圖2是根據本揭示內容的一些實例的可用於執行清潔製程的處理腔室的截面圖。
圖3是根據本揭示內容的一些實例的可用於執行沉積製程的處理腔室的截面圖。
圖4是根據本揭示內容的一些實例的可用於執行電漿處理的處理腔室的截面圖。
圖5是根據本揭示內容的一些實例的半導體處理的方法的流程圖。
圖6至圖10是圖示根據本揭示內容的一些實例的圖5的方法的態樣的中間半導體結構的截面圖。
為了便於理解,已經盡可能地使用相同的元件符號標示各圖共有的相同元件。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記)
無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記)
無
500:方法
502~524:步驟
Claims (20)
- 一種用於半導體處理的方法,該方法包括以下步驟: 在一基板上形成鰭片; 在該等鰭片上和該等鰭片之間共形地形成一襯裡層,形成該襯裡層之步驟包括以下步驟: 在該等鰭片上和該等鰭片之間共形地沉積一預襯裡層;和 使用一電漿處理使該預襯裡層緻密化以形成該襯裡層;以及 在該襯裡層上和該鰭片之間形成一介電材料。
- 如請求項1所述之方法,其中: 形成該襯裡層在一單個處理系統中執行; 共形地沉積該預襯裡層在該單個處理系統的一第一處理腔室中執行; 使該預襯裡層緻密化在該單個處理系統的一第二處理腔室中執行;以及 該基板通過該單個處理系統的一傳送設備從該第一處理腔室傳送到該第二處理腔室。
- 如請求項2所述之方法,其中在不將該基板暴露於一大氣周圍環境的情況下將該基板從該第一處理腔室傳送到該第二處理腔室。
- 如請求項2所述之方法,其中在該傳送設備中的具有小於或等於300 Torr的一壓力的傳送環境中來將該基板從該第一處理腔室傳送到該第二處理腔室,而不在該傳送期間去除該傳送環境。
- 如請求項1所述之方法,其中形成該襯裡層不包括使用一含氯氣體。
- 如請求項1所述之方法,其中形成該介電材料包括以下步驟: 使一可流動材料流動;和 將該可流動材料轉換成該介電材料,轉換包括將該可流動材料暴露於具有在1巴至80巴的一範圍內的壓力的一環境中。
- 如請求項1所述之方法,其中該預襯裡層是一矽層,並且該襯裡層是氮化矽。
- 如請求項1所述之方法,進一步包括以下步驟:使該介電材料和該襯裡層凹陷,其中在凹陷之後,該鰭片突出於該介電材料和該襯裡層的頂表面的上方。
- 一種半導體處理系統,包括: 一傳送設備; 一第一處理腔室,該第一處理腔室耦接到該傳送設備; 一第二處理腔室,該第二處理腔室耦接到該傳送設備;和 一系統控制器,該系統控制器經配置為: 控制在該第一處理腔室中執行的一沉積製程,該沉積製程在一基板上的鰭片上和鰭片之間共形地沉積一預襯裡層; 控制該基板通過該傳送設備從該第一處理腔室向該第二處理腔室的一傳送;和 控制在該第二處理腔室中執行的一電漿處理製程,該電漿處理製程使該預襯裡層緻密化以形成一襯裡層。
- 如請求項9所述之半導體處理系統,進一步包括一第三處理腔室,該第三處理腔室耦接到該傳送設備,其中該系統控制器經配置為: 控制在該第三處理腔室中執行的一清潔製程,該清潔製程清潔該基板;以及 控制該基板通過該傳送設備從該第三處理腔室向該第一處理腔室的一傳送。
- 如請求項9所述之半導體處理系統,其中該系統控制器經配置為經由一真空環境使該基板從該第一處理腔室傳送到該第二處理腔室。
- 如請求項9所述之半導體處理系統,其中該系統控制器經配置為在該基板從該第一處理腔室傳送到該第二處理腔室期間維持該傳送設備中的一壓力小於或等於300 Torr。
- 如請求項9所述之半導體處理系統,其中該沉積製程和該電漿處理製程不包括使用一含氯氣體。
- 如請求項9所述之半導體處理系統,其中: 該沉積製程包括使一含矽前驅物氣體流動,該預襯裡層是一矽層;並且 該電漿處理製程包括使一含氮氣體流動,該襯裡層是一氮化矽層。
- 一種半導體處理系統,包括: 一非暫時性電腦可讀媒體,該非暫時性電腦可讀媒體儲存指令,該等指令在由一處理器執行時致使一電腦系統執行以下操作: 控制一處理系統的一第一處理腔室中的一沉積製程,該沉積製程在一基板上的鰭片上和鰭片之間共形地沉積一預襯裡層; 控制該基板通過該處理系統的一傳送設備從該處理系統的該第一處理腔室向一第二處理腔室的一傳送,該第一處理腔室和該第二處理腔室耦接到該傳送設備;以及 控制在該第二處理腔室中的一電漿處理製程,該電漿處理製程使該預襯裡層緻密化以形成一襯裡層。
- 如請求項15所述之半導體處理系統,其中控制該基板從該第一處理腔室向該第二處理腔室的該傳送在不將該基板暴露於在該處理系統外部的一周圍環境的情況下執行。
- 如請求項15所述之半導體處理系統,其中控制該基板從該第一處理腔室向該第二處理腔室的該傳送包括控制在該傳送設備中在具有小於或等於300 Torr的一壓力的一傳送環境中該基板的該傳送。
- 如請求項15所述之半導體處理系統,其中該指令在由該處理器執行時不使該電腦系統在該沉積製程之後和該電漿處理製程之前實施一清潔製程。
- 如請求項15所述之半導體處理系統,其中該沉積製程和該電漿處理製程不包括使用一含氯氣體。
- 如請求項15所述之半導體處理系統,其中: 該沉積製程包括使一含矽前驅物氣體流動,該預襯裡層是一矽層;以及 該電漿處理製程包括使一含氮氣體流動,該襯裡層是一氮化矽層。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862768569P | 2018-11-16 | 2018-11-16 | |
US62/768,569 | 2018-11-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202038380A true TW202038380A (zh) | 2020-10-16 |
TWI804693B TWI804693B (zh) | 2023-06-11 |
Family
ID=70726718
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108140249A TWI804693B (zh) | 2018-11-16 | 2019-11-06 | 用於隔離結構的伸縮襯裡層 |
TW112103627A TW202322252A (zh) | 2018-11-16 | 2019-11-06 | 用於隔離結構的伸縮襯裡層 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW112103627A TW202322252A (zh) | 2018-11-16 | 2019-11-06 | 用於隔離結構的伸縮襯裡層 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20200161171A1 (zh) |
KR (1) | KR102316186B1 (zh) |
CN (1) | CN111199918B (zh) |
TW (2) | TWI804693B (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3428955A1 (en) * | 2017-07-10 | 2019-01-16 | Murata Manufacturing Co., Ltd. | Substrates employing surface-area amplification, for use in fabricating capacitive elements and other devices |
US10861722B2 (en) * | 2018-11-13 | 2020-12-08 | Applied Materials, Inc. | Integrated semiconductor processing |
US11171206B2 (en) * | 2019-07-11 | 2021-11-09 | Micron Technology, Inc. | Channel conduction in semiconductor devices |
KR20210035449A (ko) * | 2019-09-24 | 2021-04-01 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US11581438B2 (en) * | 2020-08-12 | 2023-02-14 | United Microelectronics Corp. | Fin structure for fin field effect transistor and method for fabrication the same |
US11499223B2 (en) | 2020-12-10 | 2022-11-15 | Applied Materials, Inc. | Continuous liner for use in a processing chamber |
US11469229B2 (en) | 2021-01-15 | 2022-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US11862482B2 (en) * | 2021-03-11 | 2024-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor substrate bonding tool and methods of operation |
US11323070B1 (en) | 2021-04-16 | 2022-05-03 | Apple Inc. | Oscillator with fin field-effect transistor (FinFET) resonator |
US20220364230A1 (en) * | 2021-05-12 | 2022-11-17 | Applied Materials, Inc. | Pulsing plasma treatment for film densification |
JP2022178406A (ja) * | 2021-05-20 | 2022-12-02 | 東京エレクトロン株式会社 | 温度制御方法及び温度制御装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1124252A2 (en) * | 2000-02-10 | 2001-08-16 | Applied Materials, Inc. | Apparatus and process for processing substrates |
KR100621888B1 (ko) * | 2005-07-19 | 2006-09-11 | 삼성전자주식회사 | 소자 분리막 형성 방법 및 이를 이용 핀형 전계 효과트랜지스터의 제조방법 |
KR101363002B1 (ko) * | 2011-12-30 | 2014-02-18 | 엘아이지에이디피 주식회사 | 플라즈마를 이용한 기판처리장치 및 기판처리방법 |
US20130288485A1 (en) * | 2012-04-30 | 2013-10-31 | Applied Materials, Inc. | Densification for flowable films |
US20140273530A1 (en) * | 2013-03-15 | 2014-09-18 | Victor Nguyen | Post-Deposition Treatment Methods For Silicon Nitride |
US9711399B2 (en) * | 2013-12-26 | 2017-07-18 | Intel Corporation | Direct plasma densification process and semiconductor devices |
US9761658B2 (en) * | 2014-12-30 | 2017-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench isolation structure with raised portion between active areas and manufacturing method thereof |
US9601626B2 (en) * | 2015-01-23 | 2017-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structure with two channel layers and manufacturing method thereof |
US9991154B2 (en) * | 2016-02-25 | 2018-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a fin field effect transistor and a shallow trench isolation |
US10358715B2 (en) * | 2016-06-03 | 2019-07-23 | Applied Materials, Inc. | Integrated cluster tool for selective area deposition |
CN107591364B (zh) * | 2016-07-07 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN107887273A (zh) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
US10008497B2 (en) * | 2016-11-29 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
US10373879B2 (en) * | 2017-04-26 | 2019-08-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with contracted isolation feature and formation method thereof |
-
2019
- 2019-09-23 US US16/579,759 patent/US20200161171A1/en not_active Abandoned
- 2019-10-31 CN CN201911052573.8A patent/CN111199918B/zh active Active
- 2019-11-06 TW TW108140249A patent/TWI804693B/zh active
- 2019-11-06 TW TW112103627A patent/TW202322252A/zh unknown
- 2019-11-14 KR KR1020190145646A patent/KR102316186B1/ko active IP Right Grant
-
2023
- 2023-01-31 US US18/103,850 patent/US20230178419A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US20230178419A1 (en) | 2023-06-08 |
CN111199918A (zh) | 2020-05-26 |
TWI804693B (zh) | 2023-06-11 |
KR102316186B1 (ko) | 2021-10-26 |
US20200161171A1 (en) | 2020-05-21 |
KR20200058298A (ko) | 2020-05-27 |
CN111199918B (zh) | 2023-08-15 |
TW202322252A (zh) | 2023-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI804693B (zh) | 用於隔離結構的伸縮襯裡層 | |
TWI688997B (zh) | 閘極電極材料殘留物移除製程 | |
TW202117931A (zh) | 間隙填充沉積製程 | |
US20070000870A1 (en) | Plasma processing method | |
US20230093011A1 (en) | Atomic layer etching of molybdenum | |
JP2016528734A (ja) | エピタキシャル成長に先立って基板表面を予洗浄するための方法及び装置 | |
US11114306B2 (en) | Methods for depositing dielectric material | |
TW202107561A (zh) | 整合半導體處理 | |
US11355350B2 (en) | Etching method, substrate processing apparatus, and substrate processing system | |
US20230298896A1 (en) | Metal-based liner protection for high aspect ratio plasma etch | |
TWI750364B (zh) | 形成鈦矽化物區域之方法 | |
US7517812B2 (en) | Method and system for forming a nitrided germanium-containing layer using plasma processing | |
US7517818B2 (en) | Method for forming a nitrided germanium-containing layer using plasma processing | |
US20220262645A1 (en) | Etching method, substrate processing apparatus, and substrate processing system | |
CN111508831A (zh) | 蚀刻方法、等离子体处理装置和处理系统 | |
US20240136229A1 (en) | Channel uniformity horizontal gate all around device | |
KR20240112205A (ko) | 에칭 방법 및 플라즈마 처리 장치 | |
CN118335603A (zh) | 蚀刻方法及等离子体处理装置 | |
TW202334463A (zh) | 用於光學膜的整合式預清潔沉積系統 | |
CN114334595A (zh) | 蚀刻方法和等离子体处理装置 | |
JP2019062045A (ja) | ボロン系膜の平坦化方法およびボロン系膜の形成方法 |