TW202037770A - Method for determining gap size in manufacturing single-crystal silicon and method for manufacturing single-crystal silicon - Google Patents

Abstract

Disclosed is a method for determining the gap size in a single-crystal silicon manufacturing process in which a large number of silicon wafers having only defect-free regions are obtained, additionally, a method for manufacturing single-crystal silicon. The relationship between the defect distribution of single-crystal silicon and the pulling speed is simulated. Based on those results, the pulling speed of single-crystal silicon having only defect-free regions can be obtained. An interval is based on the numerical value of the simulated defect distribution, the interval of the pull speed obtained from the simulation, and the first relationship with the gap size. A second relationship of the gap size during the production of the single-crystal silicon estimates the range of the pulling speed during the production of single-crystal silicon for evaluation, and determines a gap size that is larger than the estimated pulling speed range.

Description

Method for determining gap size in silicon single crystal manufacturing process and method for manufacturing silicon single crystal

The present invention relates to a method for determining the gap size in the manufacturing process of a silicon single crystal and a method for manufacturing a silicon single crystal.

The silicon wafer used as the substrate of the semiconductor device is generally cut by the silicon single crystal grown by the Tchaikovsky method (hereinafter sometimes referred to as the "CZ method"), and undergoes processes such as grinding and heat treatment. And manufacturing. The defect distribution of silicon single crystals can generally be the distance from the center of the crystal to the outer edge as the horizontal axis. The pulling speed of the silicon single crystal is V, divided by the temperature gradient G in the growth direction of the silicon single crystal shortly after the pulling. The value is represented by the graph on the vertical axis. The temperature gradient G, due to the thermal characteristics of the hot zone structure of the CZ furnace, is generally regarded as constant during the pulling up of the silicon single crystal. Therefore, V/G can be controlled by adjusting the pulling speed V.

In the above defect distribution map, it mainly shows the COP (Crystal Originated Particle) area, OSF (Oxidation induced Stacking Fault) area, Pv area, Pi area, L/D (Large Dislocation: Big difference row) area. COP is an aggregate of atomic voids that should form the crystal lattice when culturing silicon single crystals. The OSF area is adjacent to the COP area, and during high temperature (generally from 1000°C to 1200°C) thermal oxidation treatment, the OSF core will become OSF. The Pv area is adjacent to the OSF area and is a defect-free area where void-type point defects dominate. The Pv region contains oxygen precipitation nuclei in an as-grown state, and oxygen precipitation (BMD) is likely to occur when heat treatment is applied. The Pi region is adjacent to the Pv region, and is a defect-free region where inter-lattice silicon-type point defects dominate. The Pi region contains almost no oxygen precipitation nuclei in the as-grown state, and even if heat treatment is applied, BMD is not prone to occur. The L/D system is an aggregate of inter-lattice silicon that is excessively taken in between the crystal lattices, and is a defect (agglomerate) associated with a shift. The L/D area is adjacent to the Pi area.

In recent years, the demand for silicon wafers that do not have defects in the entirety has increased, and a method of manufacturing silicon single crystals that can obtain such silicon wafers has been studied (see, for example, Patent Document 1). In Patent Document 1, it is disclosed that the OSF region: and the N-region (a defect-free region composed of only the Pv region and the Pi region) located outside of the OSF region, the pulling rate V and the temperature gradient G pulling up the silicon single crystal . [Prior technical literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 11-199386

[The problem to be solved by the invention]

However, with the structure as in Patent Document 1, more or less OSF regions exist in the silicon wafer, and the following narrowly defined silicon single crystals cannot be obtained without defects.

The object of the present invention is to provide a method for determining the gap size in the manufacturing process of silicon single crystals and a method for manufacturing silicon single crystals that can obtain many silicon wafers with defect-free regions. The term "defect-free area" in a broad sense means an area from which an FPD (Flow Pattern Defect) area and an L/D area are removed, and in a narrow sense, it means an area composed of only a Pv area and a Pi area. Similarly, a defect-free silicon wafer in a broad sense means a silicon wafer that does not have FPD (Flow Pattern Defect) regions and L/D regions in the plane, and in a narrow sense it means A silicon wafer composed of only Pv area and Pi area. The so-called silicon wafer with only defect-free regions may be a defect-free silicon wafer in a broad sense or a defect-free silicon crystal in a narrow sense. [Means for solving problems]

The method for determining the gap size of the present invention is characterized in that: in use, it is equipped with: a crucible containing a silicon melt; a silicon single crystal pulling part is pulled up from the silicon melt; and a silicon single crystal being pulled is surrounded. The method for determining the gap size between the lower end of the heat shield and the surface of the molten silicon during the process of manufacturing the silicon single crystal by the pull-up device of the heat shield disposed above the crucible includes implementation: for each of the above The gap size is a process of simulating the relationship between the defect distribution of the silicon single crystal and the pulling rate of the silicon single crystal; based on the above simulation results, the interval of the pulling speed of the silicon single crystal having only defect-free regions is identified Process; the process of digitizing the defect distribution obtained by the above simulation, and identifying the first relationship between the defect distribution value and the interval of the pulling speed obtained by the simulation and the gap size; the silicon single crystal for evaluation manufactured using the pulling device The defect distribution is digitized in the same way as the defect distribution obtained by the above simulation, and the second relationship between the defect distribution value and the gap size in the manufacturing process of the silicon single crystal for evaluation is identified; based on the first relationship and the above The second relationship is a process of estimating the interval of the pulling speed in the manufacturing process of the silicon single crystal for evaluation described above, and determining the gap size larger than the interval of the estimated pulling speed.

The range of the pull-up speed of the silicon single crystal having only defect-free regions (hereinafter sometimes referred to as "defect-free range") varies depending on the gap size. The "defect-free zone" refers to the difference between the upper limit and the lower limit of the pull-up speed of the silicon single crystal in which the silicon wafer obtained from the silicon single crystal becomes a defect-free area. In addition, the term "defect-free area" means either a defect-free area in a broad sense or a defect-free area in a narrow sense as described above. Hereinafter, the present invention will be described as a defect-free area, a non-defective area in a narrow sense. The gap size at which the defect-free interval becomes the largest can be obtained by simulation. Furthermore, simulation, in addition to computer simulation by numerical calculation, also includes simulation by experiment. Applying the obtained gap size to the pull-up device should be the manufacturing condition where the defect-free interval becomes the largest. However, in fact, the thermal environment may be different from the simulation due to deterioration of components in the hot zone. State, and the defect-free interval has not become the largest. At this time, if the pull-up speed is changed during the manufacturing process, the pull-up speed may deviate from the range of the defect-free interval, and a silicon single crystal with defect areas may be produced. In the present invention, the first relationship based on the simulation results and the second relationship based on the defect distribution of the silicon single crystal for evaluation are used to estimate the size of the defect-free interval when the silicon single crystal for evaluation is manufactured, and determine the size of the defect-free interval A gap size larger than the estimated size. Therefore, by using this manufacturing gap size, a silicon single crystal can be manufactured in a state where the defect-free interval is larger than the manufacturing process of the silicon single crystal for evaluation. As a result, even if the pull-up speed changes, the pull-up speed can be suppressed from deviating from the range of the defect-free zone, and more silicon wafers with only defect-free areas can be obtained.

In the method for determining the gap size of the present invention, the radius of the circular defect region and the width of the ring-shaped defect region in the wafer surface obtained from the silicon single crystal, or the single crystal radius direction corresponding to the radius and the width It is better to digitize the above-mentioned defect distribution.

According to the present invention, the defect distribution can be easily quantified based on OSF or oxygen precipitate (BMD) that can be visually confirmed by heat treatment.

In the method for determining the gap size of the present invention, the value of the above-mentioned defect distribution is digitized, and the dimensionless value is preferable.

In the method for determining the gap size of the present invention, the above-mentioned defect distribution is preferably the distribution of the OSF area or the distribution of the Pv area.

According to the present invention, OSF or oxygen precipitates (BMD) that can be visually confirmed by heat treatment can easily determine the gap size that makes the defect-free interval larger than the silicon single crystal manufacturing process for evaluation.

In the method of determining the gap size of the present invention, the above-mentioned defect distribution is digitized as the ratio of the radius of the circular OSF area to the width of the circular OSF area, or the ratio of the radius of the circular Pv area to the width of the circular Pv area Better.

According to the present invention, based on the ratio of the radius of the circular OSF area or the Pv area to the width of the ring-shaped OSF area and the Pv area, or the ratio of the radius of the circular Pv area to the width of the ring-shaped Pv area, the defect distribution value can be easily calculated化.

The method of manufacturing a silicon single crystal of the present invention is characterized in that the silicon single crystal is manufactured using the gap size determined by the method for determining the gap size described above.

According to the present invention, it is possible to manufacture silicon single crystals that can produce many silicon wafers with defect-free regions.

In the method of manufacturing a silicon single crystal of the present invention, in the method for determining the gap size, it is preferable that the gap size is determined so that the range of the pull-up speed is maximized.

According to the present invention, the allowable value of the change in the pulling speed can be maximized, and many silicon wafers with only defect-free areas can be obtained.

[Related Technology of the Invention] First, the related technology of the present invention will be explained based on the drawings. As shown in FIG. 1, the pulling device 1 of the silicon single crystal SM is a device using the CZ method (Czochralski method: Czochralski method), and includes a device host 2. The device main body 2 is provided with: a cavity 21; a crucible 22 arranged in the cavity 21; a heater 23 for heating the crucible 22; a pull-up part 24; a heat shield 25; a heat insulating material 26; and a crucible Drive unit 27. Furthermore, the lifting device 1, as shown by the two-dot dashed line, is a device used in the MCZ (Magnetic field applied Czochralski) method, and may also have a pair of clamps on the outside of the cavity 21 The electromagnetic coil 28 of the crucible 22 is configured.

In the upper part of the cavity 21, a gas introduction port 21A for introducing an inert gas such as Ar gas into the cavity 21 is provided. In the lower part of the cavity 21, a gas exhaust port 21B for discharging the gas in the cavity 21 is provided. A heat insulating material 26 is provided on the inner surface of the cavity 21.

The crucible 22 melts silicon as a silicon melt M. The crucible 22 includes: a quartz crucible 221; and a graphite crucible 222 that houses the quartz crucible 221. The quartz crucible 221 is exchanged after each growth of 1 or plural silicon single crystal SM. On the other hand, the graphite crucible 222 is not exchanged every time one silicon single crystal SM is produced. It is exchanged when it is considered that the quartz crucible 221 cannot be properly supported.

The heater 23 is arranged around the crucible 22 to melt the silicon in the crucible 22. Furthermore, under the crucible 22, a bottom heater 231 as shown by the two-dot dashed line may be further provided. The pull-up section 24 includes a cable 241 to which the seed crystal SC is attached at one end, and a pull-up driving section 242 for lifting and rotating the cable 241. The heat shield 25 is provided so as to surround the silicon single crystal SM, and shields radiant heat radiated upward from the heater 23. The crucible driving unit 27 includes a support shaft 271 that supports the graphite crucible 222 from below, and rotates and raises and lowers the crucible 22 at a predetermined speed. Furthermore, in the hot zone of the pulling device 1, the cavity 21, the crucible 22, the heater 23, the cable 241, the heat shield 25, the heat insulating material 26, the support shaft 271, the silicon melt M, the silicon monolith Crystallization SM.

[Embodiment] [ Method for Manufacturing Silicon Single Crystal] Next, a method for manufacturing a silicon single crystal SM according to an embodiment of the present invention will be described. In addition, in this embodiment, although the case of manufacturing a silicon single crystal SM with a diameter of 300 mm in the cylindrical portion after cylindrical polishing is illustrated, the diameter after cylindrical polishing may be 200 mm, 450 mm, or other sizes. In addition, dopants for adjusting the resistivity may be added to the silicon melt M, or not.

The manufacturing method of silicon single crystal SM is as shown in FIG. 2, the process of implementing the method of determining the gap size in the manufacturing process of silicon single crystal SM (step S1), and the manufacturing gap size determined by the determination method is applied Process of silicon single crystal SM for products (Step S2: manufacturing process). Hereinafter, each step will be described in detail.

In the process of implementing the method of determining the gap size, first, the size of the gap GP between the lower end of each heat shield 25 and the surface of the silicon melt M (hereinafter, the size of the gap GP is sometimes referred to as "gap size"), Simulate the relationship between the defect distribution of the silicon single crystal SM and the pulling speed of the silicon single crystal SM (step S11: simulation process). Furthermore, the so-called gap size refers to the distance between the lower end of the heat shield 25 and the surface of the silicon melt M during the manufacturing process of the silicon single crystal SM. The simulation process is performed on at least the columnar part SM1 of the silicon single crystal SM. Due to the influence of changes in the thermal history of the silicon single crystal SM during pulling, even if the gap size is the same, the defect distribution will be different according to the position of the columnar portion SM1 in the longitudinal direction. Therefore, it is better to perform the simulation process at multiple locations along the longitudinal direction of the columnar portion SM1. In the present embodiment, the simulation process is performed on the region that divides the columnar portion SM1 into three equal parts in the longitudinal direction. Among the three equally divided areas, the upper end area in the pulling direction is called the top area, the center area is called the middle area, and the lower end area is called the bottom area. Through this simulation process, a defect distribution in which the distance from the center of the silicon single crystal SM is on the horizontal axis and the pull-up speed V is on the vertical axis is obtained. An example of a simulation result in which only the gap size is different in the columnar portion SM1 is shown in FIGS. 3 and 4. Furthermore, in FIGS. 3 to 5, the left end of the horizontal axis indicates the center position of the silicon single crystal SM, and the right end indicates the outer edge position. In addition, FIGS. 3 to 7 are diagrams related to the middle region of the silicon single crystal SM. The simulation process can also be simulated experimentally in addition to computer simulation by numerical calculation. Computer simulation by numerical calculation that can save the cost or time spent in simulation is better.

Next, based on the results of the simulation process, the non-defective section shown in FIGS. 3 and 4 is identified (step S12: non-defective section identification step). The so-called defect-free zone means the zone where the pulling speed of the silicon single crystal SM with only defect-free regions can be obtained. The defect-free area is the range from the lowest position of the OSF-Pv boundary between the OSF area and the non-defective area to the highest position of the Pi-L/D boundary between the defect-free area and the L/D area.

After that, the defect distribution obtained in the simulation process is digitized, and the value of the defect distribution, the defect-free interval identified in the defect-free area identification step, and the first relationship of the gap size are identified (step S13: first relationship identification step). In the present embodiment, first, the gap size at which the defect-free interval becomes the largest is identified (hereinafter, the gap size at which the defect-free interval becomes the largest may be referred to as "tentative gap size"). The defect-free section changes according to the gap size. For example, when a graph with the gap size on the horizontal axis and the size of the defect-free section on the vertical axis is created, it will be a mountain-shaped graph. That is, there is only one gap size at which the defect-free interval becomes the largest. Therefore, based on the results of multiple simulations in which only the gap size is changed at the same place, the provisional gap size is identified.

Next, for example, the size of the gap shown in Figure 5, a gap based on the defect size distribution tentative track the status of OSF occurrence region when OSF region is present at a speed V ₁ of the pulled silicon single crystal SM. In the silicon wafer obtained from the silicon single crystal SM, there is a disk-shaped (circular-shaped) OSF region including the center. Outside the disk-shaped OSF area, there is a ring-shaped OSF area with a defect-free area therebetween. Next, the radius of the disk-shaped OSF region and the width of the ring-shaped OSF region are obtained as the disk radius and the ring width, respectively. Furthermore, find the disk radius and ring width when the silicon single crystal SM is manufactured at other pulling speeds in the OSF region. That is, the defect distribution obtained in the simulation process is digitized.

Furthermore, based on the defect distribution when the gap size is 1 mm larger than the tentative gap size and the defect distribution when the gap size is 1 mm smaller than the tentative gap size, the radius of the disk and the ring width when being pulled up at each plural pulling speed are obtained. Then, based on the defect distribution shown in FIG. 5, a comparison data was created as shown in FIG. 6, with the disk radius as the horizontal axis, and the disk-to-ring ratio divided by the disk radius quotient as the vertical axis. This comparison data shows the numerical value of the simulated defect distribution (disk radius, disk ring ratio), the simulated defect-free interval (the largest defect-free interval), and the gap size (tentative gap size, tentative gap) Size ±1mm) the first relationship. The preparation of the comparative data is performed on the top, middle, and bottom regions. The production of comparative data can be done on a computer or by an operator.

Next, the gap size of the pull-up device 1 is set to a tentative gap size, and a silicon single crystal SM for evaluation is manufactured (step S14: single crystal manufacturing process for evaluation). In the single crystal manufacturing process for evaluation, when manufacturing the top area, middle area, and bottom area, set the gap size to the tentative gap size corresponding to each area, and set the pulling speed in each area. There are ring-shaped and disc-shaped OSFs. The speed of the area is carried out. The speed at which the OSF region exists in the shape of a ring and disk can be set as shown in Figure 5, for example, based on the defect distribution of the gap size as a tentative gap size, and set to the speed V ₁ where the OSF region exists, or based on past manufacturing Actual result setting. In this embodiment, a silicon single crystal SM for evaluation in which there are a plurality of ring-shaped and disc-shaped OSF regions is produced.

Next, the defect distribution of the silicon single crystal for evaluation is digitized by the same method as the defect distribution obtained by simulation, and the value of the defect distribution is identified and the second relationship between the value of the defect distribution and the gap size in the manufacturing process of the silicon single crystal for evaluation (step S15: The second relationship identification process). In the present embodiment, first, a silicon wafer is taken from the columnar portion SM1 of the silicon single crystal SM for evaluation, and a process of making the OSF region appear is performed. As this development treatment, after performing a heat treatment in an oxygen atmosphere at 1000°C for 3 hours, a heat treatment in an oxygen atmosphere at 1150°C for 2 hours can be exemplified. Then, the ring width and disk radius of the OSF area that appeared were measured. The above processing is performed on the silicon wafer obtained from each area of the plural silicon single crystal SM for evaluation. In addition, the number of silicon wafers obtained from each region may be one or plural. In addition, it is also possible to manufacture only one silicon single crystal SM for evaluation and obtain plural silicon wafers from the single crystal SM. Then, the relationship between the disk radius and the disk ring ratio based on the measurement result of each silicon wafer is identified. That is, the second relationship between the numerical value (disk radius, disk ring ratio) of the defect distribution of the silicon single crystal SM for evaluation and the gap size in the manufacturing process of the silicon single crystal SM for evaluation was identified.

Then, based on the first relationship and the second relationship, the defect-free interval in the manufacturing process of the silicon single crystal SM for evaluation is estimated, and the manufacturing gap size larger than the estimated defect-free interval is determined (step S16: manufacturing gap size determination process) . In this embodiment, first, the first relationship shown in the comparison data is compared with the second relationship, and it is determined whether the defect-free interval is in the largest state during the manufacturing process of the silicon single crystal SM for evaluation. The two compared are data based on the appearance of OSF, and therefore correspond to the simulation results and the defect distribution of the silicon single crystal SM for evaluation.

For example, as shown in FIG. 7, on the comparison data of FIG. 6, the measurement results (manufacturing actual results (second relationship)) in the OSF area of each silicon wafer are plotted. When the silicon single crystal SM is manufactured under the same manufacturing conditions, the measurement results of the OSF area of the silicon wafers obtained from these should be the same, but in fact, due to measurement errors or dispersion in the pulling speed, as shown in Figure 7 Sometimes different. Then, when the measurement result is almost the same as the comparison data for the provisional gap size, it is estimated that the defect-free interval is the largest, and the provisional gap size is determined as the manufacturing gap size. On the other hand, when the measurement result deviates from the comparative data by a predetermined amount, it is concluded that the defect-free interval is not in the maximum state, and a size other than the provisional gap size is determined as the manufacturing gap size.

For example, find the reference approximation line L _S of the comparison data for the tentative gap size, the first comparison approximation line L ₁ of the comparison data when the tentative gap size is 1 mm larger, and the second comparison of the comparison data when the tentative gap size is 1 mm smaller. The approximate line L ₂ , the actual result of the measurement result of the silicon wafer approximates the line N. Then, the manufacturing gap size is determined based on the distance between the approximate lines L _S , L ₁ , L ₂ and the actual result approximate line N.

In the result shown in FIG. 7, the actual result approximation line N is located approximately in the middle between the reference approximation line L _S and the first comparison approximation line L ₁ . At this time, the manufacturing conditions when the tentative gap size is applied to the elevating device 1 can be estimated to be equivalent to the manufacturing conditions when a size 0.5 mm larger than the tentative gap size is simulated and applied. Based on the results of this fracture, it can be considered that the manufacturing conditions when a size smaller than the tentative gap size is applied by 0.5 mm are equivalent to the manufacturing conditions when the tentative gap size is simulated. Therefore, a size smaller than the tentative gap size by 0.5 mm is determined as the manufacturing gap size. In addition, when the actual result approximation line N is located between the reference approximation line L _S and the second comparison approximation line L ₂ , the length dimension corresponding to the distance between the actual result approximation line N and the reference approximation line L _S , which is larger than the tentative gap size, is determined as the manufacturing Gap size. For example, when the position of the reference approximation line L _S is "0" and the position of the second comparison approximation line L ₂ is "1", when the actual result approximation line N is at the position of "0.3", it is determined to be 0.3 larger than the temporary gap size The size of mm is used as the manufacturing gap size.

On the other hand, when the actual result approximation line N is approximately the same as the reference approximation line Ls, the manufacturing conditions when the provisional gap size is applied to the lifting device 1 are estimated to be equivalent to the manufacturing conditions when the provisional gap size is simulated and the provisional gap size is determined. As the manufacturing gap size. As described above, the actual result approximation line N is aligned with the reference approximation line L _S to determine the manufacturing gap size, which becomes a manufacturing condition that maximizes the defect-free interval. This manufacturing gap size determination process is performed on the top area, the middle area, and the bottom area. The process of determining the size of the manufacturing gap can be performed by a computer or by an operator.

Furthermore, in the above processing, the manufacturing gap size is determined based on the existence of the ring-shaped and disc-shaped OSF area, but it can also be determined based on the existence of the ring-shaped and disc-shaped Pv area as shown in Figure 8. Manufacturing gap size. At this time, it is only necessary to simulate or evaluate the pull-up speed during the manufacturing process of the silicon single crystal SM for evaluation, and set the speed V ₂ at which the ring-shaped and disc-shaped Pv regions can be generated. As a process for developing the Pv region, after performing a heat treatment in an oxygen atmosphere at 780°C for 3 hours, a heat treatment in an oxygen atmosphere at 1000°C for 16 hours can be exemplified.

After that, the manufacturing process (step S2) is performed. The manufacturing process uses the manufacturing gap size determined in the process of step S1 in each manufacturing process of the top region, the middle region, and the bottom region to manufacture the silicon single crystal SM for the product.

[Effects of the implementation form] According to the above-mentioned embodiment, in the manufacturing gap size determination step, the size of the defect-free interval when manufacturing the silicon single crystal SM for evaluation is estimated, and the gap size that increases the defect-free interval is determined as the manufacturing gap size based on the estimated size. By using this manufacturing gap size in the manufacturing process, it is possible to manufacture silicon single crystal SM for products in a state where the defect-free interval is larger than the manufacturing process of silicon single crystal SM for evaluation. Therefore, even if the pull-up speed changes, it is possible to suppress the pull-up speed from deviating from the range of the defect-free interval, and more silicon wafers with only defect-free areas can be obtained. Particularly in this embodiment, by using the manufacturing gap size that maximizes the defect-free interval in manufacturing, the allowable value of the change in the pulling speed can be maximized, and more silicon wafers with only defect-free areas can be obtained. .

In the manufacturing gap size determination step, the manufacturing gap size can be easily determined based on the actual results of the approximate line N relative to the reference approximate line L _S , the first comparative approximate line L ₁ , and the second comparative approximate line L ₂ .

[Modifications] In addition, the present invention is not limited to the embodiment described above, and various improvements, design changes, etc. are possible without departing from the gist of the present invention. For example, the method of determining the gap size in the manufacturing process of silicon single crystal and the manufacturing method are performed on the top, middle, and bottom regions of the columnar portion SM1, but it can also be performed on either or two regions. It is also possible to divide the columnar portion SM1 into two or four or more regions in the longitudinal direction.

In the manufacturing gap size determination step, the manufacturing gap size is determined based on the approximate lines L _S , L ₁ , L ₂ and the distance from the actual result approximate line N, but the first and second comparison approximate lines L ₁ , L ₂ may not be required , Only based on the comparison between the reference approximate line Ls and the actual result approximate line N, the manufacturing gap size is determined. In the manufacturing gap size determination process, based on the defect distribution when the gap size is 1mm larger than the tentative gap size, the first comparative approximation line L _{1 is obtained} . However, it can also be based on 0.5mm or 2mm larger than the tentative gap size. For other sizes Defect distribution, find the first comparison approximate line L ₁ . The second comparison approximation line L ₂ can be obtained in the same way. In the manufacturing gap size determination process, plus the first and second comparative approximation lines L ₁ and L ₂ , the third and fourth can also be obtained based on the defect distribution when the gap size is larger than the provisional gap size, for example, 2 mm and 2 mm smaller. The comparative approximation line is used to determine the manufacturing gap size using the third and fourth comparative approximation lines. In the manufacturing gap size determination step, the approximate lines Ls, L ₁ , L ₂ , and N may not be obtained, and only the drawing data used to create the approximate lines Ls, L ₁ , L ₂ , and N may be compared to determine the manufacturing gap size. The manufacturing gap size may not be the gap size at which the defect-free interval becomes the largest as long as the defect-free interval becomes larger than the manufacturing process of the silicon single crystal SM for evaluation. For example, when the result shown in FIG. 7 is obtained, although a size smaller than the tentative gap size by 0.5 mm is determined as the manufacturing gap size, a size smaller than 0.3 mm can also be determined as the manufacturing gap size.

In the manufacturing gap size determination process, the manufacturing gap size is determined based on the comparison data with the disk radius as the horizontal axis and the ring width divided by the disk radius quotient as the vertical axis. However, other indicators can also be used as the horizontal axis. Axis and vertical axis indicators. The combination of the indicators on the horizontal axis and the vertical axis can exemplify the radius of the disk and the width of the ring. [Example]

Next, the present invention will be explained in more detail with examples and comparative examples, but the present invention is not limited to these examples.

[Experiment 1] Using the manufacturing gap size determined based on FIG. 7 of the above-mentioned embodiment, a silicon single crystal SM for evaluation in which a plurality of ring-shaped and disk-shaped OSF regions exist was manufactured. Then, the disk radii and disk ratios of the plural wafers obtained from the silicon single crystal SM for evaluation were obtained, and these relationships were plotted as a graph shown in FIG. 6. The results are shown in Fig. 9.

As shown in Fig. 9, it is confirmed that the actual result of the measurement result of the evaluation silicon single crystal SM manufactured with the manufacturing gap size approximates the line N ₁ , which is closer to the line N than the actual result of the evaluation silicon single crystal SM manufactured with the provisional gap size. It is very close to the reference approximate line Ls. This confirms that by using the manufacturing gap size obtained by the method for determining the gap size in the manufacturing process of the silicon single crystal SM in the manufacturing process, it is possible to manufacture the silicon single crystal SM for manufacturing products in a state where the defect-free interval is enlarged.

[Experiment 2] [Experimental example 1] ｛Comparative example 1} Perform the processing of steps S11 to S12 on the premise that the hot zone is the A-type pull-up device 1, appraise the tentative gap size for each top area, middle area, and bottom area, and manufacture the comparative example 1 based on the evaluated tentative gap size Silicon single crystal SM. As the pulling speed of the silicon single crystal SM of Comparative Example 1, the median of the defect-free interval to which the simulation result of the tentative gap size is applied is applied. After that, in the silicon single crystal SM of Comparative Example 1, the product area of the silicon wafer (product wafer) having only defect-free areas was identified. At this time, silicon wafers are obtained from multiple positions in the longitudinal direction of the columnar portion SM1, the product wafer sandwiching area is used as the product area, and the silicon wafer (defective wafer) of the OSF area with the defective area is packaged The clamped area is regarded as a defective product area. Then, the value obtained by dividing the weight of the product area by the weight quotient of the silicon raw material charged into the crucible 22 was obtained as the yield of Comparative Example 1.

｛Example 1} Based on the appearance of the OSF of the defective wafer obtained from the silicon single crystal SM of Comparative Example 1, the processing of steps S13 to S14 is performed to determine the manufacturing gap size of the area of the defective wafer. Then, the pull-up device 1 with the A-type hot zone was used to manufacture the silicon single crystal SM of Example 1 to produce the gap size. As the pulling rate of the silicon single crystal SM of Example 1, the same rate as that of Comparative Example 1 was applied. After that, the product region of the silicon single crystal SM of Example 1 was identified, and the yield of Example 1 was determined in the same manner as in Comparative Example 1.

[Experimental example 2] ｛Comparative Example 2, Example 2} Instead of using the A-type elevating device 1 for the hot zone, the B-type elevating device 1 was used, and the same treatment as in Comparative Example 1 and Example 1 was performed, respectively, and the yields of Comparative Example 2 and Example 2 were determined.

[Evaluation] The value obtained by subtracting the yield rate of Comparative Example 1 from the yield rate of Example 1 is obtained as the yield effect of Experimental Example 1, and the value obtained by subtracting the yield rate of Comparative Example 2 from the yield rate of Experimental Example 2 is taken as The yield of Example 2 was obtained. The results are shown in Fig. 10.

As shown in FIG. 10, in any of Experimental Examples 1 and 2, the yield effect was confirmed to be 1% or more. Thus, it was confirmed that the manufacturing gap size obtained by using the method for determining the gap size in the manufacturing process of the silicon single crystal SM in the manufacturing process can obtain a lot of product wafers.

1: Lifting device 22: Crucible 24: pull part 25: Heat shielding body GP: gap M: Silicon melt SM: Silicon single crystal

[Fig. 1] is a schematic diagram of the related technology of the present invention and the pulling device of an embodiment. [Fig. 2] is a flowchart of a method of manufacturing a silicon single crystal in the above-mentioned embodiment. [Fig. 3] is a schematic diagram showing an example of the relationship between the pull-up speed of a silicon single crystal and the defect distribution. [Figure 4] is a schematic diagram showing an example of the relationship between the pull-up speed of a silicon single crystal and the defect distribution. [Fig. 5] is an explanatory diagram showing the relationship between the pull-up speed and the existence of ring-shaped and disk-shaped OSF regions. [Figure 6] is a graph showing the relationship between the disk radius and the disk ring ratio in the OSF area based on the simulation results. [Figure 7] is a graph showing the relationship between the disk radius in the OSF area and the disk ring ratio based on the simulation results and the actual results of the production of silicon single crystals for evaluation using the provisional gap size. [Fig. 8] is an explanatory diagram showing the relationship between the pull-up speed and the existence of the ring-shaped and disc-shaped Pv regions in a modification of the present invention. [Figure 9] shows the results of Experiment 1 in the embodiment of the present invention, based on the simulation results and the actual results of the production of the silicon single crystal for evaluation using the production gap size, the relationship between the disk radius of the OSF area and the disk ring ratio Chart. [FIG. 10] is a graph showing the results of Experiment 2 of the above-mentioned Example, and the yield effects of Experiment Examples 1 and 2.

Claims (7)

A method for determining the gap size, characterized in that: in use, it is equipped with: a crucible containing silicon melt; a pulling part for pulling up a silicon single crystal from the silicon melt; and disposing a silicon single crystal that is being pulled up In the process of manufacturing silicon single crystal by the pulling device of the heat shield above the crucible, the method for determining the gap size between the lower end of the heat shield and the surface of the silicon melt includes implementing: For each of the above gap sizes, a process of simulating the relationship between the defect distribution of the silicon single crystal and the pulling speed of the silicon single crystal; Based on the above-mentioned simulation results, identify the process that can obtain the range of the pull-up speed of the above-mentioned silicon single crystal with only defect-free regions; The step of digitizing the defect distribution obtained by the above simulation, and identifying the first relationship between the defect distribution value and the interval of the pulling speed obtained by the above simulation and the gap size; The defect distribution of the silicon single crystal for evaluation manufactured using the above-mentioned pull-up device was digitized in the same way as the defect distribution obtained by the above simulation, and the defect distribution value and the gap size during the manufacturing process of the silicon single crystal for evaluation were identified The second relationship process; Based on the above-mentioned first relationship and the above-mentioned second relationship, the step of estimating the interval of the pulling-up speed in the manufacturing process of the silicon single crystal for evaluation, and determining the gap size larger than the interval of the estimated pulling-up speed. The method for determining the gap size as described in item 1 of the scope of patent application, where The numerical value of the defect distribution is performed by the radius of the circular defect region and the width of the annular defect region in the wafer surface obtained from the silicon single crystal, or the defect distribution in the single crystal radius direction corresponding to the radius and the width化. The method for determining the gap size as described in item 2 of the scope of patent application, where The value obtained by digitizing the above-mentioned defect distribution is a dimensionless value. For the method for determining the gap size described in any one of items 1 to 3 in the scope of the patent application, the above-mentioned defect distribution is the distribution of the OSF area or the distribution of the Pv area. The method for determining the gap size as described in item 4 of the scope of patent application, wherein the value of the above-mentioned defect distribution is digitized as the ratio of the radius of the circular OSF area to the width of the annular OSF area, or the radius of the circular Pv area and The width ratio of the ring-shaped Pv area. A method for manufacturing a silicon single crystal is characterized in that the silicon single crystal is manufactured using the gap size determined by the method for determining the gap size described in any one of items 1 to 5 in the scope of the patent application. The method for manufacturing a silicon single crystal as described in the scope of patent application, wherein the method for determining the gap size is to determine the gap size so that the range of the pulling speed becomes the largest.

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