KR102353877B1 - Method of determining gap size in manufacturing silicon single crystal, and method of manufacturing silicon single crystal - Google Patents

Abstract

The method for determining the gap size of a silicon single crystal simulates the relationship between the defect distribution and the pulling rate of the silicon single crystal, and specifies a pulling rate margin at which a silicon single crystal having only a defect-free region is obtained based on the simulation result, and the defect distribution obtained in the simulation In the first relationship between the numerical value of , the pulling rate margin and the gap size obtained in the simulation, and the second relationship between the numerical value of the defect distribution of the silicon single crystal for evaluation and the gap size during the production of the silicon single crystal for evaluation Based on the estimate, the margin of the pulling rate at the time of manufacturing the silicon single crystal for evaluation is estimated, and a gap size that is larger than the estimated pulling rate margin is determined.

Description

A method for determining a gap size at the time of manufacturing a silicon single crystal, and a method for manufacturing a silicon single crystal TECHNICAL FIELD

The present invention relates to a method for determining a gap size in the production of a silicon single crystal and a method for producing a silicon single crystal.

A silicon wafer used as a substrate for a semiconductor device is generally cut out from a silicon single crystal grown by the Czochralski method (hereinafter, sometimes referred to as "CZ method"), and is manufactured through processes such as polishing and heat treatment. .

In general, the defect distribution of a silicon single crystal is defined by the horizontal axis being the distance from the crystal center to the outer edge, and the value obtained by dividing the pulling rate V of the silicon single crystal by the temperature gradient G in the growth direction of the silicon single crystal immediately after pulling up is the vertical axis. It can be represented in one drawing. The temperature gradient G is considered to be substantially constant during the pulling of the silicon single crystal due to the thermal characteristics of the hot zone structure of the CZ furnace. For this reason, V/G can be controlled by adjusting the pulling-up speed V.

In the defect distribution diagram as described above, a COP (Crystal Originated Particle) region, an Oxidation induced Stacking Fault (OSF) region, a Pv region, a Pi region, and a L/D (Large Dislocation) region appear mainly.

COP is an agglomerate of vacancies lacking atoms that should constitute a crystal lattice when growing a silicon single crystal.

The OSF region is adjacent to the COP region, and when thermal oxidation treatment is performed at a high temperature (generally from 1000°C to 1200°C), the OSF nuclei become present as OSF.

The Pv region is adjacent to the OSF region and is a defect-free region in which vacancy point defects predominate. The Pv region contains oxygen precipitation nuclei in an as-grown state, and when heat treatment is performed, oxygen precipitates (BMD) are likely to occur.

The Pi region is adjacent to the Pv region and is a defect-free region in which interstitial silicon-type point defects predominate. The Pi region is in an as-grown state and contains almost no oxygen precipitation nuclei, so it is difficult to generate BMD even if heat treatment is performed.

L/D is an aggregate of interstitial silicon excessively blown between crystal lattices, and is a defect accompanying dislocations (dislocation clusters). The L/D region is adjacent to the Pi region.

In recent years, the demand for a silicon wafer free from defects on the entire surface has been increasing, and a method for producing a silicon single crystal capable of obtaining such a silicon wafer has been studied (for example, Document 1: Japanese Patent Application Laid-Open No. Hei 11- 199386).

Document 1 discloses pulling a silicon single crystal at a pulling rate V or a temperature gradient G in a range including an OSF region and an N-region (a defect-free region consisting only of a Pv region and a Pi region) located outside the OSF region. have.

However, in the structure as in Document 1, there are quite a few OSF regions in the silicon wafer, and a defect-free silicon single crystal in the narrow sense described below cannot be obtained.

Japanese Laid-Open Patent Publication No. 11-199386

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for determining a gap size in production of a silicon single crystal capable of obtaining a large number of silicon wafers having only defect-free regions, and a method for producing a silicon single crystal.

In a broad sense, the defect-free region is a region excluding a flow pattern defect (FPD) region and an L/D region, and in a narrow sense, it means a region composed of only a Pv region and a Pi region. Similarly, a defect-free silicon wafer means a silicon wafer in which FPD (Flow Pattern Defect) regions and L/D regions do not exist in a plane in a broad sense, and in a narrow sense, only Pv region and Pi region It means a silicon wafer to be constructed. The silicon wafer in which only the defect-free region exists may be either a defect-free silicon wafer in a broad sense or a defect-free silicon wafer in a narrow sense.

The gap size determination method of the present invention includes a crucible for accommodating a silicon melt, a pulling part for pulling a silicon single crystal from the silicon melt, and a pulling with a heat shield disposed above the crucible so as to surround the silicon single crystal during pulling up A method for determining the gap size between the lower end of the heat shield and the surface of the silicon melt in the production of a silicon single crystal using an apparatus, wherein the relationship between the defect distribution of the silicon single crystal and the pulling rate of the silicon single crystal is simulated for each gap size a step of specifying a pulling rate margin at which the silicon single crystal having only a defect-free region is obtained, based on the results of the simulation; digitizing the defect distribution obtained in the simulation, the value of the defect distribution and the simulation The step of specifying the first relationship between the pulling rate margin and the gap size obtained in , and numerically quantifying the defect distribution of the silicon single crystal for evaluation manufactured using the pulling apparatus in the same way as the defect distribution obtained in the simulation, A step of specifying a second relationship between the value of the defect distribution and the gap size in the production of the silicon single crystal for evaluation, and the production of the silicon single crystal for evaluation based on the first relationship and the second relationship It is characterized by implementing the process of estimating the margin of the pulling-up speed at the time, and determining the said gap size which becomes larger than the margin of this estimated pulling-up speed, It is characterized by the above-mentioned.

The margin of the pulling rate at which a silicon single crystal having only a defect-free region is obtained (hereinafter, sometimes referred to as a "defect-free margin") changes according to the gap size. The defect-free margin means the difference between the upper limit and the lower limit of the silicon single crystal pulling rate in which the entire silicon wafer obtained from the silicon single crystal becomes a defect-free region.

In addition, as mentioned above, the defect-free area|region may be either a defect-free area|region in a broad sense, or a defect-free area|region in a narrow meaning. Hereinafter, this invention is demonstrated by making a defect-free area|region a defect-free area|region in the narrow meaning.

The gap size at which the defect-free margin becomes the largest can be calculated|required by simulation. In addition, simulation includes simulation by experiment in addition to computer simulation by numerical calculation.

If the obtained gap size is applied to a pulling device, it should be a manufacturing condition that produces the largest defect-free margin. There are cases where this is not the largest. In this case, if the pulling rate changes during manufacture, the pulling rate will fall outside the range of the defect-free margin, and there is a fear that a silicon single crystal having a defective region may be manufactured.

In the present invention, the size of the defect-free margin when the silicon single crystal for evaluation is manufactured using the first relationship based on the simulation result and the second relationship based on the defect distribution of the silicon single crystal for evaluation is estimated, , determines the gap size that makes the defect-free margin larger than the estimated size. Therefore, by using this production gap size, it is possible to manufacture a silicon single crystal in a state where the defect-free margin is larger than that at the time of production of the silicon single crystal for evaluation. As a result, even if a pulling speed|rate changes, it can suppress that a pulling speed|rate becomes out of the range of a defect-free margin, and it can obtain many silicon wafers in which only a defect-free area|region exists.

In the gap size determination method of the present invention, the radius of the circular defect region and the width of the ring-shaped defect region in the wafer surface obtained from the silicon single crystal, or the defect distribution in the single crystal radial direction corresponding to the radius and the width , it is preferable that the digitization of the defect distribution be performed.

According to the present invention, the defect distribution can be easily quantified based on OSF and oxygen precipitates (BMD) that can be visually confirmed by heat treatment.

In the gap size determination method of this invention, it is preferable that the value which digitized the said defect distribution is a dimensionless value.

In the gap size determination method of this invention, it is preferable that the said defect distribution is distribution of OSF area|region or distribution of Pv area|region.

According to the present invention, based on OSF and oxygen precipitates (BMD) that can be visually confirmed by heat treatment, it is possible to easily determine a gap size that increases the defect-free margin compared to the time of manufacturing a silicon single crystal for evaluation.

In the gap size determination method of the present invention, the numerical value of the defect distribution is the ratio of the radius of the circular OSF region to the width of the ring-shaped OSF region, or the radius of the circular Pv region and the width of the ring-shaped Pv region It is preferable that the ratio of

According to the present invention, the defect distribution can be easily quantified based on the ratio of the radius of the circular OSF region to the width of the ring-shaped OSF region, or the ratio of the radius of the circular Pv region to the width of the ring-shaped Pv region. have.

The manufacturing method of a silicon single crystal of this invention is characterized by manufacturing a silicon single crystal using the gap size determined by the above-mentioned gap size determination method.

ADVANTAGE OF THE INVENTION According to this invention, a silicon single crystal which can obtain many silicon wafers in which only a defect-free area|region exists can be manufactured.

In the method of manufacturing a silicon single crystal of the present invention, in the method for determining the gap size, it is preferable that the gap size is determined so that the margin of the pulling rate is greatest.

ADVANTAGE OF THE INVENTION According to this invention, the change permissible value of a pulling speed|rate can be maximized, and many silicon wafers in which only a defect-free area|region exists can be obtained.

1 is a schematic diagram of a pulling device according to a related art and an embodiment of the present invention.
Fig. 2 is a flowchart of a method for manufacturing a silicon single crystal according to the embodiment.
3 is a schematic diagram showing an example of a relationship between a pulling rate of a silicon single crystal and a defect distribution.
4 is a schematic diagram showing an example of a relationship between a pulling rate of a silicon single crystal and a defect distribution.
Fig. 5 is an explanatory diagram showing the relationship between the pulling speed and the existence of ring-shaped and disk-shaped OSF regions.
Fig. 6 is a graph showing the relationship between the disk radius of the OSF area and the disk ring ratio based on the simulation result.
7 is a graph showing the relationship between the disk radius and the disk ring ratio of the OSF region based on the simulation results and the production performance of a silicon single crystal for evaluation using the temporary gap size.
Fig. 8 is an explanatory diagram showing the relationship between the pulling speed and the presence of ring-shaped and disk-shaped Pv regions in a modified example of the present invention.
Fig. 9 is a result of Experiment 1 in the Example of the present invention, showing the relationship between the disk radius and the disk ring ratio of the OSF region based on the production performance of a silicon single crystal for evaluation using a simulation result and a production gap size; It is a graph.
Fig. 10 is a graph showing the yield effect of Experimental Examples 1 and 2 as a result of Experiment 2 in the above Example.

(Embodiment of the invention)

(Related art of the present invention)

First, the related technology of the present invention will be described with reference to the drawings.

As shown in FIG. 1, the pulling apparatus 1 of silicon single crystal SM is an apparatus used for the CZ method (Czochralski method), and is provided with the apparatus main body 2 .

The apparatus main body 2 includes a chamber 21 , a crucible 22 disposed in the chamber 21 , a heater 23 heating the crucible 22 , a pulling part 24 , and a heat shield. 25 , a heat insulating material 26 , and a crucible driving unit 27 are provided.

In addition, the pulling apparatus 1 is an apparatus used for the MCZ (Magnetic field applied Czochralski) method, as shown by the dashed-dotted line, It is a pair arrange|positioned across the crucible 22 in the outer side of the chamber 21. You may have the electromagnetic coil 28 of

A gas introduction port 21A for introducing an inert gas such as Ar gas into the chamber 21 is formed in the upper portion of the chamber 21 . A gas exhaust port 21B for discharging gas in the chamber 21 is formed at a lower portion of the chamber 21 . A heat insulating material 26 is formed on the inner surface of the chamber 21 .

The crucible 22 melts silicon to make a silicon melt M. The crucible 22 includes a quartz crucible 221 and a graphite crucible 222 accommodating the quartz crucible 221 . The quartz crucible 221 is replaced every time one or a plurality of silicon single crystals SM are grown. On the other hand, the graphite crucible 222 is not replaced every time a single silicon single crystal SM is manufactured, but is replaced when it is considered that the quartz crucible 221 cannot be properly supported.

The heater 23 is disposed around the crucible 22 , and melts silicon in the crucible 22 . Moreover, below the crucible 22, you may further provide the bottom heater 231 as shown by the double-dotted line.

The pulling unit 24 includes a cable 241 to which a seed crystal SC is attached at one end, and a pulling driving unit 242 for raising/lowering and rotating the cable 241 .

The heat shield 25 is formed to surround the silicon single crystal SM, and blocks radiant heat radiated upward from the heater 23 .

The crucible driving unit 27 includes a support shaft 271 for supporting the graphite crucible 222 from below, and rotates and elevates the crucible 22 at a predetermined speed.

In addition, the hot zone in the pulling apparatus 1 includes a chamber 21 , a crucible 22 , a heater 23 , a cable 241 , a heat shield 25 , a heat insulating material 26 , and a support shaft 271 . , silicon melt (M), silicon single crystal (SM), and the like.

[Embodiment]

[Method for Producing Silicon Single Crystal]

Next, a method for manufacturing a silicon single crystal (SM) according to an embodiment of the present invention will be described.

In addition, in this embodiment, although the case of manufacturing the silicon single crystal (SM) whose diameter of the linear part after cylindrical grinding is 300 mm is exemplified, the diameter after cylindrical grinding may be 200 mm or 450 mm or other sizes. good. In addition, the dopant for resistivity adjustment may or may not be added to the silicon melt (M).

The manufacturing method of the silicon single crystal SM is, as shown in FIG. 2, the process (step S1) of implementing the gap size determination method at the time of manufacture of the silicon single crystal SM, and the manufacturing gap size determined by this determination method. A process of manufacturing a silicon single crystal (SM) for a product by applying (step S2: manufacturing process) is performed. Hereinafter, each process is demonstrated in detail.

In the step of performing the gap size determination method, first, the size of the gap GP between the lower end of the heat shield 25 and the surface of the silicon melt M (hereinafter, the size of the gap GP is referred to as “gap size”) ), the relationship between the defect distribution of the silicon single crystal SM and the pulling rate of the silicon single crystal SM is simulated (step S11: simulation process).

In addition, the gap size is the distance between the lower end of the heat shield 25 and the surface of the silicon melt M at the time of manufacture of the silicon single crystal SM.

The simulation process is performed with respect to at least the linear part SM1 of the silicon single crystal SM. Even with the same gap size, the defect distribution will differ depending on the position in the longitudinal direction of the linear body part SM1 by the influence of the change, etc. of the thermal history of the silicon single crystal SM during pulling-up. For this reason, it is preferable to perform a simulation process with respect to several places along the longitudinal direction of linear body part SM1. In this embodiment, a simulation process is performed about the area|region which divided linear body part SM1 into 3 equal in the longitudinal direction. Among the regions divided into three parts, the upper region in the impression direction is called the top region, the central region is called the middle region, and the lower region is called the bottom region.

According to this simulation process, a defect distribution with the distance from the center of the silicon single crystal SM as the horizontal axis and the pulling speed V as the vertical axis can be obtained. An example of the simulation result from which only the gap size in linear body part SM1 differs is shown in FIG.3 and FIG.4. 3 to 5, the left end of the horizontal axis indicates the central position of the silicon single crystal SM, and the right end indicates the position of the outer edge. 3 to 7 are diagrams relating to the middle region of the silicon single crystal (SM).

A simulation process can be made into simulation by experiment other than computer simulation by numerical calculation. Computer simulation by numerical calculation, which can save cost and time required for simulation, is preferable.

Next, based on the result of the simulation process, the defect-free margin as shown in FIGS. 3 and 4 is specified (step S12: defect-free margin specifying process). The defect-free margin means a margin of the pulling rate at which a silicon single crystal SM having only a defect-free region is obtained. The defect-free margin is the range from the lowest position of the OSF-Pv boundary line between the OSF region and the defect-free region to the highest position of the Pi-L/D boundary line between the defect-free region and the L/D region.

Thereafter, the defect distribution obtained in the simulation process is digitized, and the first relationship between the value of this defect distribution, the defect-free margin specified in the defect-free margin specifying process, and the gap size is specified (step S13: first relationship specification) fair).

In the present embodiment, first, the gap size at which the defect free margin becomes the maximum (hereinafter, the gap size at which the defect free margin becomes the maximum may be referred to as "provisional gap size") is specified. The defect-free margin changes according to the gap size. For example, when a graph is created with the gap size on the horizontal axis and the size of the defect-free margin on the vertical axis, it becomes a mountain-shaped graph. That is, there is only one gap size at which the defect-free margin becomes the maximum. Then, based on the some simulation result which changed only the gap size with respect to the same location, a temporary gap size is specified.

Next, for example, the generation of the OSF region when the silicon single crystal SM _{is pulled up at the same speed V 1} as the OSF region exists based on the defect distribution of the temporary gap size with the gap size as shown in FIG. 5 . figure out the situation In a silicon wafer obtained from this silicon single crystal SM, a disk-shaped (circular) OSF region including the center thereof exists. A ring-shaped OSF area exists outside this disk-shaped OSF area|region with a defect-free area|region interposed therebetween.

Next, the radius of the disk-shaped OSF region and the width of the ring-shaped OSF region are obtained as the disk radius and the ring width, respectively. In addition, the disk radius and ring width in the case of manufacturing a silicon single crystal (SM) at different pulling rates as in the presence of the OSF region are obtained. That is, the defect distribution obtained in the simulation process is digitized.

Further, based on the defect distribution when the gap size is 1 mm larger than the temporary gap size and the defect distribution when the temporary gap size is 1 mm smaller than the temporary gap size, the disk radius and the ring width when pulled at a plurality of pulling speeds are obtained.

Then, based on the defect distribution shown in Fig. 5, comparison data as shown in Fig. 6 is created with the disk radius as the horizontal axis and the disk ring ratio obtained by dividing the ring width by the disk radius as the vertical axis. This comparative data is a numerical value of the defect distribution obtained in the simulation (disk radius, disk ring ratio), the defect free margin (maximum defect free margin) obtained in the simulation, and the gap size (provisional gap size, provisional gap size ± 1 mm). ) represents the first relationship.

This comparison data is created for each of the top region, the middle region, and the bottom region. A computer may perform preparation of comparison data, and an operator may perform it.

Next, the gap size of the pulling apparatus 1 is set to the temporary gap size, and the silicon single crystal SM for evaluation is manufactured (step S14: single crystal manufacturing process for evaluation).

In the single crystal manufacturing process for evaluation, when the top region, the middle region, and the bottom region are manufactured, the gap size is set to the temporary gap size corresponding to each region, and the pulling speed is set in each region. Ring-shaped and disk-shaped OSF regions exist in each region. Set at the same speed as described above. As the speed at which the ring-shaped and disk-shaped OSF regions exist, for example, as shown in FIG. 5 , the gap size is based on the defect distribution of the temporary gap size, the speed V ₁ at which the OSF region exists, etc. may be set or may be set based on past manufacturing results.

In this embodiment, a plurality of silicon single crystals SM for evaluation in which ring-shaped and disk-shaped OSF regions exist are manufactured.

Next, the defect distribution of the silicon single crystal for evaluation is digitized in the same way as the defect distribution obtained in the simulation, and the second relationship between the value of this defect distribution and the gap size at the time of manufacturing the silicon single crystal for evaluation is specified ( Step S15: second relationship specifying step).

In the present embodiment, first, a silicon wafer is obtained from the straight body portion SM1 of the silicon single crystal SM for evaluation, and a process for making the OSF region visible is performed. As this facilitation process, after performing heat treatment for 3 hours in 1000 degreeC oxygen atmosphere, performing heat processing for 2 hours in 1150 degreeC oxygen atmosphere can be illustrated further. After that, the ring width and disk radius of the visualized OSF area are measured. The above process is performed with respect to the silicon wafer acquired from each area|region in the several silicon single crystal SM for evaluation. In addition, the number of silicon wafers acquired from each area|region may be one at a time, and may be sufficient as multiple sheets each. In addition, only one silicon single crystal SM for evaluation may be manufactured, and a plurality of silicon wafers may be obtained from this silicon single crystal SM.

Then, the relationship between the disk radius and the disk ring ratio based on the measurement result of each silicon wafer is specified. That is, the second relationship between the numerical value (disk radius, disk ring ratio) of the defect distribution of the silicon single crystal SM for evaluation and the gap size at the time of manufacturing the silicon single crystal SM for evaluation is specified.

Thereafter, based on the first relation and the second relation, the defect-free margin at the time of manufacturing the silicon single crystal SM for evaluation is estimated, and a manufacturing gap size that is larger than the estimated defect-free margin is determined (step S16: Manufacturing gap size determination process).

In the present embodiment, first, the first relationship and the second relationship indicated by the comparison data are compared to determine whether or not the defect-free margin is in the largest state during the production of the silicon single crystal SM for evaluation. Since both of these comparisons are data obtained based on the occurrence of OSF, they correspond to the simulation result and the defect distribution of the silicon single crystal SM for evaluation.

For example, as shown in FIG. 7, the measurement result (manufacturing performance (second relationship)) of the OSF area|region in each silicon wafer is plotted on the comparative data of FIG. When silicon single crystals (SM) are manufactured under the same manufacturing conditions, the measurement results of the OSF region of the silicon wafer obtained therefrom will be the same. There are different cases.

And when this measurement result substantially agrees with the comparative data in the provisional gap size, it is estimated that the defect-free margin was in the largest state, and the provisional gap size is determined as a manufacturing gap size. On the other hand, when a measurement result deviates from the comparison data by a predetermined amount, it is estimated that the defect-free margin was not in the largest state, and sizes other than a temporary gap size are determined as a manufacturing gap size.

For example, the reference approximation line L _{S of the comparison data in the temporary gap size, the first comparison approximate line L 1} of the comparison data when the temporary gap size is 1 mm larger than the temporary gap size, and the second comparison data when the temporary gap size is 1 mm smaller The comparative approximation line L ₂ and the performance approximation line N of the measurement result of a silicon wafer are calculated|required. And the manufacturing gap size is determined based on the distance of each approximate line L _S , L ₁ , L _{2 and the performance approximation line N.}

In the result shown in FIG. 7, the performance approximation line N is located substantially in the middle of the _{reference approximation line L S} and the 1st comparison approximation line L _{1 .} In this case, it is estimated that the manufacturing conditions at the time of applying the temporary gap size in the pulling apparatus 1 correspond to the manufacturing conditions at the time of applying the size 0.5 mm larger than the temporary gap size in simulation. According to this estimation result, it is thought that the manufacturing conditions at the time of applying the size 0.5 mm smaller than the temporary gap size correspond to the manufacturing conditions at the time of applying a temporary gap size in simulation. Therefore, a size 0.5 mm smaller than the temporary gap size is determined as the manufacturing gap size.

In addition, when the performance approximation line N is _{located between the reference approximation line L S} and the second comparison approximation line L ₂ , the size corresponding to the distance between the performance approximation line N and the reference approximation line L _{S is larger than the temporary gap size} is determined as the manufacturing gap size. For example, when the performance approximation line N is located at the position of "0.3" when the position of the reference approximation line L _S is set to "0" and the position of the second comparison approximation line L _{2 is set to "1"} , a size 0.3 mm larger than the temporary gap size is determined as the manufacturing gap size.

The production conditions, when the other hand, in the case that the results approximate line N approximated closely match the line L _S criteria, the production conditions of applying the gagaep size in the pulling apparatus 1 is applied to gagaep size in the simulation It is estimated that it is significant, and the temporary gap size is determined as the manufacturing gap size.

As described above, by determining the manufacturing gap size so that the performance approximation line N _{coincides with the reference approximation line L S} , the defect-free margin becomes the largest manufacturing condition.

This manufacturing gap size determination process is performed with respect to each of a top area|region, a middle area|region, and a bottom area|region. A computer may perform a manufacturing gap size determination process, and an operator may perform it.

Incidentally, in the above processing, the manufacturing gap size was determined based on the existence condition of the ring-shaped and disk-shaped OSF regions. You can decide the size. In this case, the pulling speed at the time of manufacturing a silicon single crystal (SM) for simulation or evaluation may be set to a _{speed V 2 or the like at which the ring-shaped and disk-shaped Pv regions are generated.} Examples of the treatment for making the Pv region present include performing heat treatment for 3 hours in an oxygen atmosphere at 780°C and then performing heat treatment for 16 hours in an oxygen atmosphere at 1000°C.

Thereafter, a manufacturing process (step S2) is performed.

In the manufacturing process, the silicon single crystal SM for a product is manufactured using the manufacturing gap size determined by the process of step S1 at the time of each manufacture of a top region, a middle region, and a bottom region.

[Operation and Effects of the Embodiment]

According to the above embodiment, in the manufacturing gap size determination step, the size of the defect-free margin when the silicon single crystal (SM) for evaluation is manufactured is estimated, and the gap size for making the defect-free margin larger than the estimated size is determined. Determined as the manufacturing gap size. By using this manufacturing gap size in the manufacturing process, the silicon single crystal SM for products can be manufactured in a state with a defect-free margin larger than that at the time of manufacturing the silicon single crystal SM for evaluation. Therefore, even if a pulling speed|rate changes, it can suppress that a pulling speed|rate becomes outside the range of a defect-free margin, and it can obtain many silicon wafers in which only a defect-free area|region exists.

In particular, in this embodiment, by using the manufacturing gap size that maximizes the defect-free margin for manufacturing, the allowable value for the change in the pulling rate can be maximized, and more silicon wafers having only the defect-free region can be obtained. have.

In the manufacturing gap size determination process, the manufacturing gap size can be easily determined based on the position of the performance approximation line N with respect to the _{reference approximation line L S} , the first and second comparison approximation lines L ₁ , and the comparison approximation line L _{2 .} have.

[Variation]

In addition, this invention is not limited only to the said embodiment, Various improvement, a change of design, etc. are possible within the range which does not deviate from the summary of this invention.

For example, although the method for determining the gap size and the method for manufacturing a silicon single crystal in manufacturing a silicon single crystal were performed for each of the top region, the middle region, and the bottom region of the straight body portion SM1, only one or two regions were used. You may perform it, and you may carry out with respect to the area|region which divided|segmented linear body part SM1 into two or four or more in the longitudinal direction.

In the manufacturing gap size determination process, _{although the manufacturing gap size was determined based on the distance of each approximate line L S} , L ₁ , L ₂ and the performance approximation line N, 1st, 2nd comparative approximate line L ₁ , L ₂ You may determine the manufacturing gap size based only on the comparison of the reference approximation line L _{S and the performance approximation line N without calculating|requiring .}

_{In the manufacturing gap size determination process, a first comparative approximate line L 1} was obtained based on the defect distribution when the gap size is 1 mm larger than the temporary gap size, but larger than the temporary gap size by another size such as 0.5 mm or 2 mm Based on the defect distribution in this case, you may obtain|require the 1st comparison approximation line L ₁ . The second comparison approximation line L ₂ may also be obtained in the same manner.

In the manufacturing gap size determination process, in addition to the first and second comparative approximate lines L ₁ , L ₂ , based on the defect distribution when the gap size is larger than the temporary gap size, for example, by 2 mm and smaller by 2 mm, The third and fourth comparison approximation lines may be obtained, and the manufacturing gap size may be determined using the third and fourth comparison approximation lines as well.

In the production gap size determination step, only a comparison of each approximation line L _S, L _1, L _2, without obtaining the N, each approximation line L _S, L _1, L _2, plot data based on the preparation of N, manufactured gap You can decide the size.

The manufacturing gap size may not be the gap size at which the defect-free margin becomes the largest when at least the defect-free margin becomes larger than at the time of manufacturing a silicon single crystal (SM) for evaluation. For example, when the result shown in FIG. 7 was obtained, although the size 0.5 mm smaller than the temporary gap size was determined as a manufacturing gap size, you may determine the size small 0.3 mm as a manufacturing gap size.

In the manufacturing gap size determination process, the manufacturing gap size was determined based on comparative data with the disk radius as the horizontal axis and the disk ring ratio divided by the ring width divided by the disk radius as the vertical axis. You can use it. As a combination of the indices of the horizontal axis and the vertical axis, a disk radius, a ring width, and the like can be exemplified.

Example

Next, although an Example and a comparative example demonstrate this invention further in detail, this invention is not limited at all by these examples.

[Experiment 1]

Using the manufacturing gap size determined based on FIG. 7 in the said embodiment, a plurality of silicon single crystals SM for evaluation in which ring-shaped and disk-shaped OSF regions exist were manufactured. Then, the disk radius and disk ring ratio of a plurality of wafers obtained from the silicon single crystal (SM) for evaluation were calculated, and their relationship was plotted on a graph shown in FIG. 6 .

The result is shown in FIG.

_{As shown in FIG. 9, the performance approximation line N 1} based on the measurement result of the silicon single crystal SM for evaluation manufactured with the manufacturing gap size approximates the performance of the silicon single crystal SM for evaluation manufactured with the provisional gap size. It has been confirmed that it is much closer to the _{reference approximation line L S} than to the line N .

In this regard, by using the manufacturing gap size obtained by the method for determining the gap size in manufacturing the silicon single crystal (SM) in the manufacturing process, the silicon single crystal (SM) for products is manufactured in a state in which the defect-free margin is enlarged. I could see what I could do.

[Experiment 2]

[Experimental Example 1]

{Comparative Example 1}

Steps S11 to S12 are performed on the premise of the pulling apparatus 1 having an A-type hot zone, and a temporary gap size is specified for each top region, middle region, and bottom region. (SM) was prepared. As the pulling rate of the silicon single crystal (SM) of Comparative Example 1, the median value within the defect-free margin in the simulation results to which the temporary gap size was applied was applied.

Thereafter, among the silicon single crystals SM of Comparative Example 1, a product region in which a silicon wafer (product wafer) having only a defect-free region can be obtained was specified. At this time, a silicon wafer is acquired from a plurality of positions in the longitudinal direction of the linear body SM1, a region sandwiched by the product wafer is used as a product region, and a silicon wafer (defective wafer) having an OSF region serving as a defect region is interposed between the silicon wafers. The area sandwiched between the slabs was defined as the defective product area.

Then, a value obtained by dividing the weight of the product area by the weight of the silicon raw material put into the crucible 22 was obtained as the yield of Comparative Example 1.

{Example 1}

Based on the occurrence of OSF in the defective wafer obtained from the silicon single crystal (SM) of Comparative Example 1, steps S13 to S14 were performed to determine the manufacturing gap size of the region in which the defective wafer was obtained. Then, using the pulling apparatus 1 having an A-type hot zone, a silicon single crystal SM of Example 1 was manufactured with a manufacturing gap size. As the pulling speed of the silicon single crystal (SM) of Example 1, the same speed as in Comparative Example 1 was applied.

Thereafter, the product region of the silicon single crystal (SM) of Example 1 was specified, and the yield of Example 1 was determined in the same manner as in Comparative Example 1.

[Experimental Example 2]

{Comparative Example 2, Example 2}

Comparative Examples 2 and 2 were obtained by performing the same processing as in Comparative Examples 1 and 1, respectively, except that the B-type pulling apparatus 1 was used instead of the A-type pulling apparatus 1 in the hot zone. yield was obtained.

〔evaluation〕

The value obtained by subtracting the yield of Comparative Example 1 from the yield of Example 1 was obtained as the yield effect of Experimental Example 1, and the value obtained by subtracting the yield of Comparative Example 2 from the yield of Example 2 was obtained as the yield effect of Experimental Example 2. The results are shown in FIG. 10 .

As shown in FIG. 10, also in any of Experimental Examples 1 and 2, it was confirmed that there existed 1% or more of the yield effect.

In this regard, it has been confirmed that a large number of product wafers can be obtained by using the manufacturing gap size obtained by the method for determining the gap size in manufacturing the silicon single crystal (SM) in the manufacturing process.

Claims (7)

A crucible for accommodating a silicon melt, a pulling part for pulling a silicon single crystal from the silicon melt, and a pulling device having a heat shield disposed above the crucible to surround the silicon single crystal during pulling When manufacturing a silicon single crystal using a pulling device A method for determining the gap size between the lower end of the heat shield and the surface of the silicon melt in
simulating the relationship between the defect distribution of the silicon single crystal and the pulling rate of the silicon single crystal for each gap size;
a step of specifying a margin of a pulling rate at which the silicon single crystal having only a defect-free region is obtained based on the result of the simulation;
The defect distribution obtained in the simulation is digitized by the ratio of the radius of the circular defect region in the wafer surface obtained from the silicon single crystal and the width of the ring-shaped defect region, and the value of this defect distribution and the margin of the pulling rate obtained in the simulation and specifying a first relationship between the gap size;
The defect distribution of the silicon single crystal for evaluation produced using the pulling apparatus is digitized in the same way as the defect distribution obtained in the simulation, and the value of this defect distribution and the gap size at the time of manufacturing the silicon single crystal for evaluation are quantified. specifying a second relationship;
a step of estimating a pulling rate margin at the time of manufacturing the silicon single crystal for evaluation based on the first relation and the second relation, and determining the gap size that is larger than the estimated pulling rate margin; A method of determining the gap size characterized in that it is carried out. delete delete A crucible for accommodating a silicon melt, a pulling part for pulling a silicon single crystal from the silicon melt, and a pulling device having a heat shield disposed above the crucible to surround the silicon single crystal during pulling When manufacturing a silicon single crystal using a pulling device A method for determining the gap size between the lower end of the heat shield and the surface of the silicon melt in
simulating the relationship between the defect distribution of the silicon single crystal and the pulling rate of the silicon single crystal for each gap size;
a step of specifying a margin of a pulling rate at which the silicon single crystal having only a defect-free region is obtained based on the result of the simulation;
Numericalizing the defect distribution obtained in the simulation and specifying a first relationship between the value of the defect distribution and the margin of the pulling speed obtained in the simulation and the gap size;
The defect distribution of the silicon single crystal for evaluation produced using the pulling apparatus is digitized in the same way as the defect distribution obtained in the simulation, and the value of this defect distribution and the gap size at the time of manufacturing the silicon single crystal for evaluation are quantified. specifying a second relationship;
a step of estimating a pulling rate margin at the time of manufacturing the silicon single crystal for evaluation based on the first relation and the second relation, and determining the gap size that is larger than the estimated pulling rate margin; carry out,
The defect distribution is a distribution of an OSF region or a distribution of a Pv region,
A method for determining a gap size, wherein the numerical value of the defect distribution is a ratio of a radius of a circular OSF region and a width of a ring-shaped OSF region, or a ratio of a radius of a circular Pv region and a width of a ring-shaped Pv region . delete A method for producing a silicon single crystal, wherein a silicon single crystal is produced using a gap size determined by the method for determining a gap size according to claim 1 or 4. 7. The method of claim 6,
The method of determining the gap size is a method of manufacturing a silicon single crystal, characterized in that the gap size is determined so that the margin of the pulling rate is the largest.

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